AM9512

AM9512 AMD | Alldatasheet

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Technical content

DISTINCTIVE CHARACTERISTICS

• Single (32-bit) and double (64-bit) precision capability
• Add, subtract, multiply and divide functions
• Compatible with proposed IEEE format
• Easy interfacing to microprocessors
• 8-bit data bus
• Standard 24-pin package
• 12V and 5V power supplies
• Stack oriented operand storage
• Direct memory access or programmed I/O Data Transfers
• End of execution signal
• Error interrupt
• All inputs and outputs TTL level compatible
• Advanced N-channel silicon gate MOS technology
• 100% MIL-STD-883 reliability assurance testing GENERAL DESCRIPTION The Am9512 is a high performance floating-point processor unit (FPU). It provides single precision (32-bit) and double precision (64-bit) add, subtract, multiply and divide operations. It can be easily interfaced to enhance the computational capabilities of the host microprocessor. The operand, result, status and command information transfers take place over an 8-bit bidirectional data bus. Operands are pushed onto an internal stack by the host processor and a com­ mand is issued to perform an operation on the data stack. The results of this operation are available to the host processor by popping the stack. Information transfers between the Am9512 and the host proces­ sor can be handled by using programmed I/O or direct memory access techniques. After completing an operation, the Am9512 activates an "end of execution" signal that can be used to inter­ rupt the host processor. BLOCK DIAGRAM Package Type Hermetic DIP TWO PORT DATA STACK

8 X 17

768 X 16

ORDERING INFORMATION

Ambient Maximum Clock Frequency Temperature 2MHz 3MHz O°C ",; T A ",; 70°C AM9512DC AM9512-1DC -55°C",; TA ",; +125°C AM9512DM AM9512-1DM 7-91 ERR SVACK SVREQ EACK END INTERFACE RESET CONTROL C/O cs AD WR PAUSE 1.405·203

Note: Pin 1 is marked for orientation. INTERFACE SIGNAL DESCRIPTION VCC: +5V Power Supply VDD: +12V Power Supply VSS: Ground ClK (Clock, Input) MOS·204 An external timing source connected to the ClK input provides the necessary clocking. RESET (Reset, Input) A HIGH on this input causes initialization. Reset terminates any operation in progress, and clears the status register to zero. The internal stack pointer is initialized and the contents of the stack may be affected. After a reset the END output, the ERR output and the SVREQ output will be lOW. For proper initialization, RESET must be HIGH for at least five ClK periods following stable power supply voltages and stable clock. C/O (Command/Data Select, Input) The c/is input together with the RD and WR inputs determines the type of transfer to be performed on the data bus as follows: C/D l l H H X L = LOW H = HIGH RD H l H l l X = DON'T CARE WR Function l Push data byte into the stack H Pop data byte from the stack l Enter command H Read Status l Undefined END (End of Execution, Output) A HIGH on this output indicates that execution of the current command is complete. This output will be cleared lOW by ac­ tivating the EACK input lOW or performing any read or write operation or device initialization using the RESET. If EACK is tied lOW, the END output will be a pulse (see EACK description). Reading the status register while a command execution is in progress is allowed. However any read or write operation clears the flip-flop that generates the END output. Thus such continu­ ous reading could conflict with internal logic setting of the END flip-flop at the end of command execution. EACK (End Acknowledge, Input) This input when lOW makes the END output go lOW. As men­ tioned earlier HIGH on the END output signals completion of a command execution. The END signal is derived from an internal flip-flop which is clocked at the completion of a command. This flip-flop is clocked to the reset state when EACK is lOW. Con­ sequently, if EACK is tied lOW, the END output will be a pulse that is approximately one ClK period wide. SVREQ (Service Request, Output) A HIGH on this output indicates completion of a command. In this sense this output is the same as the END output. However, the SVREQ output will go HIGH at the completion of a com­ mand. This bit must be 1 for SVREQ to go HIGH. The SVREQ can be cleared (Le., go lOW) by activating the SVACK input lOW or initializing the device using the RESET. Also, the SVREQ will be automatically cleared after completion of any command that has the service request bit as o. SVACK (Service Acknowledge, Input) A lOW on this input clears SVREQ. If the SVACK input is per­ manently tied lOW, it will conflict with the internal setting of the SVREQ output. rhus the SVREQ indication cannot be relied upon if the SVACK is tied lOW. DBO-DB7 (Data Bus, Input/Output) These eight bidirectional lines are used to transfer command, status and operand information between the device and the host processor. DBO is the least significant and DB7 is the most significant bit position. HIGH on a data bus line corresponds to 1 and lOW corresponds to O. When pushing operands on the stack using the data bus, the least significant byte must be pushed first and most significant byte last. When popping the stack to read the result of an operation, the most Significant byte will be available on the data bus first and the least significant byte will be the last. Moreover, for pushing operands and popping results, the number of transactions must be equal to the proper number of bytes appropriate for the chosen format. Otherwise, the internal byte pointer will not be aligned properly. The Am9512 single precision format requires 4 bytes and double precision format requires 8 bytes. ERR (Error, Output) This output goes HIGH to indicate that the current command execution resulted in an error condition. The error conditions are: attempt to divide by zero, exponent overflow and exponent underflow. The ERR output is cleared lOW on read status reg­ ister operation or upon RESET. The ERR output is derived from the error bits in the status register. These error bits will be updated internally at an appro­ priate time during a command execution. Thus ERR output going HIGH may not correspond with the completion of a command. Reading of the status register can be performed while a com­ mand execution is in progress. However it should be noted that reading the status register clears the ERR output. Thus reading the status register while a command execution in progress may result in an internal conflict with the ERR output. 7-92

CS (Chip Select, Input) This input must be LOW to accomplish any read or write operation to the Am9512. To perform a write operation, appropriate data is presented on DBO through DB7 lines, appropriate logic level on the C/O input and the CS input is made LOW. Whenever WR and RD inputs are both HIGH and CS is LOW, PAUSE goes LOW. However actual writing into the Am9512 cannot start until WR is made LOW. After initiating the write operation by the HIGH to LOW transition on the WR input, the PAUSE output will go HIGH indicating the write operation has been acknowledged. The WR input can go HIGH after PAUSE goes HIGH. The data lines, C/O input and the CS input can change when appropriate hold time requirements are satisfied. See 'tJrite timing diagram for details. To perform a read operation an appropriate logic level is estab­ lished on the cio input and CS is made LOW. The PAUSE output goes LOW because WR and RD inputs are HIGH. The read operation does not start until the RD input goes LOW. PAUSE will go HIGH indicating that read operation is complete and the re­ quired information is available on the DBO through DB7lines. This information will remain on the data lines as long as RD is LOW. The RD input can return HIGH anytime after PAUSE goes HIGH. The CS input and C/O input can change anytime after RD returns HIGH. See read timing diagram for details. If the CS is tied LOW permanently, PAUSE will remain LOW until the next Am9512 read or write access. RD (Read, Input) A LOW on this input is used to read information from an internal location and gate that information onto the data bus. The CS input must be LOW to accomplish the read operation. The cio input determines what internal location is of interest. See C/O, CS input descriptions and read timing diagram for details. If the END FUNCTIONAL DESCRIPTION Major functional units of the Am9512 are shown in the block diagram. The Am9512 employs a microprogram controlled stack oriented architecture with 17-bit wide data paths. The Arithmetic Unit receives one of its operands from the Operand Stack. This stack is an eight word by 17-bit two port memory with last in - first out (LIFO) attributes. The second operand to the Arithmetic Unit is supplied by the internal 17-bit bus. In addition to supplying the second operand, this bidirec­ tional bus also carries the results from the output of the Arithmetic Unit when required. Writing into the Operand Stack takes place from this internal 17-bit bus when required. Also connected to this bus are the Constant ROM and Working Registers. The ROM provides the required constants to perform the mathematical operations while the Working Registers provide storage for the intermediate values during command execution. Communication between the external world and the Am9512 takes place on eight bidirectional input/output lines, DBO through COMMAND FORMAT The Operation of the Am9512 is controlled from the host proces­ sor by issuing instructions called commands. The command for­ mat is shown below: OP CODE I I The command consists of 8 bits; the least significant 7 bits specify the operation to be performed as detailed in the accompanying Am9512 output was HIGH, performing any read operation will make the END output go LOW after the HIGH to LOW transition of the RD input (assuming CS is LOW). If the ERR output was HIGH per­ forming a status register read operation will make the ERR out­ put LOW. This will happen after the HIGH to LOW transition of the RD input (assuming CS is LOW). WR (Write, Input) A LOW on this input is used to transfer information from the data bus into an internal location. The CS must be LOW to accomplish the write operation. The cio determines which internal location is to be written. See C/O, CS input descriptions and write timing diagram for details. If the END output was HIGH, performing any write operation will make the END output go LOW after the LOW to HIGH transitionaf the WR input (assuming CS is LOW). PAUSE (Pause, Output) This output is a handshake signal used while performing read or write transactions with the Am9512. If the WR and RD inputs are both HIGH, the PAUSE output goes LOW with the CS input in anticipation of a transaction. If WR goes LOW to initiate a write transaction with proper signals established on the DBO-DB7, C/O inputs, the PAUSE will return HIGH indicating that the write operation has been accomplished. The WR can be made HIGH after this event. On the other hand, if a read operation is desired, the RD input is made LOW after activating CS LOW and estab­ lishing proper cio input. (The PAUSE will go LOW in response to CS going LOW.) The PAUSE will return HIGH indicating comple­ tion of read. The RD can return HIGH after this event. It should be noted that a read or write operation can be initiated without any regard to whether a command execution is in progress or not. Proper device operation is assured by obeying the PAUSE output indication as described. DB7 (Data Bus). These signals are gated to the internal 8-bit bus through appropriate interface and buffer circuitry. Multiplexing facilities exist for bidirectional communication between the inter­ nal eight and 17-bit buses. The Status Register and Command Register are also located on the 8-bit bus. The Am9512 operations are controlled by the microprogram contained in the Control ROM. The Program Counter supplies the microprogram addresses and can be partially loaded from the Command Register. Associated with the Program Counter is the Subroutine Stack where return addresses are held during sub­ routine calls in the microprogram. The Microinstruction Register holds the current microinstruction being executed. The register facilitates pipelined microprogram execution. The Instruction De­ code logic generates various internal control signals needed for the Am9512 operation. The Interface Control logic receives several external inputs and provides handshake related outputs to facilitate interfacing the Am9512 to microprocessors. table. The most significant bit is the Service Request Enable bit. This bit must be a 1 if SVREQ is to go high at end of executing a command. The Am9512 commands fall into three categories: Single preci­ sion arithmetic, double precision arithmetic and data manipula­ tion. There are four arithmetic operations that can be performed with single precision (32-bit), or double precision (54-bit) floating-point numbers: add, subtract, multiply and divide. These operations require two operands. The Am9512 assumes that these operands are located in the internal stack as Top of Stack 7-93

the operands. The results will be rounded to preserve the accu- register and operand formats. Table 1. Command Decoding Table. x 0 0 0 0 0 0 1 SADD Add TOS to NOS Single Precision and result to NOS. Pop stack. X 0 0 0 0 0 1 0 SSUB Subtract TOS from NOS Single Precision and result to NOS. Pop stack. X 0 0 0 0 0 1 1 SMUL Multiply NOS by TOS Single Precision and result to NOS. Pop stack. X 0 0 0 0 1 0 0 SDIV Divide NOS by TOS Single Precision and result to NOS. Pop stack. X 0 0 0 0 1 0 1 CHSS Change sign of TOS Single Precision operand. X 0 0 0 0 1 1 0 PTOS Push Single Precision operand on TOS to NOS. X 0 0 0 0 1 1 1 POPS Pop Single Precision operand from TOS. NOS becomes TOS. X 0 0 0 1 0 0 0 XCHS Exchange TOS with NOS Single Precision. X 0 1 0 1 1 0 1 CHSD Change sign of TOS Double Precision operand. X 0 1 0 1 1 1 0 PTOD Push Double Precision operand on TOS to NOS. X 0 1 0 1 1 1 1 POPD Pop Double Precision operand from TOS. NOS becomes TOS. X 0 1 0 1 0 0 1 DADD Add TOS to NOS Double Precision and result to NOS. Pop stack. X 0 1 0 1 0 1 0 DSUB Subtract TOS from NOS Double Precision and result to NOS. Pop stack. X 0 1 0 1 0 1 1 DMUL Multiply NOS by TOS Double Precision and result to NOS. Pop stack. X 0 1 0 1 1 0 0 DDIV Divide NOS by TOS Double Precision and result to NOS. Pop Stack. Notes: X = Don't Care Operation for bit combinations not listed above is undefined. Table 2. Am9S12 Execution Time in Cycles. maximum execution time of 1000 executions with random 32-bit or 64-bit patterns. Table 3. Some Execution Examples. Note: TOS, NOS and Result are in hexadecimal; Clock period is in decimal.

After properly positioning the required operands in the stack, a command may be issued. The procedure for initiating a command execution is as follows: 1. Establish appropriate command on the DBO-DB7 lines. 2. Establish HIGH on the C/O input. 3. Establish LOW on the CS input. Whenever WR and RD inputs are HIGH the PAUSE output follows the CS input. Hence PAUSE will become LOW. 4. Establish LOW on the WR input after an appropriate set up time (see timing diagrams). 5. Sometime after the HIGH to LOW level transition of WR input, the PAUSE output will become HIGH to acknowledge the write operation. The WR input can return to HIGH anytime after PAUSE goes HIGH. The DBO-DB7, C/O and CS inputs are allowed to change after the hold time requirements are satis­ fied (see timing diagram). An attempt to issue a new command while the current command execution is in progress is allowed. Under these circumstances, the PAUSE output will not go HIGH until the current command execution is completed. OPERAND ENTRY The Am9512 commands operate on the operands located at the TOS and NOS and results are returned to the stack at NOS and then popped to TOS. The operands required for the Am9512 are one of two formats - single precision floating-point (4 bytes) or double precision floating-point (8 bytes). The result of an opera­ tion has the same format as the operands. In other words, op­ erations using single precision quantities always result in a Single precision result while operations involving double preci­ sion quantities will result in double precision result. Operands are always entered into the stack least significant byte first and most significant byte last. The following procedure must be followed to enter operands into the stack: 1. The lower significant operand byte is established on the DBO-DB7 lines. 2. A LOW is established on the cio input to specify that data is to be entered into the stack. 3. The CS input is made LOW. Whenever the WR and RD inputs are HIGH, the PAUSE output will follow the CS input. Thus PAUSE output will become LOW. 4. After appropriate set up time (see timing diagrams), the WR input is made LOW. 5. Sometime after this event, PAUSE will return HIGH to indi­ cate that the write operation has been acknow~ed. 6. Anytime after the PAUSE output goes HIGH the WR input can be made HIGH. The DBO-DB7, C/O and CS inputs can change after appropriate hold time requirements are satisfied (see timing diagrams). The above procedure must be repeated until all bytes of the operand are pushed into the stack. It should be noted that for single precision operands 4 bytes should be pushed and 8 bytes must be pushed for double precision. Not pushing all the bytes of a quantity will result in byte pointer misalignment. The Am9512 stack can accommodate 4 single precision quan­ tities or 2 double precision quantities. Pushing more quantities than the capacity of the stack will result in loss of data which is usual with any LIFO stack. REMOVING THE RESULTS Result from an operation will be available at the TOS. Results can be transferred from the stack to the data bus by reading the stack. 7-95 Am9512 When the stack is popped for results, the most significant byte is available first and the least significant byte last. A result is always of the same preCision as the operands that produced it. Thus when the result is taken from the stack, the total number of bytes popped out should be appropriate with the precision - Single precision results are 4 bytes and double precision results are 8 bytes. The following prodedure must be used for reading the result from the stack: 1. A LOW is established on the C/O input. 2. The CS input is made LOW. When WR and RD inputs are both HIGH, the PAUSE output follows the CS input, thus PAUSE will be LOW. 3. After appropriate set up time (see timing diagrams), the RD input is made LOW. 4. Sometime after this, PAUSE will return HIGH indicating that the data is available on the DBO-DB7 lines. This data will remain on the DBO-DB7 lines as long as the RD input remains LOW. 5. Anytime after PAUSE goes HIGH, the RD input can return HIGH to complete transaction. 6. The CS and C/O inputs can change after appropriate hold time requirements are satisfied (see timing diagram). 7. Repeat this procedure until all bytes appropriate for the preci- sion of the result are popped out. Reading of the stack does not alter its data; it only adjusts the byte pointer. If more data is popped than the capacity of the stack, the internal byte pointer will wrap around and older data will be read again, consistent with the LIFO stack. READING STATUS REGISTER The Am9512 status register can be read without any regard to whether a command is in progress or not. The only implication that has to be considered is the effect this might have on the END and ERR outputs discussed in the signal descriptions. The following procedure must be followed to accomplish status register reading. 1. Establish HIGH on the C/O input. 2. Establish LOW on the CS input. Whenever WR and RD in­ puts are HIGH, PAUSE will follow the CS input. Thus, PAUSE will go LOW. 3. After appropriate set up time (see timing diagram) RD ~s made LOW. 4. Sometime after the HIGH to LOW transition of RD, PAUSE will become HIGH indicating that status register contents are available on the DBO-DB7 lines. These lines will contain this information as long as RD is LOW. 5. The RD input can be returned HIGH anytime after PAUSE goes HIGH. 6. The C/O input and CS input can change after satisfying ap­ propriate hold time requirements (see timing diagram). DATA FORMATS The Am9512 handles floating-point quantities in two different formats - single precision and double preCision. The single pre­ cision quantities are 32-bits long as shown below. F'·""D'" I M 31 30 23 22 Bit 31: S = Sign of the mantissa. 1 represents negative and 0 repre­ sents positive.

E = These a-bits represent a biased exponent. The bias is 27 -1 = 127 Bits 0-22 M = 23-bit mantissa. Together with the sign bit, the mantissa represents a signed fraction in sign-magitude notation. There is an implied 1 beyond the most significant bit (bit 22) of the mantissa. In other words, the mantissa is assumed to be a 24-bit normalized quantity and the most significant bit which will always be 1 due to normalization is implied. The Am9512 restores this implied bit internally before performing arithmetic; normalizes the result and strips the implied bit before returning the results to the external data bus. The binary pOint is between the implied bit and bit 22 of the mantissa. The quantity N represented by the above notation is r-----Bias J-. r-Binary Point Provided E -j; 0 or all 1 'so A double precision quantity consists of the mantissa sign bit(s), an 11 bit biased exponent (E), and a 52-bit mantissa (M). The bias for double precision quantities is 210 - 1. The double preCision format is illustrated below. F;MPUED'" M 63 62 52 51 Bit 63: S = Sign of the mantissa. 1 represents negative and 0 repre­ sents positive. Bits 52-62 E = These 11 bits represent a biased exponent. The bias is 210 - 1 = 1023. Bit 0-51 M = 52-bit mantissa. Together with the sign bit, the mantissa represents a signed fraction in sign-magnitude notation. There is an implied 1 beyond the most Significant bit (bit 51) of the mantissa. In other words, the mantissa is assumed to a 53-bit normalized quantity and the most significant bit, which will always be a 1 due to normalization, is implied. The Am9512 restores this implied bit internally before perform­ ing arithmetic; normalizes the result and strips the implied bit before returning the result to the external data bus. The binary pOint is between the implied bit and bit 51 of the mantissa. The quantity N represented by the above notation is ... ---Bias , -- r--Binary point Provided E 1= 0 or all 1 'so 7-96 STATUS REGISTER The Am9512 contains an a-bit status register with the following format. Bit 0 and bit 4 are reserved. Occurrence of exponent oerflow (V), exponent underflow (U) and divide exception (D) are indicated by bits 1,2 and 3 respectively. An attempt to divide by zero is the only divide exception. Bits 5 and 6 represent a zero result and the sign of a result respectively. Bit 7 (Busy) of the status regis­ ter indicates if the Am9512 is currently busy executing a com­ mand. AI! the bits are initialized to zero upon reset. Also, executing a CLR (Clear Status) command will result in all zero status register bits. A zero in Bit 7 indicates that the Am9512 is not busy and a new command may be initiated. As soon as a new command is issued, Bit 7 becomes 1 to indicate the device is busy and remains 1 until the command execution is complete, at which time it will become O. As soon as a new command is issued, status register bits 0, 1, 2, 3, 4, 5 and 6 are cleared to zero. The status bits will be set as required during the command execution. Hence, as long as bit 7 is 1, the remainder of the status register bit indications should not be relied upon un­ less the ERR occurs. The following is a detailed status bit description. Bit 0 Reserved Bit 1 Exponent overflow (V): When 1, this bit indicates that exponent overflow has occurred. Cleared to zero otherwise. Bit 2 Exponent Underflow (U): When 1, this bit indicates that exponent underflow has occurred. Cleared to zero otherwise. Bit 3 Divide Exception (D): When 1, this bit indicates that an attempt to divide by zero is made. Cleared to zero otherwise. Bit 4 Reserved Bit 5 Zero (Z): When 1, this bit indicates that the result returned to TOS after a command is all zeros. Cleared to zero otherwise. Bit 6 Sign (S): When 1, this bit indicates that the result returned to TOS is negative. Cleared to zero otherwise. Bit 7 Busy: When 1, this bit indicates the Am9512 is in the process of executing a command. It will become zero after the command execution is complete. All other status register bits are valid when the Busy bit is zero. ALGORITHMS OF FLOATING-POINT ARITHMETIC 1. Floating Point to Decimal Conversion As an introduction to floating-point arithmetic, a brief descrip­ tion of the Decimal equivalent of the Am9512 floating-point format should help the reader to understand and verify the validity of the arithmetic operations. The Am9512 single preci­ sion format is used for the following discussions. With a minor modification of the field lengths, the discussion would also apply to the double precision format. There are three parts in a floating point number: a. The sign - the sign applies to the sign of the number. Zero means the number is positive or zero. One means the number is negative.

b. The exponent - the exponent represents the magnitude of the number. The Am9512 single precision format has an excess 12710 notation which means the code representa­ tion is 12710 higher than the actual value. The following are a few examples of actual versus coded exponent. Actual Coded +127 10 o -12610 +254 10 12710 +110 c. The mantissa - the mantissa is a 23-bit value with the binary point to the left of the most significant bit. There is a hidden 1 to the left of the binary point so the mantissa is always less than 2 and greater than or equal to 1. To find the Decimal equivalent of the floating point number, the mantissa is multiplied by 2 to the power of the actual exponent. The number is negated if the sign bit = 1. The following are two examples of conversion: Example 1 Floating Point No. = 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B Sign ~ Exponent Mantissa Coded Exponent = 1 0 0 0 0 0 1 1 B Actual Exponent = 1 0 0 0 0 0 1 1 B - 0 1 1 1 1 1 1 1 B = 0 0 0 0 0 1 0 0 B = 4'0 Mantissa = 1.1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B Decimal No. = 24 x 1.75 = 16 x 1.75 = 2BlO Example 2 Floating Point No. = 1 0 1 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B Sign ~ Exponent Mantissa Code Exponent = 0 1 1 1 1 0 1 0 B Actual Exponent = 0 1 1 1 1 0 1 0 B - 0 1 1 1 1 1 1 1 B = 1 1 1 1 1 0 1 1 B = - 510 Mantissa = 1.0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B Decimal No. = _2-5 x 1.375 = -.04296B75,0 2. Unpacking of the Floating-Point Numbers The Am9512 unpacks the floating point number into three parts before any of the arithmetic operation. The number is divided into three parts as described in Section 1. The sign and exponent are copied from the original number as 1 and 8-bit numbers respectively. The mantissa is stored as a 24-bit number. The least significant 23 bits are copied from the original number and the MSB is set to 1. The binary point is assumed to the right of the MSB. The abbreviations listed below are used in the following sec­ tions of algorithm description: SIGN - Sign of Result EXP - Exponent of Result MAN - Mantissa of Result SIGN (TOS) - Sign of Top of Stack EXP (TOS) - Exponent of Top of Stack MAN (TOS) - Mantissa of Top of Stack SIGN (NOS) - Sign of Next on Stack EXP (NOS) - Exponent of Next on Stack MAN (NOS) - Mantissa of Next on Stack 3. Floating-Paint Add/Subtract The floating-point add and subtract essentially use the same algorithm. The only difference is that floating-point subtract changes the sign of the floating-point number at top of stack and then performs the floating-point add. The following is a step by step description of a floating-point add algorithm (Figure 1): 7-97 Am9S12 a. Unpack TOS and NOS. b. The exponent of TOS is compared to the exponent of NOS. c. If the exponents are equal, go to step f. d. Right shift the mantissa of the number with t; ,~ smaller exponent. e. Increment the smaller exponent and go to step b. f. Set sign of result to sign of larger number. g. Set exponent of result to exponent of larger number. h. If sign of the two numbers are not equal, go to m. Add Mantissas. j. Right shift resultant mantissa by 1 and increment expo- nent of result by 1. k. If MSB of exponent changes from 1 to 0 as a result of the increment. set overflow status. Round if necessary and exit. m. Subtract smaller mantissa from larger mantissa. n. Left shift mantissa and decrement exponent of result. o. If MSB of exponent changes from 0 to 1 as a result of the decrement, set underflow status and exit. p. If the MSB of the resultant mantissa = 0, go to n. q. Round if necessary and exit. Floating-Point Multiply Floating-point multiply basically involves the addition of the exponents and multiplication of the mantissas. The following is a step by step description of a floating multiplication al- gorithm (Figure 2): a. Check if TOS or NOS = O. b. If either TOS or NOS = 0, Set result to 0 and exit. c. Unpack TOS and NOS. d. Convert EXP (TOS) and EXP (NOS) to unbiased form. EXP (TOS) = EXP (TOS) -12710 EXP (NOS) = EXP (NOS) -12710 e. Add exponents. EXP = EXP (TOS) + EXP (NOS) f. If MSB of EXP (TOS) = MSB of EXP (NOS) = 0 and MSB of EXP = 1, then set overflow status and exit. g. If MSB of EXP (TOS) = MSB of EXP (NOS) = 1 and MSB of EXP = 0, then set underflow status and exit. h. Convert Exponent back to biased form. EXP = EXP + 12710 If sign of TOS = sign of NOS, set sign of result to 0, else set sign of result to 1. j. Multiply mantissa. k. If MSB of resultant = 1, right shift mantissa by 1 and increment exponent of resultant. If MSB of exponent changes from 1 to 0 as a result of the increment, set overflow status. m. Round if necessary and exit. Floating-Point Divide The floating-point divide basically involves the subtraction of exponents and the division of mantissas. The following is a step by step description of a division algorithm (Figure 3). a. If TOS = 0, set divide exception error and exit. b. If NOS = 0, set result to 0 and exit. c. Unpack TOS and NOS. d. Convert EXP (TOS) and EXP (NOS) to unbiased form. EXP (TOS) = EXP (TOS) - 12710 EXP (NOS) = EXP (NOS) - 12710 e. Subtract exponent of TOS from exponent of NOS. EXP = EXP (NOS) - EXP (TOS) f. If MSB of EXP (NOS) = 0, MSB of EXP (TOS) = 1 and MSB of EXP = 1, then set overflow status and exit. g. If MSB of EXP (NOS) = 1, MSB of EXP (TOS) = 0, and MSB of EXP = 0, then set underflow status and exit.

Figure 1. Conceptual Floating-Point Addition/Subtraction. MOS·205 h. Add bias to exponent of result. j. Divide mantissa of NOS by mantissa of TOS. decrement, set underflow status. n. Round if necessary and exit. reflect the exact internal sequence of the Am9512. Dr. John F. Palmer of Intel Corporation.

Figure 2. Conceptual Floating-Point Multiplication. shifting in the Accumulator involves the OF, G, Rand ST bits. round the same way as addition of magnitudes. formed as in addition of magnitudes. rounding is then performed as in addition of magnitudes.

Figure 3. Conceptual Floating-Point Division.

05 IF SRE = 0

bits Sand Z indicate the sign of the result and if the result is zero. The status bits U, V and D are cleared to zero.

Binary Coding: ISREI 0 0 Hex Coding: 80 IF SRE = 1

00 IF SRE = 0

Execution Time: 4 clock cycles Description: 4 3 0 0 2 0 0 0 0 The status bits S, Z, D, U, V are cleared to zero. The stack is not affected. This essentially is a no operation command as far as operands are concerned. Status Affected: S, Z, D, U, V always zero. DADD DOUBLE PRECISION FLOATING-POINT ADD 7 6 5 Binary Coding: ISREI 0 Hex Coding: A9 IF SRE = 1

29 IF SRE = 0

Execution Time: See Table 2 Description: 4 3 2 0 0 0 0 The double precision operand A from TOS is added to the double precision operand B from NOS. The result is rounded to obtain the final double precision result R which is returned to TOS. The status bits S, Z, U and V are affected to report sign of the result, if the result is zero, exponent underflow and exponent overflow respectively. The status bit D will be cleared to zero. Status Affected: S, Z, U, V. (D always zero.) STACK CONTENTS BEFORE AFTER DSUB DOUBLE PRECISION FLOATING-POINT SUBTRACT 7 6 5 4 Binary Coding: ISRE I 0 1 0 Hex Coding: AA IF SRE = 1 2A IF SRE = 0 Execution Time: See Table 2 Description: 3 2 o Am9S12 o o The double precision operand A at TOS is subtracted from the double precision operand B at NOS. The result is rounded to obtain the final double precision result R which is returned to TOS. The status bits S, Z, U and V are affected to report sign of the result, if the result is zero, exponent underflow and exponent overflow respectively. The status bit D will be cleared to zero. Status Affected: S, Z, U, V. (D always zero.) STACK CONTENTS BEFORE AFTER B ~ ~ Undefined DMUL DOUBLE PRECISION FLOATING-POINT MULTIPLY 7 6 5 4 Binary Coding: ISREI 0 0 Hex Coding: AB IF SRE = 1 2B IF SRE = 0 Execution Time: See Table 2 Description: 3 2 o o The double precision operand A from TOS is multiplied by the double precision operand B from NOS. The result is rounded to obtain the final double precision result R which is returned to TOS. The status bits S, Z, U and V are affected to report sign of the result, if the result is zero, exponent underflow and exponent overflow respectively. The status bit D will be cleared to zero. Status Affected: S, Z, U, V. (D always zero.) STACK CONTENTS . B ~ ~ Undefined 7-101

Binary Code: ISREI ° Hex Coding: AC IF SRE = 1 2C IF SRE = ° Execution Time: See Table 2 Description: 4 3 2 ° ° ·0 The double precision operand B from NOS is divided by the double precision operand A from TOS. The result (quotient) is rounded to obtain the final double precision result R which is returned to TOS. The status bits, S, Z, 0, U and V are affected to report sign of the result, if the result is zero, attempt to divide by zero, exponent underflow and exponent overflow respectively. Status Affected: S, Z, 0, U, V STACK CONTENT BEFORE AFTER B I--NOS R (see note) Undefined Note: If A is zero, then R = B (Divide exception). SADD SINGLE PRECISION FLOATING-POINT ADD 7 6 5 4 3 2 Hex Coding: 81 IF SRE = 1

01 IF SRE = °

Execution Time: See Table 2 Description: The single precision operand A from TOS is added to the single precision operand B from NOS. The result is rounded to obtain the final single precision result R which is returned to TOS. The status bits S, Z, U and V are affected to report the sign of the result, if the result is zero, exponent underflow and exponent overflow respectively. The status bit 0 will be cleared to zero. I Status Affected: S, Z, U, V. (0 always zero.) BEFORE A B C STACK CONTENT TOS NOS AFTER R C Undefined SSUB SINGLE PRECISION FLOATING-POINT SUBTRACT 7 6 5 Binary Coding: ISREI ° ° Hex Coding: 82 IF SRE = 1

02 IF SRE = °

Execution Time: See Table 2 Description: 4 3 2 ° ° ° ° ° The single precision operand A at TOS is subtracted from the. single precision operand B at NOS. The result is rounded to obtain the final single precision result R 'vvhich is returned to TOS. The status bits S, Z, U and V are affected to report the sign of the result, if the result is zero, e~ponent underflow and exponent overflow respectively. The status bit 0 will be cleared to zero. Status Affected: S, Z, U, V. (0 always zero.) BEFORE A B C STACK CONTENTS ---- TOS NOS ---- SMUL AFTER R C Undefined SINGLE PRECISION FLOATING-POINT MULTIPLY 7 6 5 432 Hex Coding: 83 IF SRE = 1

03 IF SRE = °

Execution Time: See Table 2 Description: The single precision operand A from TOS is multiplied by the single precision operand B from NOS. The result is rounded to obtain the final single precision result R which is returned to TOS. The status bits S, Z, U and V are affected to report the sign of the result, if the result is zero, exponent underflow and exponent overflow respectively. The status bit 0 will be cleared to zero. Status Affected: S, Z, U, V. (0 always zero.) STACK CONTENTS BEFORE AFTER II . D I I Undefined 7-102

7 6 5 432 ° .Binary Coding: L-I S_R_E-1I_0----1_0---L_0-L_o ---L_---L_O_L-0_ Hex Coding: 84 IF SRE = 1

04 IF SRE = °

Execution Time: See Table 2 Description: The single precision operand B from NOS is divided by the single precision operand A from TOS. The result (quotient) is rounded to obtain the final result R which is returned to TOS. The status bits S, Z, D, U and V are affected to report the sign of the result, if the result is zero, attempt to divide by zero, expo­ nent underflow and exponent overflow respectively. Status Affected: S, Z, D, U, V STACK CONTENTS BEFORE AFTER A I---TOS- R (see note) B --NOS--- C C D D Undefined Note: If exponent field of A is zero then R = B (Divide exception). POPS POP STACK SINGLE PRECISION 7 6 5 Binary Coding: ISRE I ° ° Hex Coding: 87 IF SRE = 1

07 IF SRE = 0

Execution Time: See Table 2 Description: 4 3 2 ° ° ° The single precision operand A is popped from the. stack. The internal stack control mechanism is such that A will be written at the bottom of the stack. The status bits Sand Z are affected to report the sign of the new operand at TOS and if it is zero, respectively. The status bits U, V and D will be cleared to zero. Note that only the exponent field of the new TOS is checked for zero, if it is zero status bit Z will set to 1. Status Affected: S, Z. (U, V, D always zero.) STACK CONTENTS BEFORE AFTER A ~TOS- B B I---NOS- C C D D A Am9S12 PTOD PUSH STACK DOUBLE PRECISION 7 6 5 4 Binary Coding: iSREI 0 ° Hex Coding: AE IF SRE = 1 2E IF SRE = ° Execution Time: See Table 2 Description: 3 2 ° ° The double precision operand A from the TOS is pushed back on to the stack. This is effectively a duplication of A into two con­ secutive stack locations. The status Sand Z are affected to report sign of the new TOS and if the new TOS is zero respectively. The status bits U, V and D will be cleared to zero. Status Affected: S, Z. (U, V, D always zero.) STACK CONTENTS BEFORE AFTER PTOS PUSH STACK SINGLE PRECISION 7 6 5 4 Binary Coding: ISREI 0 ° 0 Hex Coding: ·86 IF SRE = 1

06 IF SRE = °

Execution Time: See Table 2 Description: 3 2 o ° This instruction effectively pushes the single precision operand from TOS on to the stack. This amounts to duplicating the operand at two locations in the stack. However, if the operand at TOS prior to the PTOS command has only its exponent field as zero, the new content of the TOS will all be zeroes. The contents of NOS will be an exact copy of the old TOS. The status bits S and Z are affected to report the sign of the new TOS and if the content of TOS is zero, respectively. The status bits U, Vand D will be cleared to zero. Status Affected: S, Z. (U, V, D always zero.) STACK CONTENTS BEFORE AFTER A I----TOS- A* See note B I--NOS- A C B D C Note: A" = A if Exponent field of A is not zero. A* = 0 if Exponent field of A is zero. 7-103

08 IF SRE = 0

respectively. The status bits U, V and D will be cleared to zero. the TOS and A is at the NOS. All other operands are unchanged. Figure 1. Am9512 to Am8085 Interface.

MAXIMUM RATINGS beyond which useful life may be impaired Storage Temperature Ambient Temperature Under Bias VDD with Respect to VSS -O.5V to +15.0V vee with Respect to VSS -O.5V to + 7.0V All Signal Voltages with Respect to VSS -O.5V to + 7.0V Power Dissipation (Package Limitation) 2.0W The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid exposure to excessive voltages. . OPERATING RANGE Part Number Ambient Temperature VSS VCC VDD Arn9512DC +5.0V ±5% +12V ±5% Arn9512DM +5.0V ±10% +12V ±10% ELECTRICAL CHARACTERISTICS Over Operating Range (Note 1) Parameters Description Test Conditions Min. Typ. Max. Units VOH Output HIGH Voltage 10H = -2001LA 3.7 Volts VOL Output LOW Voltage 10L = 3.2rnA 0.4 Volts VIH Input HIGH Voltage 2.0 vee Volts VIL Input LOW Voltage -0.5 0.8 Volts IIX Input Load Current VSS';; VI.;; vce ±10 /LA 10Z Data Bus Leakage VO = O.4V 10 ILA VO = vce 10 TA = +25°C 50 90 ICC VCC Supply Current TA = O°C 95 rnA TA = -55°C 100 TA = +25°C 50 90

100 VDO Supply Current TA = ooe 95 mA

TA = -55°C 100 CO Output Capacitance 8 10 pF CI Input Capacitance fc = 1.0MHz, Inputs = OV 5 8 pF CIO I/O Capacitance 10 12 pF 7-105

TCDR C/D to RD LOW Set-up Time TCDW C/D to WR LOW Set-up Time TCPH Clock Pulse HIGH Width TCPL Clock Pulse LOW Width TCSP CS LOW to PAUSE LOW Delay (Note 5) TCSR CS to RD LOW Set-up Time TCSW CS LOW to WR LOW S~t-up Time TCY Clock Period TOW Data Valid to WR HIGH De!ay TEAE EACK LOW to END LOW Delay TEHPHR END HIGH to PAUSE HIGH Data Read when Busy TEHPHW END HIGH to PAUSE HIGH Write when Busy TEPW END HIGH Pulse Width TEX Execution Time TOP Data Bus Output Valid to PAUSE HIGH Delay TPPWR PAUSE LOW Pulse Width Read Data Status Data END HIGH to PAUSE HIGH Read when Busy TPPWRB Status TPPWW PAUSE LOW Pulse Width Write when Not Busy TPPWWB PAUSE LOW Pulse Width Write when Busy TPR PAUSE HIGH to Read HIGH Hold Time TPW PAUSE HIGH to Write HIGH Hold Time TRCD RD HIGH to C/D Hold Time TRCS RD HIGH to CS HIGH Hold Time TRO RD LOW to Data Bus On Delay TRZ RD HIGH to Data Bus Off Delay TSAPW SVACK LOW Pulse Width TSAR SVACK LOW to SVREQ LOW Delay TWCD WR HIGH to C/D Hold Time TWCS WR HIGH to CS HIGH Hold Time TWD WR HIGH to Data Bus Hold Time NOTES: 1. Typical values are for T A = 25°C, nominal supply voltages and nominal processing parameters. 2. Switching parameters are listed in alphabetical order. 3. Test conditions assume transition times of 20ns or less, out­ put loading of one TIL gate plus 100pF and timing reference levels of 0.8V and 2.0V. 7-106 Am9512DC Am9512-1DC Min Max Min Max Units 100 75 ns 0 0 ns 0 0 ns 200 500 140 500 ns 240 160 ns 150 100 ns 0 0 ns 0 0 ns 480 5000 320 2000 ns 150 100 nl> 200 175 ns 5.5TCY+300 5.5TCY+200 ns 200 175 ns 400 300 ns See Table 2 ns 0 0 ns 3.5TCY+50 5.5TCY+300 3.5TCY+50 5.5TCY+200 ns 1.5TCY+50 3.5TCY+300 1.5TCY+50 3.5TCY+200 See Table 2 ns 1.5TCY+50 3.5TCY+300 1.5TCY+50 3.5TCY+200 TCSW+50 TCSW+50 ns See Table 2 ns 0 0 ns 0 0 ns 0 0 ns 0 0 ns 50 50 ns 50 200 50 150 ns 100 75 ns 300 200 ns 60 30 ns 60 30 ns 20 20 ns 4. END HIGH pulse width is specified for EACK tied to VSS. Otherwise TEAE applies. 5. PAUSE is pulled low for both command and data operations. 6. TEX is the execution time of the current command (see the Command Execution Times table). 7. PAUSE will go low at this paint if CS is low and RD and WR are high.

cs \\ TCSP PAUSE 00-01 c/o MOS-208 OPERAND READ WHEN Am9S12 IS BUSY ClK - I-TCOR \\ i{ '(~ .' J --< I-TCSR TPR --TRCS- t---t--TRO ~V-Ii TPPWRB TRCO NOtE 7 [\\ { { ~~ ).1 - I-TOP TRZ- l-. ( \\~ (L ~r c/o TEHPHR_ M05-209 7-107

TIMING DIAGRAMS (Cont.) OPERAND ENTRY CLK~. ~ :~:~::-- 00-07 CiD TCSP DATA VALID ~x= ~'---- COMMAND OR DATA WRITE WHEN Am9512 IS BUSY ClK I t--+--TWO 00-07 CID TEHPHW END \\ ~t ~ 7-108 MOS-210 MOS-211

TIMING DIAGRAMS (Cont.) COMMAND INITIATION ClK , \\'---- I II / f--f--TCSW f--TWCS I fl, i TPW TCSP_ .-- \\ NOtE 7 i II TOW- I-TWD H 00-07 -~ \\ K DATA VALID I, I reDW) l- I-TWC0"1 ',I I I Clli TEX } ~~] p ~ {'" i, I "~y END TEX ! \\ ~TSAR} SVREQ Ii /) , " SVACK MOS-212 7-109