AM9150 AMD | Alldatasheet
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1024x4 High-Speed Static R/W RAM. DISTINCTIVE CHARACTERISTICS © 1024x 4 organization ‘© High density SLIM 24-pin 300-MIL package © High speed 20 ns Max. access time © Three-state output butters: © Separate data inputs and outputs © Single +5 V power supply +10% © Memory reset function © Low-power version GENERAL DESCRIPTION The Am9150 is a high-performance, static, n-channel, The Am9150 has four contro! signals A, 5, W and G. The 5 read/write, random-access memory organized as 1024x 4. _input controls read, write and reset operations of the device It features single 5 V supply operation, TTL-compatible and provides for easy selection of an individual device input and output levels, and separate input and output pins when the outputs are tied together. The W (WE) input for improved system performance and ease of use. controls the normal read and write operations, and the G (OE) controls the state of the outputs. ‘The Am9150 also incorporates a reset feature which will reset the entire contents of the memory to logical LOW in two cycle times by controlling A (RESET) and 5 (CS). BLOCK DIAGRAM MODE SELECT TABLE * Inputs ° | " s = —{ Outputs lode : s|wiela * a aad Wot Splecied cya | x | fz Roset® cic) x lm fez Write L | Ho] tL | H |ap-a5 — |roas ctx te os fiz. Output Disabie Norn "See Reset cycle description. Le tow ts Bon 4 ery co ee oo HF 180005261 PRODUCT SELECTOR GUIDE Pan None? [sna anos anaes [Ano | Anois [ani TOE O° to +70°C 160 180 10 | 180 | 130 130 loc Max. (mA) a 0 55°C to + 125°C 180 too | 190 —«| NA | OA N/A | 4-53
CONNECTION DIAGRAMS, Top View sooness 3 (—] 5 veces eege aooness « [_] [) aconess 2 Hoo ooo ‘aponess s (“] [—) avoness + ake ? 1 8 ees, aponess 6 (_] [_) Adoress 0 AEs ath sooness 7 [5 ese a NH bt ‘vores # (“] [7] ear eEECT B) node 22 enc ‘aponess ¢ (—] [) WRITE ERABCE () Ayre 2otw DATA INPUT 0(g) [} [—) SUTPUT ENABTE (@) D, Ey 10 2Ckhs DATAIMPUTS(D4) (—] [) OATA INPUT 3(05) or aie oO, oaTaourpur 149 C] [5 pata mur 2009 NE te a5 te ura vrnurviay [5 ota ourpuraioy RAR ono C] Fone ourrura0 ogide pons cooosoee Note: Pin 1 is marked for orientation. LOGIC SYMBOL METALLIZATION AND PAD (OIP ONLY) LAYOUT oj =) Zn neesenp— 2 | [a Ta — ” ie [axe] —— - 2s a — ad roe eae een sos —_ aa ee ~—_ . Ls001821 ‘coven 30 ~ Die Size: 0.93” x 0.163"
454 Amg150
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Device Number b. Speed Option (if applicable) ©. Package Type d. Temperature Range ©. Optional Processing Amg150_ = Q & a5 | L___ om er Blank = Standard processing | B= Bunn 4. TEMPERATURE RANGE | C= Commorcial (0 10. + 70°C) ©. PACKAGE TYPE D= 26-Pin (300-Mi) Ceramic DIP (C03024) i= 26-Pin Rectangular Coremic Leadess Chip Carer (CLROZ8) b. SPEED OPTION =20= 20 ng 25225 ns 735 =35 ne 245 245 ns -—— . DEVICE NUMBER/DESCRIPTION ‘Am9150/Ama1L50 1024 x4 High-Spe0d Static A/W RAM ‘AmS1L50 = Low-Power Version Valid Combinations Valid Combinations be, pea, Valid Combinations list configurations planned to be supported in volume [Awer5045 | tC, Lc for this device, Consult MSIS sales department to confirm availability of ANTAL SO-25 specific valid combinations, and to obtain additional data on MSIS's AMBILEG-35 standard military grade products.
MILITARY ORDERING INFORMATION APL Products ‘AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a cehination of: a. Device Number b. Speed Option (it applicable) ©. Device Class d. Package Type e. Lead Finish APL Products = 1B 4 A ‘A= Hot Solder Dip C= Gold 4. PACKAGE TYPE Us 245in OOD Ceramic OF (CORn24) U= 28-in Rectangular Ceramic Garrar (C8028) “me k= 24Pin CERPACK (CFMO24) . DEVICE CLASS 18 = Glass B b. SPEED OPTION ~25 = 25 ns 735 = 35 ne 745 = 45 ns ‘4, DEVICE NUMBER/DESCRIPTION Am9150
10244 High-Spoed State A/W RAM
TBLA Valid Combinations list configurations planned to be supported in volume awstsoas | auc for this device. Consult MSIS sales department to confirm availability of JBKA specific valid combinations, and to obtain additional data on MSIS's standard military grade products. Group A Tests Group A tests consist of Subgroups PIN DESCRIPTION Ag-Ag Address (Inputs) R_ RESET (Input; Active Low) ‘The 10 address inputs select one-of the 1024 4-bit words in An active-Low pulse on Ri while Ag~ Ag are stable, 5 is the RAM. LOW, and W and & are HIGH rosets the whole memory.
3 Chip Select (Input; Active LOW) G_ Output Enable (Input; Active LOW)
An active-LOW input which selects the device for operation. G controls the state of the data outputs in conjunction with 5 ‘When § is HIGH, the device is deselected and the outputs and W. will be in a high-impedance state. Do=D3 Data Input W__ Write Enable (Input; Active Low) Data inputs to the RAM. W controls read and write operations. When Wis KiGH and 29-03 Data Output Gis LOW, data will be present at the data outputs. When Data outputs from the RAM, The data out tt . L (puts will be in a is LOW, data present on the data inputs will be written into hight ‘ither Sor G the celgcted memory locaten ne pts willbe inva highempedance slate whan athe S or aro HIGH or Wis high-impedance state. : ‘gh i Voc Power Supply +5 Volts Vss_ Ground
ABSOLUTE MAXIMUM RATINGS | (Note 1) OPERATING RANGES (Note 2) Storage Temperature oc... ccs =65 to +150°C Commercial (C) Devices Ambient Temperature with Ambient Temperature (Ta) sce seecrseesee0 10 +70°C Power AppIEM cso. 55 to +125°C Supply Voltage (VOC) oon #50 V 410% Supply Voltage with iia vy (M) Devices Pere AO Grou eeersreenenes 08 VIO $7.0 V Ambiont Temperature (Ta) o-cocssoessn 55 tO +125°C Sig tages wit Supply Voltage (VoC) esses sees # 5.0 V 410% Respact to Ground... sensei 8.5 V 10 +70 V Dissipati imitati fo Fe eae eam acnag® Lirstaton) 26k Operating ranges define those limits between which the rrrrennercnsrnnnsennnncs functionality of the device is guaranteed. The products described by this spectication include internal rcuitry designed to protect input devices trom damaging accumulations of static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid exposure to excessive voltages. DC CHARACTERISTICS over operating ranges unless otherwise specified (for APL Products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) [_amoiso | amoweso | Parameter Parameter Symbol_ | _ Desciption est conations [win | ax | win. | wax. | unt Yon [Output HIGH Curent [vows 2a va ee fo [Outpt LOW Gurrent [Von S04 yea a Vin [input HIGH Vottage [22 [eo [a2 [eo Tv Vi | input LOW Votage j =25 [oe | -2s [oa Tv x Input Load Curent [GNOSWieVoo [10 F010 0 loz [Output Leakage Curent [GND Vo < Vos Output Osabiod | =t0 [yo [10 | 10 [aa S| moat Capactance eee, | |e | Tos Te Co. Vog=5 V (Note 8) a a loc Vee Operating Supply Max Voo 5 Vi, Output a a . mA carert Open | los GND <Vo<Voo (Wotes 7,6) [+50 [+300 [50] +300 [ma Noles: 1. Absolute Maximum Ratings are intended for user guidelines and aro not tested.
2 For test and corelaton purposes, ambont tomporaturs Is defined as the "instant ON" case tomperatue
- Test conditons assume signal transition timas of 10 ns of less, ting reference lovels of 1.5 V. input puso levels of O to 3.0 V and uot oad of te special an 30 oF lead eapactancas Cup ang teenco 1.5 4. The intemal write time of the memory 's detined by the overan of § LOW and W LOW. Both signals must be LOW to initate a wite and ther signal can terminate @ write by going HIGH. Tho data input setup and hold timing js referenced 10 tho rsing edge of to ‘Signal hat torminates the wre. R must bo HIGH 5. Transiton is measured at 1'5.V on the inputs 10 Vow ~$00 mV and Voy + 500 mV on the outputs using the load shown in B. under Serning Tot Creu, © Wand & are HIGH for read cycle. 7. For test purposes, not more than one output at @ te should be shored. Short circu tost duration should not exceed 30 seconds 8. This parameter 's ot tested, BUt Qunrantoed by charactorzaton ragioy «or |
a SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified (for APL Products, Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) Parameter | ansss020| ‘Am9150-25 ‘Am9150-45 ‘Symbol Parameter ‘Am91L50-25 | Am91L50-35 | Am91L50-45 READ CYCLE T_]TAVAV tao [Reac Gyoro time owe) YT 20 [Tas [Ts [fs [7 ns “2 fravav [un [aasross Access Time TT 20 [fs Ps Ps Ts 3_[rstav[tscs [hip Select Accoss Time [fro [Ts Peo PT as ne 4 [Tetav ioe — [Output Enable Access Tme [fo fs [| ao fT as ns a Low-z (Notes 5, 8) cm =O Fiz (Notes 5. 8) heeft Pt | Low-2 (Note 5, 8) cl Hi-Z (Notes 5, 8) 9 [taxax Oupu Hold attr oot [a [3 [ts fs [yn Asross Change a CA WRITE CYCLE 10 [TAVAY Two [Werle Gycte Time ote 4) [20 TT 6 [fs Ts TT ns [een fou Reserve wees] eT Tey ey fet 2 |TAVWH [aw Tadoress Vaid io End of wete [a8 | [ao [so [oe TT ns va [wows [we [write Puse wan to | is fe Pe Pe is fiw “Twa Tasress Hots etter End of wine [5 [Ts [ts Ts fT ns efor low pgrewewwree Te Tet fey fet ft 17 [WHO lipg [ata Hod ator End ot wine [5 [6 | fs {ys ss ve [rwiaz [wz Write Enable LOW to Output rs ee [we friar [ee ye Tete re tet? | a a Ol Low-Z (Notes 5, 8) RESET CYCLE 20 _[TAVAV[ianc [Reset Gycie Time a0 TT so Tf 7 Tf fT ns a a Reset a [efor renewal Ye ey fey a c= | 24 [TALRH [iw _[Rosat Puiso wan ao [ao fo Po Ts i a OO Reset a a a eset 27 [TAHAX [tua [Aderess Hots after End of Reset [20 | [so [ [40 [| so [| os
28 Reset LOW to Output in HiZ 8
peor [re leewgrowrnnes Te Pepe pe ye tats | ca cl Ol (Notes 5, 8) Notes: See notes following OC Characteristics table | 400 ruse
RESET CYCLE control § must be <Vi__ maximum, and W must be > Vin minimum and it is recommended that G be > Vijq minimum. The reset cycle is initiated by F going LOW for a time > tap, and is terminated by holding Fi HIGH for a time > taya. The The reset cycle is normally associated with current spikes, addresses to the device must be stable during the RESET both at Voc and GND as shown in the graph. To attenuate the cycle time. The entire contents of the RAM will be reset to current spikes, an external bypass capacitor (high frequency, ZERO regardless of the address chosen during the cycle. The 0.1 iF) for each Amg150 socket is recommended, Typleal Ic¢ and Ignp During a Reset Cycle The aee Vee= 38¥ won A —___J . foo, Ke ® oma — mma — see naa - ono ss ss ow 0 «0 © 0 % © w se «na wF009920 wee SWITCHING TEST CIRCUITS Yee Yee soa son Pour Pour 2096 2000 wouce ron Sor #0) To002360 Tooe2360 A B. ‘Am9150 4-59 |
KEY TO SWITCHING WAVEFORMS ——_ oo scone CO) aoe 0; @ ® Koo Read Cycle 4-60 Am9150
SWITCHING WAVEFORMS (Cont'd) ===S*~C*~CS soe CC © ) “ im "oe woe (SYS Am9150 4-61 |