AM95C96 AMD | Alldatasheet
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Optical Disk Controller Devices DISTINCTIVE CHARACTERISTICS ™ Supports the proposed X3B11 and ISO ™® Up to 32 MHz NRZ Serial Disk Data Continuous Composite Servo standard High Level Command Set ® User programmable disk formats ® Supports intelligent SCSHtype Interfaces ® Minimal Rotational Latency Read/Write . Operations On-chip Buffer Management 4:1 Sector interleave Read/Write Operations ™ Direct support of DRAM Butter (up to 4 MBytes) @ 20 MHz System Clock GENERAL DESCRIPTION The Optical Disk Data Controfler (ODC) is a hightypro- controller application, the control CPU (referredto inthis Qgrammable optical disk data format controller designed document as simply the CPU), interprets all SCSI com- for use in both standard and custom applications. The mands and controls disk head positioning and head se- device has been optimized for applications utilizing an lection, while the ODC handles all data transfers. The embedded SCSI disk data manager, but it easily sup- CPU sets up and initiates ODC operation by modifying ports other intelligent proprietary interfaces as well. as few as 6 ODC registers. ODC registers are directly ressab! be rectly As an embeddedontrolier,the ODC handles the timing __Saymessabis- one eat be read t wien orn , of all disk read/write control signals, the transfer of NRZ Motorola 68xxx type non-multiplexed bus interface. data between the disk and butler RAM, and the transfer of disk data between a parallel host interface and buffer Adadicated interface to an external error processor per- RAM. The ODC performs all buffer management and ar- mits the ODOC to cope with the high error rates associ- bitration associated with this transfer of data while main- ated with optical media. Through this interface the ODC, taining data integrity by using a dedicated interface to an in combination with AMD's Advanced Burst Error Proc- external, high performance Advanced Burst Error Proc- essor (ABEP), can correct an error in as little as 10 essor (ABEP). In addition, the ODC can perform ad- secs. The ABEP supports 5 or 10 way interleaving with vanced data mapping operations during data transfer, optional overlay CRC capability. The ABEP can correct simplifying the task of cache management. The ODC up to 80 errors in a single sector in less than a millisec- can handle up to 4 Mbytes of data buffer Dynamic RAM ond. With this error correction capability, the ODC and directly, including address multiplexing and reiresh, with ABEP can perform on-the-fly error correction without no external logic. missing a sector. This avoids the necessity of jumping A . back to continue a disk read operation following a read The ODC acts as anintelligent peripheral to a micropro- cessor or microcontroller. In an embedded SCSI disk °F when handling spiral formatted media, Publication # 13081 Rev. A “Amanderart (0! (eae Date Septorber 1989
—P Me V Button Bus cRC Controller Logic Fane ra Controller (WCS) cPU Disk Sy Sis fete] Be one eneee File Control a en Ss uSeq 10996-0014 SYSTEM APPLICATION Extemal Extemal Butter Presostor Memory ABE (ORAMs) anesedsy Butter Bus Ses! nts (Parity Optional) {SCSI (Am33C93A) Py ope Bata Disk /Am95C96 Encoder! , ¢ ) Frcodes Logic +o ~~ Migtogontrofier lg ' CPU BUS : — La ' RAM/ROM (8/16 Bats) Interface ‘ 10936-002A
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RELATED AMD PRODUCTS. [ Partnumber | Description CONNECTION DIAGRAM 238558 82223323223223 nono nnnN po7 LU] 12 ° 74 [J] bo spry CJ 13 73 [Jo cucx2 LJ 14 72 [02 eukxt Cf 15 71 [103 READY C] 16 7o [J D4 wt] 17 69 [} Ds Voc CL} 18 68 |] D6 Vee O 19 67 LJ07 RAS] 20 66 1) Voc Vss C] 21 es [6S vss O 22 64 1] Vss Ves C] 23 e WR cas] 24 62 1 Vee BwE 25 6: [RO Hora’ L] 26 60 [J ALE PROC] 27 s9 [J Ao PWR] 28 sa [At . Hack: C] 29 s7 [J a2 ) Acs C] 30 se [J a3 | Epos] 1 ss [a4 EPCS] 32 54 [J As 33.34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 OOOCOCCUOOOOUOOOODOoOooo 7 a 3 = ssc o =: ce 0 oO wou “These pins have programmable polarity. Am95C96 3
Ao-Ay u 4 BABA. ALE 1 F N E CAS FST T R RAS INT R B BWE F u cs A s ACS READY [DTACK] c PRO [PDS|_ WRIRA] — M PWR [PRA] FD [DS] T E HDRQ* RDREFCLK Hy HACK* WRCLK D A — WRDAT 1 c EPCS RDDAT s E iad WGATE K BERROR RGATE VECTAV GENO1 4 GENO T GENIO E INDEX R AMC F A c AMF/SECTOR E FAULT oT Ves 10996-0044, * These pins have programmable polarity
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ORDERING INFORMATION
‘AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of: a, Device Number b. Speed Option (if applicable) c. Package Type 4. Temperature Range @. Optional Processing amosces «20 TL @. OPTIONAL PROCESSING Blank = Standard processing d. TEMPERATURE RANGE C = Commercial (0 to +70°C) cc. PACKAGE TYPE J = 84-Pin Plastic Leaded Chip Carrier (PL 084) b. SPEED OPTION -2 = 16 MH2/24 MHz ~4 = 20 MH2/32 MHz a. DEVICE NUMBER/DESCRIPTION Am95C96 Valld Combinations Valid Combinations list configurations planned to AM95C96-206 Je be supported in volume for this device. Consult AM95C96-4JC the local AMD sales office to confirm availability of ‘specific valid combinations, to check on newly re- leased combinations, and to obtain additional data on AMD's standard military grade products. ‘Am95C96 5
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