AM95C95 AMD | Alldatasheet
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ell a TE lm DE a Ne PA lt = Am95C95 Advanced Micro Magnetic Disk Controller Devices DISTINCTIVE CHARACTERISTICS @ Handles ESMD/ESDI and ST-506 Magnetic @ 20 MHz System Clock Disk Data Format @ Up to 32 MHz NRZ Serial Disk Data disk Comm ™@ User programmable formats High Level and Set ion and . onen nip ReedSo lomon Error Detection a @ Supports Intelligent SCSI-type Interfaces Minimal Rotational Latency Read/Write ® On-chip Buffer Management Operations ® Direct support of DRAM Buffer 1:1 Sector interleave Read/Write Operations (up to 4 MBytes) nS GENERAL DESCRIPTION The Magnetic Disk Data Controller (MDC) is a highly The MDC acts as an intelligent peripheral to a micropro- programmable magnetic disk data format controller de- cessor or microcontroller. In an embedded SCSI disk signed for use in both standard and custom applica- controller application, the control CPU (referred to in this tions. The device has been optimized for applications document as simply the CPU), interprets all SCS! com- utilizing an embedded SCSI disk data manager, but it mands and controls disk head positioning and head se- easily supports other intelligent proprietary intertaces as lection, while the MDC handles all data transfers. The well. CPU sets up and initiates MOC operation by moditying - as few as 6 MDC registers. MOC registers are directly As anembedded controller, the MDC handles thetiming —_agdressable, and can be read or written directly with of all disk read/write control signals, the transfer of NRZ i i ° either an iAPX multiplexed address/data bus, or a data between the disk and buffer RAM, and the transter Motorola 68xxx type non-multiplexed bus interface. of disk data between a parallel host interface and butter RAM. The MOC performs all buffer management and ar- The on-chip Reed-Solomon Error Detection And Cor- bitration associated with this transter of data while main- rection (EDAC) logic enables the MDC to perform on- taining data integrity through on-chip error detection and the-fly error correction during disk read operations while correction logic. In addition, the MDC can perform ad- maintaining a zero sector interleave on the disk. The vanced data mapping operations during data transfer, MDC performs such error correction without CPU inter- simplifying the task of cache management. The MDC vention. The Reed-Solomon logic supports 2, 3 or 5 can handle up to 4 Mbytes of data butter Dynamic RAM EDAC interleaves within a sector data field and either directly, including address multiplexing and refresh, with single- or double-burst correction capability. no external logic. tssue Oato: Septerber 1989 |
a INTERNAL BLOCK DIAGRAM lost ==) (Le., SCSI) 7 . cae FAS, CAS, BWE negs 2 AAM 2 9 Refresh Data r'] P| NA2 Date md ed : Pt we Cope a = “ sees] [[reo]-—~| Comet = ie a at +m [7] FAULT ea a eee a 2] SENC2 Logic Status 10935-001A SYSTEM APPLICATION External Butter Inter (Paty Oper face ‘ar ne (SCSI) wy Cro (Am33C93A) 8+Pty Dat: 5 ( 5) and Logic H CPU BUS : —t— > Lm | ' RAM/ROM (8/16 Bits) Interface 7 Disk 10935-002A
[Pan number | deserpion | [ameosx | Miseconroier | a CONNECTION DIAGRAM £888888932235223222323 nono onnononnM p07 C 12 ° 74 [ bo pety C 13 73 Do ciw2 0] 14 72 1 oe cikxt O15 71 | os READY Cf 16 7o H) 04 int Q 17 69 1) os Vee Cf 18 es 1) be Veco O 19 67 ) v7 RAS C{ 20 66 Vee Ves C21 65 PD) cs Ves C{ 22 64 LO Vs Ves Cf 23 e3 [J WR CAS C] 24 62 [ Vee BwE CJ 25 61 ( PO Hora’ Cf 26 60 |) ALE PRD C] 27 so 1) ao PWR 28 sa Dat Hack CJ 29 s7 J a2 Acs C 30 sé LH) as Epos C] 31 55 Fas EPCS CJ 32 54 1] as 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 OOOUODOODOODOOOUOOOUOUUUG SBREESQSESHEESSLRS bese * These pins have programmable polarity. ° Am95C95 3
CLKxt MDC BD, - BD. D, -D; c 2 = BD P BOP U Ao ~ Ay B BAy - BA ALE 1 Hy Fst " Ha oS iNT Ee E RAS R R BWE ws F READY{DTACR] a 5 tes wm ( E 8 Pampa PWR [PI FD [D3] [PRAY] ? N HDRQ* WRCLK K E WRDAT R RopAT ——=| 1 4 ERCS WGATE N EPOS T c BERROR RGATE E E VECTAV GENO1 F ‘GENO2 A GENO ——>}] C INDEX E AMC AMF/SECTOR ——>| FAULT ——+| EoT Vss 10835-004A, * These pins have programmable polarity. ee
4 Am95C95
ORDERING INFORMATION
‘AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by acombination of: a. Device Number b. Speed Option (if applicable) c. Package Type ¢. Temperature Range e. Optional Processing - AM9sc95 = -2 J c ‘L_____. ..opmionat. processive Blank = Standard processing d. TEMPERATURE RANGE C = Commercial (0 10 +70° C) c. PACKAGE TYPE J. = 84-Pin Plastic Leaded Chip Carrier (PL 084) b. SPEED OPTION 2 = 16 MHz/24 MHz -4 = 20 MHz/32 MHz a. DEVICE NUMBER/DESCRIPTION ‘Am95C95 dons iat configurator Valid alid Combinations Valid Combinations list configurations planned to AM95C95-2JC be supported in volume for this device. Consult JC the local AMD sales office to confirm availability of AM95C95—4JC specific valid combinations, to check on newly re- leased combinations, and to obtain additional data on AMD's standard military grade products. Am95C95 5
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