AM79C901A

Advanced Micro Devices

HomePHY Single-Chip 1/10 Mbps Home Networking PHY

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Publication# 22304 Rev: C Amendment/0 Issue Date: July 2000 Refer to AMD’s Website (www.amd.com ) for the latest information. Am79C901A HomePHY™ Single-Chip 1/10 Mbps Home Networking PHY DISTINCTIVE CHARACTERISTICS /G110Fully integrated 1 Mbps HomePNA Physical Layer (PHY) as defined by Home Phoneline Networking Alliance (HomePNA) specification 1.1 — Optimized for home networking applications over existing telephone wire — Media Independent Interface (MII)-compatible for connecting external Media Access Controller (MAC) — In-band control features: Adjustable power and speed levels 32 bits of reserved in-band messaging piggy- backed on Ethernet packet — Register programmable features: Power control Speed control Performance registers Optional control of Squelch algorithm Major frame timing parameters programma- ble: ISBI, AID ISBI, pulse width, inter-symbol time — any1Home ™ link detection: Indicates to the MAC that a valid home net- working node has been detected Detects a network failure and allows the upper layer protocol to take corrective action /G110Fully integrated 10 Mbps Ethernet transceiver — Comprehensive Auto-Negotiation implementation — IEEE 802.3u-compliant MII — Full-duplex operation supported on the MII port with independent Transmit (TX) and Receive (RX) channels — Optimized for 10BASE-T applications /G110Compliant with HomePNA specification 1.1 /G110General Purpose Serial Interface (GPSI)/Serial Peripheral Interface (SPI) /G110Extensive programmable internal/external loopback capabilities /G110Extensive LED status support /G110IEEE 1149.1-compliant JTAG Boundary Scan test access port interface /G110Very low power consumption /G110+3.3 V power supply along with 5 V tolerant I/Os enable broad system compatibility — XTAL1 supports 3.3 V I/O only — XTAL2 supports 1.0 V I/O only /G110Available in 68-pin PLCC and 80-pin TQFP packages /G110Industrial Temperature Support (-40ºC to +85ºC) GENERAL DESCRIPTION The Am79C901A HomePHY is a single-chip device that contains both a physical layer (PHY) for 1 Mbps data networking over existing residential telephone wiring based on the specification published by HomePNA and a physical layer for supporting the IEEE 802.3 standard for 10BASE-T. The HomePHY is targeted at embedded applications and has both GPSI and MII-compatible interfaces. The integrated HomePNA transceiver is a physical layer device that enables data networking at speeds up to 1 Mbps over existing residential phone wiring regardless of topology and without disrupting telephone (POTS) service. The integrated Ethernet transceiver is a physical layer device supporting the IEEE 802.3 standard for 10BASE-T. It provides all of the PHY layer functions required to support 10 Mbps data transfer speeds. A compliant IEEE 1149.1 JTAG test interface for board level testing is provided. The Am79C901A PHY also provides on-chip LED drivers for collision, link integrity, speed, activity, and power output. The Am79C901A PHY is fabricated in an advanced low power 3.3 V CMOS process to provide low operating current for power sensitive applications. The Am79C901A PHY is available in the commercial temperature range (0ºC to +70ºC) in 68-pin PLCC and 80-pin TQFP packages. The Am79C901A also supports the industrial temperature range (-40ºC to +85ºC) in the 80-pin TQFP package. The industrial temperature range is well suited to environments with enclosures with restricted air flow or outdoor equipment.

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PHY_SEL PHY_AD ISOLATE MII/GPSI GM_MODE RXDAT, RXCLK, RXCRS, CLS, TXDAT, TXCLK, TXEN or RXD[3:0], TXD[3:0], CRS, COL, RX_DV, TX_EN, TX_CLK, RX_CLK, RX_ER MDC, MDIO or SCLK, SDI, SDO, CS POWER TDO TDI TCLK TMS LED Interface JTAG Port Control Link Control Data Interface Drive Control Analog Front End Transmit State Machine Receive State Machine PHY Control & Registers Link Control Data Interface Transmit State Machine Receive State Machine PHY Control & RegistersClock Reference DATA CONTROL 10BASE-T PHY 1Mbps HomePNA PHY TX± RX± XTAL1 XTAL2 XCLK/XTAL CONTROL DATA CONTROL 22304B-1

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Table 1. Clock Source Selection 21 Table 22. HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register - Table 23. HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register - Table 46. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Table 47. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) -

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CONNECTION DIAGRAM (PL 068) Note: NC pins are reserved and should be left unconnected. 4 32187659 6 86 76 66 56 46 36 26 1 32 33 34 3528 29 30 3127 36 37 38 39 40 41 42 43 RX_DV DVDD DVSS RXD0/RXDAT RXD1 RX_CLK/RXCLK AVDD PHY_SEL DVDD RX_ER DVSS GM_MODE TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT TXD1/SDI NC NC RX- AVDD RX+ AVSS TX- AVDD TX+ AVSS IREF AVDD HRTXRXP AVDD HRTXRXN AVSS AVSS AVDD RXD2 RXD3 DVSS LED_SPEED LED_POWER DVDD LED_ACTIVITY LED_COL LED_LINK MDC/SCLK DVSS MDIO/SDO ISOLATE PHY_AD MII/GPSI TEN RESET COL/CLS DVSS DVSS TXD3/CS TXD2 CRS/RXCRS DVDD DVDD TDO TCK TMS TDI XCLK/XTAL XTAL2 XTAL1 AVDD NC Am79C901 HomePHY 22304B-2 A

CONNECTION DIAGRAM (PQT 80) 22304B- NC NC RX01 RXD0/RXOAT DVSS RX_DV DVDD RX_CLK/RXCLK AVDD PHY_SEL DVDD RX_ER DVSS GM_MODE TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT TXD1/SDI NC NC NC NC TXD2 TXD3/CS DVSS COL/CLS DVSS CRS/RXCRS DVDD DVDD TDO TDK TMS TDI XCLK/XTAL XTAL2 XTAL1 AVDD NC NC NC NC RESET TEN MH/GPSI PHY_AD ISOLATE MDIO/SDO DVSS MDC/SCLK LED_LINK LED_COL LED_ACTIVITY DVDD LED_POWER LED_SPEED DVSS RXD3 RXD2 NC NC NC RX- AVDD RX+ AVSS TX- AVDD TX+ AVSS IREF AVDD HRTXRXP AVDD HRTXRXN AVSS AVSS AVDD NC NC Am79C901 A HomePHY Note: NC pins are reserved and should be left unconnected.

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PIN DESIGNATIONS (PL 068) Listed By Pin Number Note: NC pins are reserved and should be left unconnected. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 LED_LINK 18 DVDD 35 TDO 52 AVSS

2 LED_COL 19 RX_ER 36 TCK 53 TX+

3 LED_ACTIVITY 20 DVSS 37 TMS 54 AVDD

4 DVDD 21 GM_MODE 38 TDI 55 TX-

5 LED_POWER 22 TX_CLK/TXCLK 39 XCLK/XTAL 56 AVSS

6 LED_SPEED 23 TX_EN/TXEN 40 XTAL2 57 RX+

7 DVSS 24 TXD0/TXDAT 41 XTAL1 58 AVDD

8 RXD3 25 TXD1/SDI 42 AVDD 59 RX-

9 RXD2 26 NC 43 NC 60 NC

10 RXD1 27 TXD2 44 AVDD 61 RESET

11 RXD0/RXDA T 28 TXD3/CS 45 AVSS 62 TEN

12 DVSS 29 DVSS 46 AVSS 63 MII/GPSI

13 RX_DV 30 COL/CLS 47 HRTXRXN 64 PHY_AD

14 DVDD 31 DVSS 48 AVDD 65 ISOLATE

15 RX_CLK/RXCLK 32 CRS/RXCRS 49 HRTXRXP 66 MDIO/SDO

16 AVDD 33 DVDD 50 AVDD 67 DVSS

17 PHY_SEL 34 DVDD 51 IREF 68 MDC/SCLK

PIN DESIGNATIONS (PQT 80) Listed By Pin Number Note: NC pins are reserved and should be left unconnected. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 NC 21 NC 41 NC 61 NC

2 NC 22 NC 42 NC 62 NC

3 RXD1 23 TXD2 43 AVDD 63 RESET

4 RXD0/RXDA T 24 TXD3/CS 44 AVSS 64 TEN

5 DVSS 25 DVSS 45 AVSS 65 MII/GPSI

6 RX_DV 26 COL/CLS 46 HRTXRXN 66 PHY_AD

7 DVDD 27 DVSS 47 AVDD 67 ISOLATE

8 RX_CLK/RXCLK 28 CRS/RXCRS 48 HRTXRXP 68 MDIO/SDO

9 AVDD 29 DVDD 49 AVDD 69 DVSS

10 PHY_SEL 30 DVDD 50 IREF 70 MDC/SCLK

11 DVDD 31 TDO 51 AVSS 71 LED_LINK

12 RX_ER 32 TCK 52 TX+ 72 LED_COL

13 DVSS 33 TMS 53 AVDD 73 LED_ACTIVITY

14 GM_MODE 34 TDI 54 TX- 74 DVDD

15 TX_CLK/TXCLK 35 XCLK/XTAL 55 AVSS 75 LED_POWER

16 TX_EN/TXEN 36 XTAL2 56 RX+ 76 LED_SPEED

17 TXD0/TXDAT 37 XTAL1 57 AVDD 77 DVSS

18 TXD1/SDI 38 AVDD 58 RX- 78 RXD3

19 NC 39 NC 59 NC 79 RXD2

20 NC 40 NC 60 NC 80 NC

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PIN DESIGNATIONS (PL 068) Listed By Group Pin Name Pin Function Type Driver Type Number of Pins Configuration MII/GPSI Selects MII or GPSI mode I – 1 GM_MODE Selects MDC/MDIO and GPSI data I – 1 ISOLATE Isolates device if register isolate bit is set = 1 I – 1 PHY_SEL Defines default PHY I – 1 PHY_AD Defines bit 2 of the PHY address I – 1 Board Interface RESET RESET I – 1 XCLK/XTAL Oscillator/Crystal Select I – 1 XTAL1 Crystal Input (20 MHz XTAL/60 MHz CLK) I – 1 XTAL2 Crystal Output (20 MHz XTAL) O XTAL 1 IREF Tied to GND via a 12.1 k Ω 1% resistor I – 1 LED_COL Collision Indication O LED 1 LED_ACTIVITY Activity Indication O LED 1 LED_LINK Link Valid Indication O LED 1 LED_SPEED High Speed Indication O LED 1 LED_POWER High Power Indication O LED 1

1 Mbps HomePNA PHY Network Ports

HRTXRXP/N Receive/Transmit Data I/O – 2 10BASE-T PHY Network Ports TX± Serial Transmit Data O – 2 RX± Serial Receive Data I – 2 MII Interface TX_CLK MII Transmit Clock O OMII 1 TXD[3:0] MII Transmit Data I – 4 TX_EN MII Transmit Enable I – 1 RX_CLK MII Receive Clock O OMII 1 RXD[3:0] MII Receive Data O OMII 4 RX_ER MII Receive Error O OMII 1 RX_DV MII Receive Data Valid O OMII 1 MDC MII Management Data Clock I – 1 MDIO MII Management Data Input/Output I/O TSMII 1 CRS Carrier Sense O OMII 1 COL Collision O OMII 1

Pin Name Pin Function Type Driver Type Number of Pins GPSI Interface TXCLK GPSI Transmit Clock O OMII 1 TXDAT GPSI Transmit Data I – 1 TXEN GPSI Transmit Enable I – 1 RXCLK GPSI Receive Clock O OMII 1 RXDAT GPSI Receive Data O OMII 1 RXCRS Carrier Sense O OMII 1 CLS Collision O OMII 1 SPI Interface SCLK SPI Clock I – 1 SDI SPI Data In I – 1 SDO SPI Data Out O TSMII 1 CS Chip Select I – 1 IEEE 1149.1 (JTAG) Test Access Port Interface TCK Test Clock I – 1 TMS Test Mode Select I – 1 TDI Test Data In I – 1 TDO Test Data Out O TS 1 Power Supply DVDD Digital Power P – 6 AVDD Analog Power P – 6 DVSS Digital Ground G – 7 AVSS Analog Ground G – 3 Test Interface TEN Test Enable I – 1

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PIN DESIGNATIONS (PQT 80) Listed By Group Pin Name Pin Function Type Driver Type Number of Pins Configuration MII/GPSI Selects MII or GPSI mode I – 1 GM_MODE Selects MDC/MDIO and GPSI data I – 1 ISOLATE Isolates device if register isolate bit is set = 1 I – 1 PHY_SEL Defines default PHY I – 1 PHY_AD Defines bit 2 of the PHY address I – 1 Board Interface RESET RESET I – 1 XCLK/XTAL Oscillator/Crystal Select I – 1 XTAL1 Crystal Input (20 MHz XTAL/60 MHz CLK) I – 1 XTAL2 Crystal Output (20 MHz XTAL) O XTAL 1 IREF Tied to GND via a 12.1 k Ω 1% resistor I – 1 LED_COL Collision Indication O LED 1 LED_ACTIVITY Activity Indication O LED 1 LED_LINK Link Valid Indication O LED 1 LED_SPEED High Speed Indication O LED 1 LED_POWER High Power Indication O LED 1 HRTXRXP/N Receive/Transmit Data I/O – 2 10BASE-T PHY Network Ports TX± Serial Transmit Data O – 2 RX± Serial Receive Data I – 2 MII Interface TX_CLK MII Transmit Clock O OMII 1 TXD[3:0] MII Transmit Data I – 4 TX_EN MII Transmit Enable I – 1 RX_CLK MII Receive Clock O OMII 1 RXD[3:0] MII Receive Data O OMII 4 RX_ER MII Receive Error O OMII 1 RX_DV MII Receive Data Valid O OMII 1 MDC MII Management Data Clock I – 1 MDIO MII Management Data Input/Output I/O TSMII 1 CRS Carrier Sense O OMII 1 COL Collision O OMII 1

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The following table describes the various types of out- put drivers used in the Am79C901A PHY . All IOL and IOH values shown in the table apply to 3.3 V signaling. A sustained tri-state signal is an active-low signal that is driven high for one clock period before it is left floating. TX± is a differential output driver. Its characteristics and those of the XTAL2 output are described in the DC Characteristics section. Note: For reference only. See DC specification for actual limits. Driver Name Type I OL (mA) I OH (mA) Load (pF) LED LED 12 0.4 50 TS Tri-State 6 2 50 OMII Tri-State 4 4 50 TSMII Tri-State 4 4 150

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) SPEED OPTION PACKAGE TYPE Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations DEVICE NUMBER/DESCRIPTION Not applicable J = Plastic Leaded Chip Carrier (PL 068) V = Thin Plastic Quad Flat Pack (PQT 80) Am79C901A HomePHY Single-Chip 1/10 Mbps Home Networking PHY Valid Combinations Am79C901A JC, JC\\T VC, VI ALTERNATE PACKAGING OPTIO N \\T = Tape and Reel C\\I J\\V \\TAm79C901A

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MII/GPSI selects between the MII and the GPSI inter- face. This pin must be connected to either VDD or VSS . Changing the state of this pin is prohibited. GM_MODE GM_MODE Input This input pin selects between the MDC/MDIO com- mand and control interface and the SPI interface nor- mally available in the GPSI mode. This pin must be connected to either V DD or VSS . Changing the state of this pin is prohibited. Note: GM_MODE = 1 overrides the value on the MII/GPSI configuration pin. PHY_AD PHY Address Input Sets bit 2 of the PHY Address field. The PHYs have de- fault MII address of 0x00 (0000b) for the 1 Mbps HomePNA PHY and 0x01 (0001b) for the 10BASE-T PHY . If this bit is set, the address for the HomePNA PHY is 0x02 (00010b) and 0x03 (00011b) for the 10BASE-T PHY . ISOLATE Isolate Input In an environment that utilizes the MII or the SPI com- mand and control interface (managed mode), this pin must be held HIGH. In an environment that does not use the MII or the SPI command and control interface (external control mode), this pin enables the data inter- face when set to a LOW, and forces the interface into a high impedance state when held HIGH. This pin func- tions in conjunction with the PHY_SEL pin and HPR0, bit 10, and TBR0, bit 10. PHY_SEL PHY Select Input In an environment that utilizes the MII or the SPI com- mand and control interface (managed mode), this pin must be held LOW. In an environment that does not use the MII or the SPI command and control interface (ex- ternal control mode), this pin selects which PHY data and status signals will be driven onto the interface. When set to a LOW, the HomePNA PHY data and sta- tus signals will be driven onto the interface. When set to a HIGH, the 10BASE-T PHY data and status signals will be driven onto the interface. This pin functions in conjunction with the ISOLATE pin. LOW = 1 Mbps HomePNA PHY HIGH = 10BASE-T PHY Board Interface LED_COL LED_COL Output This output is designed to directly drive an LED. COL low indicates that a collision has been detected on the currently active PHY . An internal pulse stretching circuit will ensure that the minimum output pulse is approximately 100 ms. LED_ACTIVITY LED_ACTIVITY Output This output is designed to directly drive an LED. ACTIVITY low indicates that there is receive or trans- mit activity on the network of the currently active PHY . An internal pulse stretching circuit will ensure that the minimum output pulse is approximately 100 ms. LED_LINK LED_LINK Output This output is designed to directly drive an LED. LINK low indicates that a valid link has been detected on the currently active PHY . GM_MODE MII/GPSI Data Interface Command and Control Interface 0 1 MII MDC/MDIO 0 0 GPSI SPI

1 X GPSI MDC/MDIO

Bit 10 PHY_SEL ISOLATE Interface Source Managed Mode 11 0 1 H i Z 01 0 1 1 Mbps HomePNA 1 0 0 1 10BASE-T 00 0 1 N o n V a l i d External Control Mode 1 1 1 0 10BASE-T 11 0 0 1 Mbps HomePNA

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LED_SPEED LED_SPEED Output This output is designed to directly drive an LED. SPEED low indicates that the HomePNA PHY is currently in the high-speed mode. When operating in the 10BASE-T mode this output will be held high. LED_POWER LED_POWER Output This output is designed to directly drive an LED. POWER low indicates that the HomePNA PHY is cur- rently in high-power mode. When operating in the 10BASE-T mode this output will be held high. RESET RESET Input The RESET is an active-low, asynchronous RESET signal. This signal must be held low for a minimum of µs and requires 60 µs for recovery after the rising edge of RESET. GPSI Interface RXDAT Receive Data Output RXDAT is the serial data received from the selected port. Data on RXDAT is driven on the falling edge of RXCLK. RXCLK Receive Data Clock Output RXCLK provides the timing reference for transfer of the receive data. RXCLK is driven by the device and operates at a maximum frequency of 10 MHz. RXCRS Receive Carrier Sense Output The RXCRS pin is active during receive or transmit ac- tivity for the HomePNA PHY or during receive (based on TBR17, bit 2) for the 10BASE-T PHY . CLS Collision Output This signal is asserted whenever a collision is detected on the transmit and receive path of the selected port. This signal will also be asserted for ~1 µs within 40 µs after the negation of the TXEN signal in support of the SQE test. The SQE functionality may be controlled via TBR17, bit 11, and HPR16, bit 12. TXDAT Transmit Data Input TXDAT is the serial data driven from the MAC. Data on TXDAT is latched on the falling edge of TXCLK. TXCLK Transmit Data Clock Output TXCLK provides the timing reference for transfer of the transmitted data. TXCLK is driven by the device and operates at a maximum frequency of 10 MHz. TXEN Transmit Enable Input TXEN indicates when the MAC device is presenting valid transmit data on the TXDA T pin. TXEN must be asserted with the first bit of preamble and remain as- serted throughout the duration of the packet until it is deasserted prior to the first TXCLK following the final bit of the frame. TXEN transitions are synchronous to TXCLK. SPI Interface (Slave Mode Only) SCLK SPI Clock Input SCLK is driven from the controlling device as a timing reference for transfer of information on the SDI and SDO signals. The maximum clock frequency is 2.5 MHz. CS SPI Chip Select Input This pin is used to enable the Am79C901A for slave mode transfers. When this pin is inactive (HIGH), the device ignores SCLK and SDI inputs and holds SDO in high-impedance. SDI SPI Serial Data In Input This data line provides input data from the master de- vice to the Am79C901A. The data presented on this pin is latched on the rising edge of SCLK. SDO SPI Serial Data Out Output This data line provides output data from the Am79C901A to the master device. To provide for a ro- bust interface, this data is driven on the rising edge of SCLK. MII Interface RX_CLK Receive Clock Output RX_CLK is a clock input that provides the timing ref- erence for the transfer of the RX_DV, RXD[3:0], and RX_ER signals from the Am79C901A device. RX_CLK will provide a nibble rate clock. It operates at a maximum frequency of 2.5 MHz.

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RXD[3:0] Receive Data Output RXD[3:0] is the nibble-wide receive data bus. Data on RXD[3:0] is driven on the falling edge of RX_CLK. RXD[3:0] should be ignored while RX_DV is deasserted. RX_DV Receive Data Valid Output RX_DV is an output used to indicate that valid received data is being presented on the RXD[3:0] pins and RX_CLK is synchronous to the receive data. RX_DV will be asserted prior to the RX_CLK rising edge, when the first nibble of the Start of Frame Delimiter (SFD) is driven on RXD[3:0], and will remain asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0]. RX_DV will be deasserted prior to the RX_CLK rising edge which follows this final nibble. RX_DV transitions are driven on the falling edge of RX_CLK. CRS Carrier Sense Output The CRS pin is active during receive or transmit activity for the HomePNA PHY or during receive (based on TBR17, bit 2) for the 10BASE-T PHY . COL Collision Output This signal is asserted whenever a collision is detected on the transmit and receive path of the selected port. This signal will also be asserted for ~1 µs within 40 µs after the negation of the TXEN signal in support of the SQE test. The SQE functionality may be controlled via TBR17, bit 11, and HPR16, bit 12. RX_ER Receive Error Output RX_ER is an output for the 10BASE-T PHY that indi- cates that the transceiver device has detected a coding error in the receive data frame currently being trans- ferred on the RXD[3:0] pins. RX_ER is ignored while RX_DV is deasserted. Special code groups generated on RXD while RX_DV is deasserted are ignored (e.g., bad SSD in TX and idle in T4). RX_ER transitions are synchronous to RX_CLK. TX_CLK Transmit Clock Output TX_CLK is a clock output that provides the timing ref- erence for the transfer of the TXD[3:0] and TX_ER sig- nals from the Am79C901A device. TX_CLK provides a nibble rate clock. TXD[3:0] Transmit Data Input TXD[3:0] is the nibble-wide data bus. Valid data is gen- erated on TXD[3:0] on every rising edge of TX_CLK while TX_EN is asserted. While TX_EN is deasserted, TXD[3:0] values are ignored. TXD[3:0] transitions are latched on the falling edge of TX_CLK. TX_EN Transmit Enable Input TX_EN indicates that the MAC device is presenting valid transmit data on the TXD[3:0] bus. TX_EN must be asserted with the first nibble of preamble and re- mains asserted throughout the duration of the packet until it is deasserted prior to the first TX_CLK following the final nibble of the frame. TX_EN transitions are latched on the falling edge of TX_CLK. MDC Management Data Clock Input MDC is the non-continuous clock input that provides a timing reference for bits on the MDIO pin. During MII management port operations, MDC runs at a nominal frequency of 2.5 MHz. MDIO Management Data Input/Output Input/Output MDIO is a bidirectional MII management port data pin. MDIO is an input during the header portion of the man- agement frame transfers and during the data portion of write operations. MDIO is an output during the data portion of read operations. The MDIO pin should be externally pulled up to V DD with a 1.5 kΩ ±5% resistor. IEEE 1149.1 (JTAG) Test Access Port Interface TCK Test Clock Input TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency of up to 10 MHz. TCK has an internal pull-up resistor. TDI Test Data In Input TDI is the test data input path to the Am79C901A PHY . The pin has an internal pull-up resistor. TDO Test Data Out Output TDO is the test data output path from the Am79C901A PHY . The pin is tri-stated when the JTAG port is inactive.

fine the specific boundary scan test to be executed. The pin has an internal pull-up resistor. nected to the transmit side of the magnetics module. Ω resistor should be placed between these pins. lected bypassing the crystal circuit and clock trippler. illustrates how this pin works. Table 1. Clock Source Selection mode, this pin should be left unconnected. DVDD pins must be connected to a +3.3 V supply. AVDD pins must be connected to a +3.3 V supply. connected to VSS for normal operation.

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and IEEE 802.3 specification. mand and control interface while in the GPSI mode. the Detailed Functions sections. of each type of RESET operation. nal reset operation will be performed. in the 10BASE-T PHY . These bits are self-clearing. GPSI-related state of the PHY in detail. Figure 1. Idle State signals toggle for an overall period of 583.3ns (about 1.7 MHz).

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Figure 4. TXPKT - TXEN Asserted Figure 5. TXPKT - RXCLK Active Note: TXCLK continues to toggle until the SFD is observed, as shown in the first section of the above diagram. RXCLK during packet reception.

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Figure 8. RXPKT - CLS Asserted Table 2. GPSI Timing When MII/GPSI is set to 0, the device is in “SPI” mode. mand can be sent in one CS cycle. Figure 9. Operation of the SPI Interface

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Figure 13. Normal Operation RLL25 ™ encoding scheme. See Table 4. Table 4. MII-Compatible Timing ships when the MII-compatible data interface is utilized. HomePNA header, the clock enters the data phase. 96 bit times and then returns to the Idle state. the appropriate PHY address for each PHY entity. Table 5. MII Control Frame Format

The operation field (OP) follows the start field (ST). field, and it is required to allow the drivers to turn off. prior knowledge of the appropriate PHY address. and the MII pin descriptions. Figure 14. MII Start of Transmission

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Figure 15. MII End of Transmission

96 Bit Times

1 Mbps HomePNA PHY

The integrated HomePNA transceiver is a physical layer device supporting HomePNA specification 1.0 for home phoneline networking. It provides all of the PHY layer functions required to support 1 Mbps data transfer speeds over existing residential phone wiring. All data bits are encoded into the relative time position of a pulse with respect to the previous one. The wave- form on the wire consists of a 7.5 MHz carrier sinusoid enclosed within an exponential (bell shaped) enve- lope. The waveform is produced by generating four

7.5 MHz square wave cycles and passing them

through an external bandpass filter. The HomePNA PHY frame consists of a HomePNA header that replaces the normal Ethernet 64-bit pream- ble and delimiter. The frame header is prepended to a standard Ethernet packet starting with the destination address and ending with the CRC. Only the PHY layer and its parameters are modified from that of the standard Ethernet implementation. The HomePNA PHY layer is designed to operate with a standard Ethernet MAC layer controller implementing all the CSMA/CD protocol features. The frame begins with a characteristic SYNC interval that delineates the beginning of a HomePNA frame fol- lowed by an Access ID (AID) which encodes 8 bits of AID and 4 bits of control word. The AID is used to de- tect collisions and is dynamically assigned, while the control word carries speed and power information. The AID is followed by a silence interval, then 32 bits of data reserved for PHY layer communication. These bits are accessible via internal registers and are for future use. Data encoding consists of two symbol types: an AID symbol and a data symbol. The AID symbol is always transmitted at the same speed and encodes 2 bits that determine the pulse position (one of four) relative to the previous pulse. These bits are transmitted LSB first. The access symbol interval is fixed. The data symbol interval is variable. The arriving bit stream is blocked into from 3-bit to 6-bit blocks accord- ing to a proprietary (RLL25) algorithm. The bits in each block are then used to encode a data symbol. Each symbol consists of a Data Inter Symbol Blanking Inter- val (DISBI) and then a pulse at one of 25 possible po- sitions. The bits in the data block determine the pulse position. Immediately after the pulse a new symbol in- terval begins. During the DISBI the receiver ignores all incoming pulses to allow network reflections to die out. Any station may be programmed to assume the role of a PHY master and remotely command, via the control word, the rest of the units on the network to change their transmit speed or power level. Many of the framing parameters are programmable in the HomePNA PHY and will allow modifications to transmission speed center frequency as well as noise and reflection rejection algorithms. Two default speeds are provided, low at 0.7 Mbps and high at 1 Mbps. HomePNA PHY Medium Interface Framing The HomePNA frame on the phone wire network con- sists of a header generated in the PHY prepended to an IEEE 802.3 Ethernet data packet received from the MAC layer. See Figure 16. When transmitting on the phone wire pair, the HomePNA PHY first receives an Ethernet MAC frame from the MAC. The 8 octets of preamble and delimiter are stripped off and replaced with the HomePNA PHY header described below, then transmitted on the home network with the LSB of each symbol being transmitted first. During a receive operation, the reverse process is exe- cuted. When a HomePNA PHY frame is received by the PHY , the header is stripped off and replaced with the 4 octets of preamble and delimiter of the IEEE

802.3 Ethernet MAC frame specification and then

passed on to the MAC layer.

32 Am79C901A

Figure 16. HomePNA PHY Framing terval from the preceding pulse. Table 6. HomePNA PHY Pulse Parameters 7/60E6 seconds or approximately 116.7 ns. These symbols are described in the following sections. described in the Collisions section. 22304B-18Note: Using default configurations.

34 Am79C901A

The next two AID symbols (5 and 6) encode four bits of control word information. The MSB is encoded in AID Symbol 5. Control word messages are described further in the Mode Interface section. AID Transmit Timing: The transmitter encodes the Ac- cess ID in a pulse position in each 129 TIC interval. Each AID symbol interval must have only one pulse. Pulse transmission must start in only one of the four possible positions (measured from the beginning of the Access ID symbol) defined in Table 7. AID Receive Timing: The receiver allows for jitter by establishing a window around each legal pulse posi- tion. This asymmetrical window is two TICS wide on one side of the position and one TIC wide on the other. A pulse that arrives outside of the legal AID positions is considered a COLLISION event. Collisions A Collision is detected only during Access ID and silent intervals (AID symbols 0 through 7). In general during a collision, a transmitting station will read back an AID value that does not match its own, recognize the event as a collision, and alert other stations with a JAM sig- nal. Non-transmitting stations may also detect some collisions by interpreting received non-conforming AID pulses as collisions. With two transmitters colliding, each transmitter nor- mally blanks its receive input immediately after trans- mitting (and simultaneously receiving) a pulse. Therefore, only when a transmitting station receives pulses in a position earlier than the position it transmit- ted will it recognize it as a pulse transmitted by another station and signal a collision. For this reason, guaranteed collision detection is pos- sible only as long as the spacing between successive possible pulse positions in an AID symbol (20 TICs or 2.3 µs) is greater than the roundtrip delay between the colliding nodes. At approximately 1.5 ns propagation delay per foot, the maximum distance between two HomePNA units must not be greater than 500 feet for collision detection purposes (1.5 µs roundtrip delay plus margin). The following criteria must be met to guarantee reliable collision detection: At least one HomePNA station of a colliding group must always detect a collision when the delay between the beginning of its transmitted packet and the beginning of the received colliding packet is between -1.5 µs and +1.5 µs. In general, any received pulse at a HomePNA station that does not conform to the pulse position require- ments of AID symbols 0 through 7 shall indicate a col- lision on the wire. When a transmitting station senses a collision, it emits a JAM signal to alert all other sta- tions to the collision. The following conditions signify a COLLISION event: 1. A HomePNA station receives an AID that does not match the one being sent. 2. A HomePNA station receives a pulse outside the AID_GUARD INTERVAL in AID intervals 0 to 7. 3. A HomePNA station receives a pulse inside the SILENT_INTERVAL (AID symbol 7). As in all cases, pulses received during a blanking interval are ignored. Passive stations (stations not actively transmitting dur- ing the collision) cannot reliably detect collisions. Therefore, once a collision is detected by a transmitting station, the station must inform the rest of the stations of the collision with a JAM pattern described below. Only a transmitting station emits a JAM signal. Once a collision is detected, the COLLISION signal to the MAC interface is asserted and is not reset until the MAC deactivates the TXEN signal. JAM Signal A JAM pattern consists of 1 pulse every 32 TICs and continues until at least the end of the AID intervals. After the AID interval, the JAM pattern will continue until TXEN from the MAC is deactivated. Access ID Values The access ID values for stations are randomly picked by each individual station from the set of AID numbers described in the management section. During opera- tion, each HomePNA station monitors HomePNA frames received on the wire. If it detects another Home- PNA station using the same AID, it will select a new random AID. Silence Interval (AID symbol 7) The Access ID symbols are followed by a fixed silence interval of 129 TICs. The receive blanking interval is the same as that of the AID symbols (1 through 6). Any pulses detected in the silence interval are consid- ered a COLLISION event for transmitting stations and are handled as described in the Collisions section. Data Symbols Data symbols encode data for a much higher transmis- sion rate, and they do not allow collision detection.

36 Am79C901A

If the first bit (bit A) is a one, the next three bits (B, C,
If bit A is a zero and bit B is a one, the next three bits
If bit A is a zero, bit B is a zero, and bit C is a one, the

process then continues at the root node.

Finally, if bits A, B, and C are all zeros, position 0 is
Remote Control-Word management commands
Management messages from a local management

Figure 21. RLL 25 Coding Tree

1 D0 0 E F

HomePNA PHY header is preserved.

The master station is identified on the HomePNA

wire network with an AID of FFh.

A slave is identified with an AID of 00h to EFh.
AID values of F0h to FEh are reserved for future use.

completion of the command sequence.

SET_POWER: Commands slave stations to set
SET_SPEED: Commands slave stations to set their

Table 9. Master Station Control Word Functions

VERSION_STATUS: The HomePNA PHY version of

this version to interpret the packet.

POWER_STATUS: The transmit power level of the

HIGH_POWER modes of operation.

SPEED_STATUS: The transmit speed of the slave

1 Mbps HomePNA PHY Loopback

5 LSB 0 = version 0

5M S B 0 = Set to low-power transmit mode. 1 = Set to high-power transmit mode. 6L S B 0 = Set to low-speed transmit mode. 1 = Set to high-speed transmit mode.

38 Am79C901A

suring that no system resources are required. normal Data packet within the last 400 ms time period. in the HomePNA PHY Status Register (HPR1, bit 2). the data before transmission to the network. Refer to Figure 22 for the 10BASE-T block diagram. Figure 22. 10BASE-T Transmit and Receive Data the differential driver circuitry on the TX± pins. cable that meets IEEE 802.3, Section 14.4. port is a differential twisted-pair receiver. modules or common mode chokes. case signal attenuation and crosstalk noise conditions.

allow it to enter the Link Pass state. circuits are active for an excessive period (20-150 ms). Control block to assert only the COL signal at the MII. Control block to assert both COL and CRS on the MII. ignored, but it will set the polarity to the correct state. brought down and back up again. termine the abilities of the devices sharing a link. an ordered resolution between exchanged abilities. an FLP burst to learn the abilities of the sending device. gotiation with reverse polarity link pulses. plex, then 10BASE-T half-duplex. See Table 10. est performance possible without software support. Table 10. Auto-Negotiation Capabilities

20 Mbps 10BASE-T, Full Duplex

10 Mbps 10BASE-T, Half Duplex

40 Am79C901A

Pages before connecting to the Link Partner. self-clearing. Writing a 1 to this bit causes a soft reset. still being performed; otherwise, it is cleared to zero. ditions, soft reset will be finished in 150 clock cycles. loopback mode” in TBR0, bit 14, to 1. loopback mode in TBR0 = 0), the MAC in full duplex. the receive data bus for the MAC to process and verify. nection of an LED and its supporting pull-up device. Table 11. LED Default Configuration Boundary Scan Architecture document for details. mary of supported instructions.

Shift Stage and the Parallel Output Stage, respectively.

Device ID register (32 bits) (Table 14).

latches are linked together to form a scan chain. and output pins have input-type cells. Table 15. Boundary Scan Ring Order Table 12. IEEE 1149.1 Supported Instruction Table 13. BSR Mode Of Operation

1 Capture

2 Shift

3 Update

4 System Function

Table 14. Device ID Register accordance with JEDEC publication 106-A.

53 XTAL_SEL_L IN 39

52 CRS IN 32

51 CRS OUT 32

50 CRS_COL_OEN CO –

49 COL IN 30

48 COL OUT 30

47 TXD3_CSN IN 28

46 TXD2 IN 27

45 TXD1_SDI IN 25

44 TXD0_TXDAT IN 24

43 TX_EN IN 23

42 TX_CLK_OEN CO –

41 TX_CLK IN 22

40 TX_CLK OUT 22

39 GM_MODE IN 21

38 RX_ER IN 19

37 RX_ER OUT 19

36 PHY_SEL IN 17

35 RX_CLK IN 15

34 RX_CLK OUT 15

33 RX_DV_RXEN IN 13

32 RX_DV_RXEN OUT 13

31 RXD_OEN CO –

30 RXD0_RXDAT IN 11

29 RXD0_RXDAT OUT 11

28 RXD1 IN 10

27 RXD1 OUT 10

26 RXD2 IN 9

25 RXD2 OUT 9

24 RXD3 IN 8

23 RXD3 OUT 8

22 LED_SPEED CO 6

21 LED_SPEED IN 6

20 LED_SPEED OUT 6

19 LED_POWER CO 5

42 Am79C901A

Notes: 1. IN = input cells, samples the device inputs and internal outputs; OUT = output cells, drives the device outputs and internal inputs; and CO = control cells, controls the output enable. 2. BSR Cell 0 is closest to TDO.

18 LED_POWER IN 5

17 LED_POWER OUT 5

No. Cell Name Cell Type1 Pin No.

16 LED_ACTIVITY CO 3

15 LED_ACTIVITY IN 3

14 LED_ACTIVITY OUT 3

13 LED_COL CO 2

12 LED_COL IN 2

11 LED_COL OUT 2

10 LED_LINK CO 1

9L E D _ L I N K I N 1 8L E D _ L I N K O U T 1

7 MDC_SCLK IN 68

4 MDIO_OEN CO –

2P H Y _ A D I N 6 4 1M O D E _ M I I I N 6 3 0 RESET_L IN 613. Boundary register is 54 bits long. Data path starts from TDI to cell 53, cell 0 to TDO.

1 Mbps HomePNA PHY Management

implemented in the HomePNA PHY . Table 16. 1 Mbps HomePNA PHY Management Registers (HPRs)

0 HPR0 Control Register B 0400h

1 HPR1 Status Register B 0841h

2 HPR2 PHY_ID Register E 0000h

3 HPR3 PHY_ID Register E 6B91h

4 HPR4 Auto-Negotiation Register E 0021h

5 HPR5 Auto-Negotiation Register E 0000h

6 HPR6 Auto-Negotiation Register E 0000h

7 HPR7 Auto-Negotiation Register E 0000h

16 HPR16 PHY Control Register E 0005h

17 HPR17 Status/Control Register E 000xh

18 HPR18 PHY TXCOMM Register E 0000h

19 HPR19 PHY TXCOMM Register E 0000h

20 HPR20 PHY RXCOMM Register E 0000h

21 HPR21 PHY RXCOMM Register E 0000h

22 HPR22 PHY AID Register E 0000h

23 HPR23 PHY Noise Control Register E 03FFh

24 HPR24 PHY Noise Control 2 Register E F4xxh

25 HPR25 PHY Noise Statistics Register E 03FFh

26 HPR26 Event Status Register E 0000h

27 HPR27 AID Control Register E 1440h

28 HPR28 ISBI Control Register E 2C1Ch

29 HPR29 TX Control Register E 0444h

30 HPR30 Drive Level Control Register E x549h

31 HPR31 Analog Control Register E C000h

44 Am79C901A

Table 17. HPR0: HomePNA PHY Control Register (Register 0)

For collision test, the “enable loopback mode” bit must also be set to ensure that collision traffic is not imposed
R/W = Read/Write; R = Read only.

15 RESET

14 Enable Loopback Mode 1 = Loopback mode enable

13 Speed Selection 0 = 10 Mbps R0

12 Auto-Negotiation Enabled 1 = Enabled

11 Power Down

10 Isolate 1 = Electrically isolates PHY from the MII/GPSI

9 Restart Auto-Negotiation

8 Duplex Mode 1 = Full-Duplex (for Loopback test only)

7 Collision Test (Note 1) 1 = Enable COL test signal

Table 18. HPR1: HomePNA PHY Status Register (Register 1)

6 Management Frame Preamble

5 Auto-Negotiation Complete 1 = Auto-Negotiation completed

4 Remote Fault 1 = Remote fault detected

3 Auto-Negotiation Ability 1 = PHY is able to perform Auto-Negotiation

2 Link Status

1 Jabber Detect 1 = Jabber condition detected

0 Extended Capability 1 = Extended Register capability

46 Am79C901A

Table 19. HPR2: HomePNA PHY ID Register (Register 2) Table 20. HPR3: HomePNA PHY ID Register (Register 3)

guarantee the change is implemented. Table 21. HPR4: HomePNA PHY Auto-Negotiation Advertisement Register (Register 4)

15 Next Page

14 Reserved R0

13 Remote Fault

code work will have the bit position for remote fault as cleared.

9 Reserved R0

8 Full-Duplex

7 Half-Duplex

this bit does not advertise Half-Duplex capability.

6 Full-Duplex

5 Half-Duplex

this bit does not advertise Half-Duplex capability.

48 Am79C901A

Table 22. HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register - Base Page Format Table 23. HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register - Next Page Format

15 Next Page Link partner next page request R0

14 Acknowledge Link partner acknowledgment R0

13 Remote Fault Link partner remote fault request R0

13 Message Page Link partner message page request R0

12 Acknowledge 2 1 = Link partner can comply with the request

11 Toggle Link partner toggle bit R0

Table 24. HPR6: HomePNA PHY Auto-Negotiation Expansion Register (Register 6) message page with the message code set to null. Table 25. HPR7: HomePNA PHY Auto-Negotiation Next Page Register (Register 7) should not be written to at any time.

4 Parallel Detection

3 Link Partner Next

2 Next Page Able 1 = Am79C901A device channel is next page able

1 Page Received 1 = A new page has been received

0 Link Partner Auto-

15 Next Page Am79C901A device channel next page request R0

13 Message Page Am79C901A device channel message page request R0

12 Acknowledge 2

11 Toggle Am79C901A device channel toggle bit R0

50 Am79C901A

Table 26. HPR16: HomePNA PHY Control Register (Register 16) Note: Writes to bits 1 and 2 will affect speed and power on node only.

15 Remote Command 1 = Ignore Remote Commands

12 SQE_TEST Disable

11 Command Low Power 1 = Command low power

10 Command High Power 1 = Command high power

9 Command Low Speed 1 = Command low speed

8 Command High Speed 1 = Command high speed

7 Disable AID Negotiation 1 = Disable AID negotiation

6 Clear PHY -Event Counter

5 Disable Squelch adaptation 1 = Disable Squelch adaptation

4 Power Down

3 Reserved Reads will produce undefined results RX

2 High Speed 1 = Device is currently in High speed

1 High Power 1 = Device is currently in High power

0 Reserved Reads will produce undefined results R/W X

Table 27. HPR17: HomePNA PHY Status/Control Register (Register 17) Table 28. HPR18 and HPR19: HomePNA PHY TxCOMM Registers (Registers 18 and 19) Ready bit in the ISTAT register.

6 Received_Power 1 = Last packet received, was sent at High Power

5 Received_Speed 1 = Last packet received, was sent at High Speed

4 Received_Ver 1 = Last packet received, was sent at Version XX

52 Am79C901A

Table 29. HPR20 and HPR21: HomePNA PHY RxCOMM Registers (Registers 20 and 21) by subsequent received packets. Table 30. HPR22: HomePNA PHY AID Register (Register 22) the PHY is assured to select a unique AID address. defined to indicate a remote command. Table 31. HPR23: HomePNA PHY Noise Control Register (Register 23) writes to this bit will have no effect. cleared by setting bit 6 of HPR16.

Table 32. HPR24: HomePNA PHY Noise Control 2 Register (Register 24) Table 33. HPR25: HomePNA PHY Noise Statistics Register (Register 25) to raise the level at the end of an 870 ms period.

54 Am79C901A

Table 34. HPR26: HomePNA PHY Event Status Register (Register 26) facilitate software-stimulated event testing. Table 35. HPR27: HomePNA PHY AID Control Register (Register 27)

8 TxPCOM

1 Remote Command Received A valid remote command was received. Status is cleared by writing a 0. 0 Remote Command Sent A remote command has been sent. Status is cleared by writing a 0.

Table 36. HPR28: HomePNA PHY ISBI Control Register (Register 28) Table 37. HPR29: HomePNA PHY TX Control Register (Register 29) Table 38. HPR30: HomePNA PHY Drive Level Control Register (Register 30) the transmit spectrum of the PHY .

56 Am79C901A

Table 39. HPR31: HomePNA PHY Analog Control Register (Register 31) the MII basic register set and extended register set. consists of Registers 2 to 31 (decimal). Table 40. 10BASE-T PHY Management Registers (TBRs) the number of current sources enabled for transmit.

7 Force_Link_Valid 1 = Link Status bit will be held valid

0 TBR0 PHY Control Register B 1500h

1 TBR1 PHY Status Register B 1xx9h

2 TBR2 PHY Identifier Register E 0000h

3 TBR3 PHY Identifier Register E 6B71h

4 TBR4 Auto-Negotiation Advertisement Register E 0061h

5 TBR5 Auto-Negotiation Link Partner Ability RegisterE 0000h

6 TBR6 Auto-Negotiation Expansion Register E 0004h

7 TBR7 Auto-Negotiation Next Page Register E 2001h

16 TBR16 Status and Enable Register E 0000h

17 TBR17 PHY Control/Status Register E 0001h

18 TBR18 Reserved E –

19 TBR19 PHY Management Extension Register E –

24 TBR24 Summary Status Register E 0000h

Table 41. TBR0: 10BASE-T PHY Control Register (Register 0)

R/W = Read/Write, SC = Self Clearing, R = Read only.
Soft Reset does not reset the PDX block. Refer to the Soft Reset section for details.
Bits 8 and 13 have no effect if Auto-Negotiation is enabled (Bit 12 = 1).
If the ISOL pin of the chip and the Isolate bit in Register 0 is 1, this bit will be set.
The “enable loopback mode” bit must also be set to ensure that collision traffic is not imposed on the network.

15 Soft Reset (Note 2)

14 Enable Loopback Mode

13 Speed Selection

12 Auto-Negotiation Enable

8 Duplex Mode

7 Collision Test

58 Am79C901A

is read only; a write will have no effect. See Table 42. Table 42. TBR1: 10BASE-T PHY Status Register (Register 1)

LH = Latching High, LL = Latching Low.

3 Auto-Negotiation Ability 1 = PHY able to auto-negotiate,

2 Link Status 1 = Link is up

0 Extended Capability 1 = Extended register capabilities

Table 43. TBR2: 10BASE-T PHY Identifier Register (Register 2) Table 44. TBR3: 10BASE-T PHY Identifier Register (Register 3)

60 Am79C901A

link partner device. See Table 45. guarantee the change is implemented. Table 45. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) process. Setting this bit advertises Half-Duplex capability. Clearing this bit does not advertise Half-Duplex capability. process. Setting this bit advertises Half-Duplex capability. Clearing this bit does not advertise Half-Duplex capability.

logic one. See Table 46 and Table 47. Table 46. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page Format Table 47. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Next Page Format

62 Am79C901A

are Read Only. See Table 48. Table 48. TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) with the message code set to null. See Table 49. Table 49. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7)

2 Next Page Able

1 Page Received

0 Link Partner ANEG

15 Next Page Am79C901A device channel next page request R/W 0

13 Message Page Am79C901A device channel message page request R/W 1

clear the status bits. See Table 50. Table 50. TBR16: 10BASE-T Status and Enable Register (Register 16) All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.

13 Status Test Enable

a forced interrupt condition. bits in 12:9 are set) occurs.

9 Speed Change Enable

8 Global Enable

4 Link Status Change

3 Duplex Mode Change

2 Auto-Negotiation Change

1 Speed Change

0 Global

64 Am79C901A

Mbps PHY of the Am79C901A home networking device. Table 1. TBR17: 10BASE-T PHY Control/Status Register (Register 17) Note: For these loopback paths, the data is also transmitted out of the MDI pins (TX±).

13 Force Link Good Enable 1 = Link status forced to link up state

12 Disable Link Pulse

11 SQE_TEST Disable

10 Reserved R0

9 Jabber Detect Disable 1 = Disable jabber detect

6 Receive Polarity

5 Auto Receive Polarity

4 Extended Distance

3 TX_DISABLE 1 = TX± outputs not active

2 TX_CRS_EN

1 Reserved R0

0 PHY Isolated 1 = 10BASE-T PHY is isolated

Table 2. TBR19: 10BASE-T PHY Management Extension Register (Register 19) tus, Auto-Negotiation Alert, and Speed. See Table 3. Table 3. TBR24: 10BASE-T Summary Status Register (Register 24)

5 Mgmt Frame Format

2 Full-Duplex

1 Auto-Negotiation

0 Speed

66 Am79C901A

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Function- ality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Industrial (I) Devices Operating ranges define those limits between which the functionality of the device is guaranteed.

Notes: 1. VOH does not apply to open-drain output pins. 2. IOH2 applies to all other outputs. 3. IOZ applies to all output and bidirectional pins. Tests are performed at VIN = 0 V and at VDD only. 4. IIX applies to all input pins except TDI, TCLK, and TMS pins. 5. IIL and IIH apply to the TDI, TCLK, and TMS pins. 6. Parameter not tested. Value determined by characterization. 7. C CLK applies only to the CLK pin. 8. VOUT reflects output levels prior to 1: √ 2 transformer state. Parameter Symbol Parameter Description Test Conditions Min Max Units Digital I/O Voltage VIH Input HIGH Voltage 2.0 V VIH5V Input HIGH voltage (5V) 2.0 DVDD + 2.5 V VIL Input LOW Voltage 0.8 V VOL Output LOW Voltage IOL1 = 4 mA IOL2 = 6 mA IOL3 = 12 mA 0.4 V VOH Output HIGH Voltage (Notes 1, 2) IOH1 = -4 mA IOH2 = -2 mA (Note 2) 2.4 V VOUT Output Voltage on TX± (peak) (Note 8) 1.55 1.98 V VDIFF Input Differential Squelch Assert on RX± (peak) 300 520 mV VDIFF Input Differential De-Assert Voltage on RX± (peak) 150 300 mV Digital I/O Current IOZ Output Leakage Current (Note 3)0 V <VOUT <VDD -10 10 µA IIX Input Leakage Current (Note 4) 0 V < VIN < VDD -10 10 µA IIL Input LOW Current (Note 5) VIN = 0 V; VDD = 3.6 V -200 -10 µA IIH Input HIGH Current (Note 5) VIN = 2.7 V; VDD = 3.6 V -50 10 µA Power Supply Current ICC (1 Mbps) 1 Mbps mode on TX± and RX±. Outputs driving load. VDD = Maximum Transmitting maximum packets at minimum IPG. 100 mA ICC (10 Mbps) 10BASE-T mode on TX± and RX±. Outputs driving load. VDD = Maximum Transmitting maximum packets at minimum IPG. 175 mA ICC (Static) XCLK frequency = 0. VDD = Maximum 45 mA ICC (Idle) Not transmitting. VDD = Maximum 75 mA Pin Capacitance C IN Pin Capacitance FC = 1 MHz (Note 6) 10 pF C CLK CLK Pin Capacitance FC = 1 MHz (Notes 6, 7) 5 12 pF LPIN Pin Inductance FC = 1 MHz (Note 6) 20 nH

68 Am79C901A

Figure 1. Normal and Tri-State Outputs

Figure 2. 10 Mbps Transmit Timing (GPSI)

70 Am79C901A

Figure 3. 10 Mbps Receive Start of Packet Timing (GPSI)

72 Am79C901A

1 Mbps HomePNA Transmit Timing (GPSI)

Figure 6. 1 Mbps HomePNA Transmit Timing (GPSI)

1 Mbps HomePNA Receive Timing (GPSI)

Figure 7. 1 Mbps HomePNA Receive Timing (GPSI)

74 Am79C901A

1 Mbps HomePNA Clock Timing (GPSI)

Note: During AID interval, RXCLK and TXCLK stop for up to 140 µs. Figure 8. 1 Mbps HomePNA Clock Timing (GPSI)

Figure 9. 10 Mbps Transmit Timing (MII)

76 Am79C901A

Figure 10. 10 Mbps Receive Start of Packet Timing (MII)

Figure 11. 10 Mbps Receive End of Packet Timing (MII)

78 Am79C901A

Figure 12. 10 Mbps Transmit and Receive Clock Timing (MII)

1 Mbps HomePNA Transmit Timing (MII)

Figure 13. 1 Mbps HomePNA Transmit Timing (MII)

80 Am79C901A

1 Mbps HomePNA Receive Timing (MII)

Figure 14. 1 Mbps HomePNA Receive Timing (MII)

1 Mbps HomePNA Clock Timing (MII)

Note: During AID interval, RX_CLK and TX_CLK stop for up to 140 µs. Figure 15. 1 Mbps HomePNA Clock Timing (MII)

82 Am79C901A

Figure 16. MII Management Timing

Figure 17. SPI Timing

84 Am79C901A

will turn internal Carrier Sense off. Figure 18. 10 Mbps Transmit (TX±) Timing Diagram Figure 19. 10 Mbps Receive (RX±) Timing Diagram

1 Mbps HomePNA Analog

All registers at default values and VCC = 3.3 V, 25°C.
Measurements across HRTXTXP and HRTXTXN, differentially measured, with a 50 Ω resistive load.

Figure 20. HomePNA PHY AC Waveform

86 Am79C901A

Note: 1. Not tested; parameter guaranteed by design characterization. Figure 21. JTAG (IEEE 1149.1) Test Signal Timing

Figure 22. External Clock Timing

88 Am79C901A

PHYSICAL DIMENSIONS* PL 068 Plastic Leaded Chip Carrier (measured in inches) *For reference only. BSC is an ANSI standard for Basic Space Centering.

PHYSICAL DIMENSIONS* PQT 80 Thin Plastic Quad Flat Pack (measured in millimeters) *For reference only. BSC is an ANSI standard for Basic Space Centering.

90 Am79C901A

The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD ”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD ’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD ’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical im- plant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD ’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks Copyright  1999, 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. AlertIT, any1Home, eIMR, eIMR+, GigaPHY , HIMIB, HomePHY, IMR2, MACE, Magic Packet, NetPHY, PCnet, PCnet-Home, QuEST, and QuIET are trademarks of Advanced Micro Devices, Inc. RLL25 is a trademark of Tut Systems, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 22304C

Product Information

AM79C901A specifications and overview.

Summary

HomePHY Single-Chip 1/10 Mbps Home Networking PHY

Description

HomePHY Single-Chip 1/10 Mbps Home Networking PHY

Source title AM79C901A Datasheet(PDF) - Advanced Micro Devices

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