AM79C30A

AM79C30A AMD | Alldatasheet

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 09893 Rev: H Amendment/0 Issue Date: December 1998 Am79C30A/32A Digital Subscriber Controller™ (DSC™) Circuit DISTINCTIVE CHARACTERISTICS ■ Combines CCITT I.430 S/T-Interface Transceiver, D-Channel LAPD Processor, Audio ■ Processor (DSC device only), and IOM-2 Interface in a single chip ■ Special operating modes allow realization of CCITT I.430 power-compliant terminal equipment ■ S- or T-Interface Transceiver — Level 1 Physical Layer Controller — Supports point-to-point, short and extended passive bus configurations — Provides multiframe support ■ Certified protocol software support available ■ CMOS technology, TTL compatible ■ D-channel processing capability — Flag generation/detection — CRC generation/checking — Zero insertion/deletion — Four 2-byte address detectors — 32-byte receive and 16-byte transmit FIFOs BLOCK DIAGRAM S/T Interface CAP1 AINA AREF AINB EAR1 EAR2 LS1 LS2 Main Audio Processor (MAP) SBIN SCLK BCL/CH2STRB* SBIOUT SFS HSWCAP2 (Am79C30A Only) XTAL1 XTAL2 MCLK CS WR RD Peripheral Port (PP) B-channel Multiplexer (MUX) Microprocessor Interface (MUX) Oscillator (OSC) Ba Bb Bc Bd Be Bf S/T Line Interface Unit (LIU) D Channel LOUT1 LOUT2 LIN1 LIN2 D-Channel Data Link Controller (DLC) D Channel RESET D7 D6 D5 D4 D3 D2 D1 D0 INT A2 A1 A0 Microprocessor Interface Audio Interface SBP/IOM-2 Interface 09893H-1

2 Am79C30A/32A Data Sheet

DISTINCTIVE CHARACTERISTICS (continued) ■ Audio processing capability (DSC circuit only) — Registers for implementation of software-based speaker phone algorithms — Dual audio inputs — Earpiece and loudspeaker drivers — Codec/filter with A/µ selection — Programmable gain and equalization filters — Programmable sidetone level — Programmable DTMF , single tone, progress tone, and ringer tone generation — Programmable on-chip microphone amplifier ■ Pin and software compatible with the Am79C32A ISDN Data Controller (IDC™) Circuit. The Am79C32A is used in data-only applications. GENERAL DESCRIPTION The Am79C30A Digital Subscriber Controller (DSC) Circuit and Am79C32A ISDN Data Controller (IDC) Cir- cuit, shown in the Block Diagram, allow the realization of highly-integrated Terminal Equipment for the ISDN. The Am79C30A/32A is fully compatible with the CCITT-I-series recommendations for the S and T refer- ence points, ensuring that the user of the device may design TEs which conform to the international stan- dards. The Am79C30A/32A provides a 192-Kbit/s full duplex digital path over four wires between the TE located on the subscriber's premises and the NT or PABX line- card. All physical layer functions and procedures are implemented in accordance with CCITT Recommen- dation I.430, including framing, synchronization, main- tenance, and multiple terminal contention. Both point-to-point and point-to-multipoint configurations are supported. The Am79C30A/32A processes the ISDN basic rate bit stream, which consists of B1 (64 Kbit/s), B2 (64 Kbit/s), and D (16 Kbit/s) channels. The B channels are routed to and from different sections of the Am79C30A/32A under software control. The D channel is partially pro- cessed by the DSC/IDC circuit and is passed to the mi- croprocessor for further processing. The Main Audio Processor (MAP) uses Digital Signal Processing (DSP) to implement a high performance codec/filter function. The MAP interface supports a loudspeaker, an earpiece, and two separate audio in- puts. Programmable on-chip gain is provided to sim- plify use of low output level microphones. The user may alter frequency response and gain of the MAP receive and transmit paths. Tone generators are included to im- plement ringing, call progress, and DTMF signals. A Peripheral Port (PP) is provided to allow the B chan- nels to be routed off-chip for processing by other pe- ripherals. This port is configurable as either an industry-standard IOM-2 port, or as a serial bus port (SBP). The TE design process is simplified by the availability of certified protocol software packages, which provide complete system solutions through OSI Layer 3.

Note: 1. Pin 1 is marked for orientation purposes. 2. RSRVD = Reserved pin; should not be connected externally to any signal or supply. 44-Pin PLCC LOUT1 LOUT2 AV SS DV SS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT RSRVD RSRVD AV CC DV CC RESET CS RD WR DV SS RSRVD RSRVD RSRVD RSRVD RSRVD LS2 LS1 AREF LIN1 LIN2 HSW BCL/CH2STRB SBIN Am79C32A 44-Pin PLCC

4 Am79C30A/32A Data Sheet

CONNECTION DIAGRAMS (continued) Top View LOUT1 LOUT2 AV SS DV SS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT CAP1 CAP2 AV CC DV CC RESET CS RD WR DV SS AV SS AINB AINA EAR2 EAR1 LS2 LS1 AREF LIN1 LIN2 HSW BCL/CH2STRB SBIN Am79C30A Note: Pin 1 is marked for orientation purposes. 44-Pin TQFP LOUT1 LOUT2 AV SS DV SS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT RSRVD RSRVD AV CC DV CC RESET CS RD WR DV SS RSRVD RSRVD RSRVD RSRVD RSRVD LS2 LS1 RSRVD LIN1 LIN2 HSW BCL/CH2STRB SBIN Am79C32A 44-Pin TQFP

ORDERING INFORMATION

AMD ® standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Reference Appendix C, Figures 1 & 2, for specific mechanical dimensions of the two packages. DEVICE NAME/DESCRIPTION Am79C30A/32A Digital Subscriber Controller (DSC) device ISDN Data Controller (IDC) device AM79C30A/32A JC OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Plastic Quad Flat Pack (PQT044) SPEED OPTION Not Applicable Valid Combinations AM79C30A JC, VC AM79C32A JC, VC

6 Am79C30A/32A Data Sheet

PIN DESCRIPTION* Line Interface Unit (LIU) HSW Hook-Switch (Input) The HSW signal indicates if the hook-switch is on or off hook. This signal may be generated with a mechanical switch wired to ground with a pull-up resistor to V CC . Any change in the HSW state causes an interrupt. LIN1, LIN2 Subscriber Line Input (Differential Inputs) The LIN1 and LIN2 inputs interface to the subscriber (S reference point) via an isolation transformer. LIN2 is the positive input; LIN1 is the negative input. These pins are not TTL compatible. LOUT1, LOUT2 Subscriber Line Output (Differential Outputs) The LOUT1 and LOUT2 line driver output signals inter- face to the subscriber line at the S reference point via an isolation transformer and resistors. LOUT2 is the positive S-interface driver (sources current during a High mark), and LOUT1 is the negative S-interface driver (sources current during Low mark). For multi-point applications, all TEs must maintain the same polarity on the S Interface. These pins are not TTL compatible. Main Audio Processor (MAP) All MAP pins are analog, and therefore are not TTL compatible. AINA, AINB Analog (Inputs) These analog inputs allow for two separate analog (au- dio) inputs to the transmit path of the codec/filter.Input signals on either of these pins must be referenced to AREF . AREF Analog Reference (Output) This is a nominal 2.25-V reference voltage output for bi- asing the analog inputs. When the MAP is disabled, this pin is high impedance. CAP1, CAP2 Capacitor/Resistor (CAP1, Input; CAP2, Output) An external resistor and capacitor are connected in se- ries between these pins. These components are needed for the integrator in the Analog-to-Digital Con- verter (ADC). EAR1, EAR2 Earpiece Interface (Differential Outputs) EAR1 and EAR2 are the outputs from the receive path of the codec/filter. These differential outputs can di- rectly drive a minimum load of 130 ohms. LS1, LS2 Loudspeaker Interface (Differential Outputs) LS1 and LS2 are push-pull outputs which can directly drive a minimum load of 40 ohms. Microprocessor Interface (MPI) A2–A0 Address Line (Inputs) A2, A1, and A0 signals select source and destination registers for read and write operations on the data bus. CS Chip Select (Input) CS must be Low to read or write to the Am79C30A/ 32A. Data transfer occurs over the bidirectional data lines (D7–D0). D7–D0 Data Bus (Bidirectional with High-Impedance State) The eight bidirectional data bus lines are used to ex- change information with the microprocessor. D0 is the least significant bit (LSB) and D7 is the most significant bit (MSB). A High on the data bus line corresponds to a logic 1, and Low corresponds to a logic 0. These lines act as inputs when both WR and CS are active and as outputs when both RD and CS are active. When CS is inactive or both RD and WR are inactive, the D7–D0 pins are in a high-impedance state. INT Interrupt (Output) An active Low output on the INT pin informs the exter- nal microprocessor that the Am79C30A/32A needs in- terrupt service. INT is updated once every 125 µs. The INT pin remains active until the Interrupt Register (IR) is read or the Am79C30A/32A is reset. RESET Reset (Input) Reset is an active High signal which causes the Am79C30A/32A to immediately terminate its present activity and initialize to the reset condition. When reset returns Low, the Am79C30A/32A enters the Idle mode. The MCLK output remains active while RESET is held High. Note: * All signal levels are TTL compatible unless otherwise stated.

Read (Input) The active Low read signal is conditioned by CS and in- dicates that internal information is to be transferred onto the data bus. A number of internal registers are user accessible. The contents of the accessed register are transferred onto the data bus after the High to Low transition of the RD input. WR Write (Input) The active Low write signal is conditioned by CS and indicates that external information on the data bus is to be transferred to an internal register. The contents of the data bus are loaded on the Low to High transition of the WR input. Oscillator (OSC) MCLK Master Clock (Output) The MCLK output is available for use as the system clock for the microprocessor. MCLK is derived from the 12.288-MHz crystal via a programmable divider in the Am79C30A/32A which provides the following MCLK 0.768, and 0.384 MHz. XTAL1, XTAL2 External Crystal (Output, Input) XTAL1 and XTAL2 are connected to an external parallel resonant crystal for the on-chip oscillator. XTAL2 can also be connected to an external source instead of a crystal, in which case XTAL1 should be left discon- nected. The frequency must be 12.288 MHz, ± 80 ppm. Peripheral Port (PP) SBIN Serial Data (Input/Output) When the Peripheral Port is programmed to SBP mode, SBIN operates as an input for serial data. When the Pe- ripheral Port is programmed to IOM-2 mode, SBIN functions as the data input except in the special case of IOM-2 Slave mode, when it becomes an open-drain output during part or all of the IOM-2 frame, or when deactivated. SBOUT Serial Data (Input/Output) When the Peripheral Port is programmed to SBP mode, SBOUT operates as an output for serial data. When the Peripheral Port is programmed to IOM-2 mode, SBOUT functions as the data output except in the special case of IOM-2 Slave mode when it becomes an input during part or all of the IOM-2 frame. SCLK Serial Data Clock (Input/Output) When the PP is programmed to SBP mode, SCLK out- puts a 192-kHz data clock, which may be inverted under software control. When the PP is programmed to IOM-2 Master mode, SCLK outputs a 1.536-MHz 2X data clock. In IOM-2 Slave mode, SCLK functions as the clock input. The SCLK pin defaults to a high-imped- ance state upon reset, but becomes active after any MUX connection is made or if the PP is programmed to IOM-2 Master mode. SFS Serial Frame Sync (Input/Output) In SBP mode, SFS outputs an 8-kHz frame synchroni- zation signal. SFS is an output in IOM-2 Master mode, and an input in IOM-2 Slave mode. As an output, SFS is active for 8-bit periods. The SFS pin defaults to a high-impedance state upon reset, but becomes active after any MUX connection is made or if the PP is pro- grammed to IOM-2 Master mode. For SBP mode, the active signal state is Low during Idle and 8 kHz in Ac- tive Data Only and Active Voice and Data modes. BCL/CH2STRB Bit Clock/SBP Channel 2 Strobe (Output, Three-state) In SBP mode, this pin provides a strobe during the 8-bit times of the second 64-kbit/s data channel. In IOM-2 Master mode, this pin provides a 768-kHz bit clock to aid in the connection of non-IOM-2 devices to the port. In IOM-2 Slave mode, this pin is high-impedance. Power Supply Pins PLCC/TQFP Packages AV CC +5-V analog power supply, ±5% AV SS Analog ground DV SS Digital ground DV CC +5-V digital power supply, ±5% Note: For best performance, decoupling capacitors should be in- stalled between VCC and VSS as close to the chip as possible. Do not use separate supplies for analog and digital power and ground connections.

8 Am79C30A/32A Data Sheet

The minimization of power consumption is a key factor in the design of Terminal Equipment for the ISDN, and the DSC/IDC circuit employs two basic approaches to power management: 1. The power consumption of the DSC/IDC circuit it- self is managed by using four basic power modes which allow unused functional blocks to be dis- abled. The INIT register may be programmed to se- lect Active Voice and Data, Active Data Only, Idle, or Power-Down mode, depending upon which DSC/ IDC device resources are required at the time. 2. The power consumption of the controlling micro-pro- cessor system may be controlled by driving the pro- cessor clock with the DSC/IDC circuit MCLK output. A wide range of MCLK operating frequencies may be selected, and a special Clock Speed-Up function is provided which increases the speed of MCLK upon the occurrence of a key event, without processor in- tervention. Control of MCLK frequency and Clock Speed-up is accomplished by programming the INIT and INIT2 registers, as described later. Active Voice and Data Mode In Active Voice and Data mode all functional blocks of the DSC/IDC circuit are available. Device registers may be accessed through the MPI, the LIU and DLC are available, the OSC is running, the Peripheral Port is available, MUX connections may be made, the Sec- ondary Tone Ringer may be activated, and the MAP is operational (DSC circuit only). Active Data Only Mode Active Data Only mode is similar to Active Voice and Data mode, except that the MAP (DSC circuit only) is disabled to reduce system power consumption. This in- creases the amount of power available for the Second- ary Tone Ringer or microprocessor system during the phases of call setup and teardown, or during a data-only telephone call. Idle Mode Idle mode is the RESET default mode of DSC/IDCcir- cuit operation, and represents an operational state in which power consumption is reduced, yet the micropro- cessor system is operational to program DSC/IDC cir- cuit registers or perform other required background tasks. Idle mode may also be entered by appropriate programming of the INIT register. In Idle mode, the MCLK output is available to drive the microprocessor system, the MPI is available for pro- gramming of DSC/IDC registers, and the LIU is avail- able to initiate or respond to S/T interface activity. The HSW hookswitch interrupt is also available in Idle mode. Idle mode reduces DSC/IDC circuit power consump- tion by disabling the MUX, DLC, and MAP functional blocks. The Peripheral Port is also disabled, except that an IOM-2 activation request interrupt is possible, and the SFS and SCLK outputs may still be activated. The SFS and SCLK outputs are high impedance upon RE- SET, but become active after any MUX connection is programmed. The DLC read-only registers are cleared when the DSC/IDC circuit enters the Idle mode. Power-Down Mode Power-Down mode consumes the least power of all the DSC/IDC power options, and differs from Idle mode in that all clocks, including the XTAL oscillator, are stopped. Most functional blocks are disabled, except for those required to recognize key external events that will force the DSC/IDC circuit to return to Idle mode. The Power-Down mode is not available unless the Power-Down Enable bit is set in the INIT2 register; see the INIT2 register description for further details. Entering the Power-Down Mode The Power-Down mode is entered by appropriate pro- gramming of the INIT and INIT2 registers. Selection of the Power-Down mode causes the DSC/IDCcircuit to begin an internal countdown of at least 250 MCLK cy- cles after which the MCLK and XTAL1 outputs are both stopped and held High, and the XTAL2input will be dis- regarded. The purpose of this countdown cycle is to allow the microprocessor time for housekeeping oper- ations before its clock is stopped. If an interrupt causes the DSC INT pin to go Low during the countdown, the Power-Down mode bits in the INIT register will be reset and the countdown will be canceled. If the LIU is enabled and in any state other than F3 at the end of the countdown, MCLK is stopped but the os- cillator continues to run. This allows the LIU to identify the incoming signal and either (1) generate an interrupt and force the DSC/IDC circuit to Idle mode when acti- vation is complete, or (2) move to the F3 state and stop the oscillator once the line goes idle. Exiting the Power-Down Mode The DSC/IDC circuit will exit the Power-Down mode and enter the Idle mode if any of the following events occur:

• The DSC/IDC circuit receives a hardware reset via the RESET pin.
• T h e C S and WR pins are both pulled Low at the same time, as would occur during a normal write operation from the microprocessor to the DSC cir- cuit. No data will be transferred by this operation.
• The HSW hookswitch pin changes state, and the hookswitch interrupt is enabled.

• The LIU receiver is enabled, detects an incoming signal on the S/T Interface, and achieves activation as indicated by a transition to state F7. Both the INT pin and the F7 transition interrupt must be enabled for Power-Down mode to be exited. If the LIU is en- abled, it may restart the oscillator so that it can iden- tify the activity on the interface. If the activity is determined to be noise, the LIU will stop the oscilla- tor and continue to monitor the line without an inter- rupt or returning to Idle mode.
• The IOM-2 Interface is enabled as a clock master and the SBIN input pin goes Low. This indicates that a slave device wants to activate the IOM-2 Interface and communicate with the DSC circuit. Both the INT pin and the IOM-2 timing request interrupts must be enabled for Power-Down mode to be exited.
• The IOM-2 Interface is enabled as a clock slave and the SCLK input pin goes High. This indicates that the master device is activating the IOM-2 Interface and the DSC circuit must wake up in order to moni- tor the data. Both the INT pin and the IOM-2 timing request interrupts must be enabled for Power-Down mode to be exited. If the DSC/IDC circuit is awakened by any condition other than RESET , the MCLK output will be restored to its previously programmed frequency, and will not gen- erate any shortened or spurious output cycles. If the DSC/IDC circuit is revived by RESET , MCLK will default to its normal 6.144-MHz rate. The DSC/IDC circuit pro- vides a minimum of two MCLK cycles prior to activating the interrupt pin when exiting Power-Down mode. MCLK Frequency Control The MCLK frequency selection bits in the INIT register are unchanged from Revision D. However, additional MCLK frequencies are available by programming bits in the INIT2 register. No shortened or spurious clock pulses that might disrupt the external microprocessor will result when the MCLK frequency is changed. In order to reduce the probability of errant software dis- rupting system operation, the INIT2 register requires two consecutive writes before the value will be entered into the register. Note that there will be no MCLK count- down as is the case for entering Power-Down mode if INIT2 is programmed to cause MCLK to STOP , and there will be no shortened or spurious MCLK pulses. MCLK Clock Speed-up Function A programmable automatic MCLK speed-up option is provided that will force a hardware reset of INIT2 bits 3-0, which will cause the MCLK frequency to be re- stored to the value programmed in the INIT register. There are two events that will trigger the clock speed-up function: 1. The DLC receive FIFO threshold has been reached; or, 2. a second packet begins to be received while data from a prior packet is still in the receive FIFO. The second packet case requires provision of an inter- rupt; see the DLC register section for further informa- tion. The clock speed-up function allows the user to program a very slow MCLK frequency using INIT2 when D-channel activity is minimal. If a burst of activity is seen on the D channel and it exceeds the pro- grammed threshold of the receive FIFO or threatens to overrun the receive FIFO status buffers, MCLK will in- stantly toggle back to the higher frequency pro- grammed in the INIT register. This eliminates the latency incurred if an interrupt has to be serviced to change the clock speed, and allows the overall system power to be reduced during typical voice connections. Note that automatic clock speed-up will not function un- less at least one of the associated interrupts are en- abled so the processor can be informed that the clock speed has been altered. Global Register Functions INIT Register (INIT) default = 00H Address = Indirect 21 Hex, Read/Write

Table 1. INIT Register

0 X X X X X X X DLC transmitter abort disabled

1 X X X X X X X DLC transmitter abort enabled

10 Am79C30A/32A Data Sheet

1. Write the INIT2 address to the Command Register.
2. Write to the Data Register (INIT2 is not yet up-
3. Write the INIT2 address to the Command Register.
4. Write to the Data Register (INIT2 is updated).

direct accesses to the DSC/IDC circuit. pin deactivates the INT pin and clears the IR. Table 2. INIT2 Register

00 XXXXXXR e s e r v e d , m u s t b e w r i t t e n t o 0 ;

Table 3. Reset Pin Conditions

Am79C30A/32A Data Sheet 11 Bc buffers must be accessed within 122.4 µs. This is to prevent erroneous data transfers. Only one interrupt is used to signal accessibility for both B channels of the S Interface. Since the data transfer must occur synchro- nously to the S Interface, any data access to either Bb or Bc or both must be made within the122.4 µs limit. Note that even though only a single interrupt is issued, either or both S-Interface B channels must be serviced. IR bits 2, 3, 5, 6, and 7, if set, indicate that a bit has been set in the associated status or error register. All of the interrupts generated by the Am79C30A/32A can be individually disabled. In the case of IR bit 7, the inter- rupt can also be masked by setting PPIER bit 7 to 0. DMR1, DMR2, DMR3, LMR2, MCR4, and MF control the mask conditions that affect the INT pin. The INT pin is activated only by interrupts that are not disabled. The Interrupt Register reflects the status of enabled inter- rupts. The INT pin can be disabled by setting INIT Reg- ister bit 2 to a logical 1. The Am79C30A/32A has facilities that allow the micro- processor to read the status registers (status update is inhibited during status read) or the IR at any time dur- ing functional operation.

12 Am79C30A/32A Data Sheet

Table 4. Format of the Interrupt Register (IR), Read Only

0 D-channel transmit threshold interrupt/load D-channel T ransmit buffer DMR1 bit 0

1 D-channel receive threshold interrupt/read D-channel Receive buffer DMR1 bit 1

2 D-channel status interrupt/read DSR1

3 D-channel error interrupt/read DER and DSR2 bit 2

4 Bb or Bc byte available or buffer empty interrupt/read or write Bb or Bc buffers MCR4 bit 3

5 LIU status interrupt/read LSR

6 D-channel status interrupt/read DSR2

7 Multiframe or PP interrupt/read MFSB and PPSR

ters, coefficient RAM, and transmit/receive buffers. External connections to the MPI are shown in Table 5. and A0 input pins, as defined below by Table 6. read or written to the DR after the CR has been loaded. are automatically terminated. The RD and WR signals must never both be Low under normal operating conditions. Table 5. MPI External Interface Table 6. Direct Register Access Guide

010000 C o m m a n d R e g i s t e r ( C R ) W

001000 I n t e r r u p t R e g i s t e r ( I R ) R

010001 D a t a R e g i s t e r ( D R ) W

001001 D a t a R e g i s t e r ( D R ) R

001010 D - c h annel Status Register 1 (DSR1) R

001011 D - c h annel Error Register (DER) (2-byte FIFO) R

010100 D - c h annel Transmit buffer (DCTB) (8- or 16-byte FIFO) W

001100 D - c h annel Receive buffer (DCRB) (8- or 32-byte FIFO) R

010101 B b - c hannel Transmit buffer (BBTB) W

001101 B b - c hannel Receive buffer (BBRB) R

010110 B c - c hannel T ransmit buffer (BCTB) W

001110 B c - c hannel Receive buffer (BCRB) R

001111 D - c h annel Status Register 2 (DSR2) R

1 X X X X X No access (X = logical 0 or 1) —

14 Am79C30A/32A Data Sheet

Table 7. Indirect Register Access Guide

7 FTGR1, FTGR2 R/W 67H FTGR1, 2

8 A TGR1,A TGR2 R/W 68H A TGR1, 2

1 FRAR 1, 2, 3 R/W 81H FRAR1, 2

2 SRAR1, 2, 3 R/W 82H SRAR1, 2

4 DRLR R/W 84H LSB, MSB

5 DTCR R/W 85H LSB, MSB

one for the receive direction, as shown in Figure 1. CCITT recommendations for the S Interface. nized to the received frame.

9 DRCR R 89H LSB, MSB

10 RNGR1 (LSB) R/W 8AH One byte transferred

11 RNGR2 (MSB) R/W 8BH One byte transferred

12 FRAR4 R/W 8CH One byte transferred

13 SRAR4 R/W 8DH One byte transferred

3 PPIER R/W C2H One byte transferred

Table 7. Indirect Register Access Guide (Continued)

16 Am79C30A/32A Data Sheet

three marks above receive threshold. consists of several groups of bits. chronization at the start of the next multiframe. (MFSB) once the S-bit available bit (MFSB bit 5) is set. upon the reception of a non-zero S-channel word. lows subsequent valid all-zero words to be received. ceived words within the multiframe. Figure 1. LIU Block Diagram

is repeated in the next multiframe. framing synchronization is re-established. Table 8. Multiframing Structures

18 Am79C30A/32A Data Sheet

The LIU contains the registers shown in Table 9. The LSR format is shown in Table 10. cess. Its default value after reset is 0. The LPR format is shown in Table 11. Table 9. LIU Registers

1 MFSB

Table 10. LIU Status Register

3 Change of state to F3 If LMR2 bit 3 = 1

4 Change of state from/to F7 If LMR2 bit 6 = 1

5 Change of state from/to F8 If LMR2 bit 4 = 1

6 HSW state No

7 HSW change of state If LMR2 bit 5 = 1

Table 11. LIU Priority Register

LMR1 is defined in Table 12. receiver has been enabled for a minimum of 250 µs. is cleared by reset and must be written to logical 1 in order to receive activation from the S Interface, or to request activation. LMR2 is used to select the operations found in Table 13. Table 12. LIU Mode Register 1

0 Enable B1 transmit Disable B1 transmit

1 Enable B2 transmit Disable B2 transmit

2 Disable F transmit Enable F transmit

3 Disable F

4 Activation request No activation request

5 Go from F8 to F3 No transition

6 Enable receiver/transmitter Disable receiver/transmitter

7 Reserved; must be set to logical 0 Reserved; must be set to logical 0

Table 13. LIU Mode Register 2

0 D-channel loopback at Am79C30A/32A enable D-channel loopback at Am79C30A/32A disable

1 D-channel loopback at LIU enable D-channel loopback at LIU disable

2 D-channel back-off disable D-channel back-off enable

3 F3 change of state interrupt enable F3 change of state interrupt disable

4 F8 change of state interrupt enable F8 change of state interrupt disable

5 HSW interrupt enable HSW interrupt disable

6 F7 change of state interrupt enable F7 change of state interrupt disable

20 Am79C30A/32A Data Sheet

looped back to the microprocessor. Table 14. Multiframe Register

0 Enable Multiframe sync Disable Multiframe sync

1 Enable S-data available interrupt Disable interrupt

2 Enable Q-bit buffer empty interrupt Disable interrupt

3 Enable Multiframe change of state interrupt Disable interrupt

4 First subframe Not first subframe

7 Multiframe synchronized (read only) Multiframe not synchronized (read only)

The MFSB reset default value is 40H. The MUX contains the registers found in Table 17. sor Interface), and the PP (Peripheral Port).

1. From/to the LIU channels B1 and B2
2. From/to the MAP channel Ba
3. From/to the MPI channels Bb and Bc
4. From/to the PP channels Bd, Be, and Bf

vided for both of the MPI data channels Bb and Bc.

1. In each of these three MCR registers, the channel

codes found in Table 18 are used for both ports 1 and 2. Table 15. Multiframe S-Bit/Status Buffer

1 S2 No

2 S3 No

3 S4 No

4 S5 No

5 S-data available If MF bit 1 = 1

6 Q-bit buffer empty If MF bit 2 = 1

7 Multiframe change of state If MF bit 3 = 1

Table 16. Multiframe Q-Bit Buffer

0 Q1 (default = 1)

1 Q2 (default = 1)

2 Q3 (default = 1)

3 Q4 (default = 1)

4 Q-bit value when multiframing enabled but

Table 17. MUX Registers Table 18. MCR Register Channel Codes

0000 No connection (default value)

0001 B1 (LIU)

0010 B2 (LIU)

0011 Ba (MAP)

0100 Bb (MPI)

0101 Bc (MPI)

0110 Bd (PP channel 1)

0111 Be (PP channel 2)

1000 Bf (PP channel 3)

22 Am79C30A/32A Data Sheet

tion across the S Interface. is lost in the arrangement proposed in MCR2. Figure 2. MUX Logical Channels

the format shown in Table 19. Table 19. MUX Control Register 4

3 Enable Bb- or Bc-channel byte available interrupt (IR Bit 4) Disable interrupt

6 Reserved, must be set to logical 0 Reserved, must be set to logical 0

7 Reserved, must be set to logical 0 Reserved, must be set to logical 0

24 Am79C30A/32A Data Sheet

preamplifier is included in front of the A/D converter. ringing signals, DTMF tones, and call progress signals. **These registers can also be programmed for infinite attenuation to break the signal path if desired. Figure 3. Main Audio Processor Block Diagram

facing electret-type handsets to the DSC circuit. bits in the Extended FIFO Control Register, EFCR.6–3. The programming values are given in Table 20.

1. An ADC converts the incoming analog signal at a
2. The Band Pass filter and a series of decimators re-

ducing the sampling rate to 8 kHz.

1. The X filter is an 8-tap user-programmable filter for
2. The GX filter is a programmable gain filter that al-

0.5-dB steps. The default value is 0 dB.

1. The µ-law or A-law digital compression algorithm

A-law code. The default algorithm is µ-law code.

1. An expander converts the input A- or µ-law data to

ferred from the MUX first. The default value is µ-law.

1. The GR filter is a programmable gain filter that al-

0.5-dB steps. The default value of GR is 0 dB.

1. The GER and Sidetone Gain (STG) are program-
2. The R filter is provided to correct for speaker atten-

similar to the X filter in the transmitter.

1. A series of interpolators increases the sampling
2. A DAC converts the digital signal to the analog

these registers in the processing path.

1. The GX and GR blocks are used as gain/attenua-
2. The data is presented in compressed A-law format,
3. The data extraction point for the transmit path is
4. The data extraction point for the receive path is im-

mediately following the expander.

1. The compressed data from the transmit and receive

Table 20. Analog Sidetone

26 Am79C30A/32A Data Sheet

1. The peak registers are double-buffered and can be

register. They are cleared on read.

1. The peak registers default to “don't care” values

operations by loading the command register with 72H. enabled via MAP Mode Register 2, bits 2, 3, and 4. guaranteed to ±1.2% deviation. Generator Registers (A TGR1, A TGR2), respectively . Tone Ringer uses the amplitude programmed in A TGR2. Common frequency values are listed in Table 22. quencies are listed in Table 21. Table 21. DTMF Codes

These coefficients do not apply to the DTMF generator. See the amendment to T able 23 following page 100. Table 22. Tone Ringer and Tone Generator Table 23. Amplitude Gain Coefficients

28 Am79C30A/32A Data Sheet

for the GER filter are listed in Table 24. The gain values are rounded off to the nearest 0.1 dB. The coefficient 0008 provides an attenuation of infinity when GER gain is enabled. Table 24. GER Gain Coefficients

rounded off to the nearest 0.1 dB. Table 25. GX Gain Coefficients Table 26. GR Gain Coefficients

30 Am79C30A/32A Data Sheet

GR, GX, and/or STG are enabled. equivalent to a ± full scale signal in the transmit path. Table 29 shows the limits by design. Table 27. STG Gain Coefficients

formance requirements of the system. tended values unless greater resolution is required. hj (j = 0,1,...7) = user-defined coefficients. 16-byte transfer with the format shown in Table 30. your local AMD Sales Office for more information. ital to be tested using a local signal source. Table 28. Recommended Ranges Table 29. Design Ranges Table 30. X/R Filter Format

32 Am79C30A/32A Data Sheet

processor that the MAP digital circuitry is functional. D-D gain is approximately 2.5 dB. ferred to update the X filter. MMR2, MMR3, STRA, and STRF all default to 00 hex. Table 31. Map Registers Table 32. Default Values

transmission of DC or low frequency signals. Table 33. Map Mode Register 1

0 A-Law µ-Law

1 GX coefficient loaded from register GX bypassed; gain = 0 dB

2 GR coefficient loaded from register GR bypassed; gain = 0 dB

3 GER coefficient loaded from register GER bypassed; gain = 0 dB

4 X coefficient loaded from register X bypassed; response = flat

5 R coefficient loaded from register R bypassed; response = flat

6 Sidetone gain coefficient loaded from register STG gain = –18 dB*

7 Digital loopback #1 at MAP enabled Digital loopback #1 at MAP disabled

Table 34. Map Mode Register 2

0 AINB selected AINA selected

1 LS1/LS2 selected EAR1/EAR2 selected

2 DTMF enabled DTMF disabled

3 Tone generator enabled Tone generator disabled

4 Tone ringer enabled Tone ringer disabled

5 High pass filter disabled High pass filter enabled

6 ADC auto-zero function disabled ADC auto-zero function enabled

7 Reserved, must be Logical 0 Reserved, must be Logical 0

34 Am79C30A/32A Data Sheet

Table 35. Map Mode Register 3

0 X X X X X X X Bit 7 Reserved, must be written to 0

0 X X X 1 X X X MUTE ON, AINA and AINB inputs disabled

0 X X X 0 X X X MUTE OFF , AINA or AINB enabled

0 X X X X 0 X X Digital Loopback 2 disabled

0 X X X X X 1 X EAR and LS simultaneously enabled

0 X X X X X 0 X EAR or LS enabled by MMR2 bit 1

0 X X X X X X 1 Secondary T one Ringer enabled

0 X X X X X X 0 Secondary T one Ringer disabled

Table 36. Secondary Tone Ringer Amplitude

served and should not be used. The coefficients are defined in Table 37. Table 37. Frequencies for Secondary Tone Ringer

36 Am79C30A/32A Data Sheet

address allocation procedure. erates in the following manner. the LSB of the counter is loaded by the microprocessor. aborted at any time by setting INIT bit 6 to logical 1.

1. DSR1 bit 7 will be set after each sequence of seven

consecutive 1s followed by 0. mitted first for all bytes except the FCS. nel access protocol specifies use of mark Idle. Table 37. Frequencies for Secondary Tone Ringer (Continued)

follows five contiguous logical 1s.

1. 1-byte address signified by the LSB of the first ad-
2. 2-byte address signified by the LSB of the first ad-
3. More than 2-byte address signified by the LSB of

FRAR4 defaults to FE hex; SRAR4 defaults to FF hex. Figure 4. Level-2 Frame Structure Formats

38 Am79C30A/32A Data Sheet

Table 38. .Address Recognition ignored when matching the first incoming address byte. individually enabled/disabled via DMR1 bits 4–7. address matches, the packet will be received. address matches, the packet will be received. dress interrupt if the End of Address interrupt is enabled. threshold values set by DMR4 bits 2 and 3.

1 X X X SRAR4

1 X X X FRAR4:SRAR4

Am79C30A/32A Data Sheet 39 disabled, the Am79C30A/32A receives the first two bytes, issues an End of Address interrupt, and receives the packet. Both a Valid Address and an End of Ad- dress interrupt set Interrupt Register bit 2 to a logical 1 and bit 0 of the D-channel Status Register 1 (DSR1) to a logical 1. The Valid Address/End of Address interrupt can be disabled via DMR3 bit 0. There is an internal 3-byte delay which holds the first of the D-channel ad- dress bytes until the interrupt has been issued. Note that the incoming address bytes cannot be read how- ever, until the D-channel Receive Byte Available or D-channel Receive Threshold interrupt is set. After the address is received, the DLC continues to re- ceive D-channel bytes into the D-channel Receive buffer FIFO. The DLC issues an interrupt when data is available in the D-channel Receive buffer. This interrupt can be disabled by setting DMR3 bit 3 to a logical 0. The DLC also issues an interrupt when the receive threshold set in DMR4 is reached. This interrupt can be disabled by programming a logical 0 into DMR1 bit 1. By polling, the microprocessor can then read the D-channel bytes. The 3-byte delay incurred during ad- dress recognition is maintained. Therefore, the DLC re- ceives the Frame Check Sequence (FCS) before issuing an interrupt to signal the last byte of the packet has been received and appropriate status bits have been updated. If DMR3 bit 7 is set, the two FCS bytes at the end of the packet are transferred into the D-chan- nel Receive buffer along with the data. The DLC issues an interrupt when the last byte of the packet is read from the DCRB. This interrupt can be disabled by setting DMR3 bit 2 to a logical 0. After the FCS is received, the DLC receiver detects the closing flag (a bit sequence of 01111110) and then ter- minates the packet by issuing an End Of Receive Packet interrupt (bit 1 of DSR1) and returns to looking for opening flags. The DLC also terminates the packet when an abort, an overflow, or overrun error condition is detected. The End Of Receive Packet interrupt can be disabled by setting DMR1 bit 3 to a logical 0. The D-channel Receive Byte Count Register (DRCR) is a 16-bit wide, two-word deep FIFO that is used to record the number of bytes in the incoming D-channel packets. Each count is terminated by an end-of-packet condition. Thus, the DRCR informs the microprocessor of the number of bytes, including the address bytes, which have been received. The counter is updated when the last byte of a packet is placed in the D-chan- nel Receive buffer. When the FCS bytes are included in the data transferred to the D-channel Receive buffer, the FCS bytes are included in the byte count; if the FCS bytes are not included in the transfer, they are not in- cluded in the byte count. The opening flag and closing flag are not included in the byte count. The D-channel Error and Address Status Registers are also double buffered. Reading the last byte of a packet causes the DER byte to propagate to the output of the FIFO and updates the D-channel Status and Interrupt Registers accordingly. Reading the MSB of the DRCR causes the next count and associated ASR byte to propagate to the output of the FIFOs and updates the D-channel Status and Interrupt Registers accordingly. For this reason it is important to read ASR, DER, and DSR1 prior to reading the DRCR. When a receive error occurs, an End-of-Packet inter- rupt is generated and the packet is terminated. When the last byte of the associated packet is read from the D-channel Receive buffer, the appropriate DER bits are set and an error interrupt is generated. All error inter- rupts can be individually masked by setting the corre- sponding bits in DMR2 to a logical 0. There is one 16-bit D-channel Receive Byte Limit Reg- ister (DRLR). The received byte count is compared with the DRLR. When the byte count of the currently re- ceived D-channel packet exceeds the limit value, a re- ceiver overflow is detected, the packet is terminated, and an End-of-Packet interrupt is issued. D-channel Error Register (DER) bit 4 is set to a logical 1 and an overflow interrupt issued when the last byte of the as- sociated packet is read from the D-channel Receive buffer. The Overflow Error interrupt can be masked by setting DMR2 bit 4 to a logical 0. The minimum packet length is 5 bytes for a 2-byte ad- dress packet (not including flags). If the packet length is less than the above, an interrupt is issued and DER bit 5 is set to a logical 1 when the last byte of the asso- ciated packet is read from the D-channel Receive buffer. The error interrupt can be masked by setting DMR2 bit 5 to a logical 0. If packet reception is in progress and the D-channel Receive buffer is full, the microprocessor has a maxi- mum of 425 µs to respond to the D-channel Receive Data Available interrupt. If the microprocessor fails to do so, then an overrun error occurs when the data byte is overwritten. When this happens, the packet is termi- nated. DER bit 6 is set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. The Overrun Error interrupt can be masked by setting DMR2 bit 6 to logical 0. Error indication is given if two packets have been re- ceived and not serviced by the user and a third packet is received via DSR2 bit 2. When this error occurs, the third packet is terminated (not received). Error indication is given for a receiver abort (the recep- tion of seven contiguous 1s) by DER bit 0. If the number of bits received between two flags is not an integer multiple of eight (if the received packet does not contain an integral number of bytes), DER bit 1 is

40 Am79C30A/32A Data Sheet

set and an interrupt is generated when the last byte of the associated packet is read from the D-channel Re- ceive buffer. The incoming bit stream (including FCS) is run through the FCS generation and compare block. Upon receipt of the closing flag, the result is checked and must be (MSB first) 0001110100001111. Any other pattern indi- cates an FCS error, and DER bit 3 is set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. The DLC receiver does not assume the packet to be byte-aligned. The architecture supports shared flags be- tween packets, interframe fill consisting of logical 1s (Mark idle), and interframe fill consisting of flags (Flag idle). Mark idle is defined as at least 15 or more contig- uous 1s. Flag idle is defined as more than two consecu- tive flag characters, not including a closing flag. DSR2 bit 5 is set to a logical 1 while Mark idle is being detected. DSR2 bit 6 is set to a logical 1 while Flag idle is being de- tected. The receiver D-channel packet can be aborted at any time during reception by setting INIT bit 6. Transmitting D-Channel Packets The DLC Transmitter is activated when the MSB (sec- ond byte) of the 16-bit D-channel Transmit Byte Count Register (DTCR) is loaded by the microprocessor. Next, the LIU starts counting the number of consecu- tive 1s on the E-channel until the number of 1s defined by the LIU priority mechanism is detected. After the se- quence of 1s, the DLC transmitter will begin packet transmission. Address bytes for a transmit packet can be handled in two ways: they can be loaded into the transmit buffer or loaded into the Transmit Address Register (TAR). There is one 16-bit TAR which can be loaded by the mi- croprocessor. The bytes loaded into the TAR are trans- mitted LSB first followed by MSB. For LAPD operation, the LSB contains the SAPI, and the MSB contains TEI. This 16-bit address (loaded LSB first) is transmitted within the address field of the D-channel packet if en- abled by setting DMR1 bit 2 to a logical 1. If the TAR is enabled, the DTCR should be loaded with the number of bytes to be transmitted excluding the address, flags, and FCS. If the TAR is disabled, the DTCR should be loaded with the number of bytes to be transmitted ex- cluding the flags and FCS, and the microprocessor must load the address to be transmitted as the first two bytes of the D-channel packet data. The DLC issues an interrupt when a position is avail-able in the D-channel Transmit buffer. This inter- rupt can be disabled by setting DMR3 bit 5 to a logical 0. The DLC also issues an interrupt to the microproces- sor to request D-channel data bytes when the D-chan- nel Transmit buffer empties to the threshold specified in the D-channel FIFO mode register. This interrupt can be disabled by setting DMR1 bit 0 to a logical 0. If the D-channel Transmit buffer is empty, the micropro- cessor has up to 375 ms to respond to the D-channel transmit buffer interrupt. If the microprocessor fails to load the data bytes in this time frame, an underrun inter- rupt is generated in DER bit 7, and packet transmission is terminated with a transmitted abort. The Underrun in- terrupt can be masked by setting DMR2 bit 7 to a logical 0. Transmission is also terminated when a collision is de- tected or LIU loss of synchronization occurs. The D-channel Transmit Byte Count Register is decre- mented each time a byte of data is transferred from the D-channel Transmit buffer to the DLC. The count repre- sents the number of bytes left to be transferred, exclud- ing the FCS and flags. If the transmit abort bit (INIT bit 7) is set, the transmit byte count is frozen and indicates the number of bytes left to transfer, not the number of bytes transmitted. The last byte of the packet is deter- mined by the D-channel Transmit Byte Count decre- menting to zero. When this occurs, DSR2 bit 3 is set to a logical 1. After the last byte of the packet is transmitted, the DLC adds the FCS and closing flag. Then the DLC issues an interrupt (bit 6 of DSR1) to signify the end of the packet transmission. This interrupt can be masked by setting DMR3 bit 1 to a logical 0, and is reset either by reading DSR1 or when the D-channel Transmit Byte Count Register is loaded for the next packet. Once the D-channel Transmit Byte Count has decre- mented to 0, a second packet may be loaded into the D-channel Transmit FIFO. If the MSB of the D-channel Transmit Byte Count Register is loaded prior to the end-of-transmit packet interrupt, the second packet is transmitted back-to-back with the previous packet. The End-of-Transmit Packet interrupt is not set between the two packets. If the MSB of the D-channel Transmit Byte Count Register is loaded after the end-of-packet inter- rupt, the second packet is transmitted once the LIU pri- ority mechanism has been resatisfied. Collision Detection The Network T erminator echoes the transmitted D-channel data back to the DLC in the E-channel bits of the S-interface frame. If there is a difference between the data transmitted and the data echoed back, a colli- sion has occurred. The DLC alerts the microprocessor to this event by asserting the interrupt line (INT ) and setting DER bit 2. If a collision occurs during the trans- mission of an abort sequence, the interrupt is still is- sued. The collision detect interrupt can be masked by setting DMR2 bit 2 to a logical 0.

Am79C30A/32A Data Sheet 41 D-Channel Receive and Transmit Errors Non-Integer Number of Bytes A non-integer number of bytes occurs when the num- ber of D-channel bits received between opening and closing flags is not divisible by eight. If a received packet consists of a non-integer number of bytes, the DLC sets bit 1 in the D-channel Error Register (DER) to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. Frame Check Sequence Error If a received packet, including its 16-bit Frame Check Sequence, is not received perfectly, the DLC sets DER bit 3 to a logical 1 when the last byte of the associated packet is read from the Receive buffer. Receive Packet Abort If seven contiguous 1s are received while receiving a packet, the packet will be terminated. DER bit 0 will be set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. Overflow Overflow occurs when the total number of D-channel bytes within a packet (including, only when enabled, the Frame Check Sequence bytes) exceeds the limit contained in the D-channel Receive Byte Limit Regis- ter. (See Receiving D-channel Packets section.) When overflow occurs, the DLC terminates the packet, and sets DER bit 4 to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. Underflow If a received D-channel (including FCS) packet is less than 5 bytes for a 2-byte address packet, an underflow error condition occurs, and the DLC sets DER bit 5 to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer. Overrun A D-channel overrun error occurs when the receiver buffer is full, and another byte is received. This can happen if the D-channel Receive buffer fills, and is not read within 425 µs. When this error occurs, the DLC sets DER bit 6 to a logical 1 and terminates the packet. Underrun A D-channel underrun error occurs when an empty D-channel buffer is transmitted. This can happen if the D-channel Transmit buffer is not loaded within 375 µs of the D-channel Transmit buffer Empty interrupt being asserted (IR bit 0). When this error occurs, the DLC sets DER bit 7 to a logical 1 and terminates the packet. Receive Packet Lost Receive Packet Lost occurs when two outstanding packets have been received and not serviced (the mi- croprocessor has not read the DCRB register), and a third packet is received. When this error occurs, DSR2 bit 2 is set to a logical 1 and the incoming packet is ter- minated (not received). DLC REGISTERS The DLC contains the following registers. Registers Number of Registers Mnemonic First Received Byte Address Registers 4 FRAR Second Received Byte Address Registers 4 SRAR Transmit Address Register (16-bit) 1 TAR D-channel Receive Byte Limit Register (16-bit) 1 DRLR D-channel Receive Byte Count Register (16-bit) (2-word FIFO) 1 DRCR D-channel Transmit Byte Count Register (16-bit) 1 DTCR Random Number Generator Registers 2 RNGR D-channel mode registers 4 DMR Address Status Register (2-byte FIFO) 1 ASR Extended FIFO Control Register 1 EFCR D-channel Transmit buffer Register — DCTR D-channel Receive buffer Register — DCRB D-channel Status Register #1 1 DSR1 D-channel Status Register #2 1 DSR2 D-channel Error Register (2-byte FIFO) 1 DER

42 Am79C30A/32A Data Sheet

This register contains the address of the packet to be transmitted if the TAR bit is enabled (DMR1 bit 2). abled, these registers are ignored. abled, these registers are ignored. This register determines the maximum number of bytes in a received packet. This register contains the total number of received bytes. This register contains the total number of transferred bytes. generate any interrupts. DMR1 is defined in Table 39. Table 39. D-Channel Mode Register 1

0 Enable D-channel T ransmit Threshold interrupt (see IR bit 0) Disable interrupt (default value)

1 Enable D-channel Receive Threshold interrupt (see IR bit 1) Disable interrupt (default value)

2 Enable Transmit Address Register Disable T ransmit Address Register (default value)

3 Enable End of Receive Packet interrupt (see DSR1 bit 1) Disable interrupt (default value)

4 Enable FRAR1/SRAR1 Disable FRAR1/SRAR1 (default value)

5 Enable FRAR2/SRAR2 Disable FRAR2/SRAR2 (default value)

6 Enable FRAR3/SRAR3 Disable FRAR3/SRAR3 (default value)

7 Enable FRAR4/SRAR4 Disable FRAR4/SRAR4

trolled by the microprocessor and does not generate interrupts. DMR2 is defined in Table 40. Table 40. D-Channel Mode Register 2

0 Enable Receive Abort interrupt (see DER bit 0) Disable interrupt

1 Enable Non-integer Number of Bytes Received interrupt (see DER bit 1) Disable interrupt

2 Enable Collision Abort Detected interrupt (see DER bit 2) Disable interrupt

3 Enable FCS Error interrupt (see DER bit 3) Disable interrupt

4 Enable Overflow Error interrupt (see DER bit 4) Disable interrupt

5 Enable Underflow Error interrupt (see DER bit 5) Disable interrupt

6 Enable Overrun Error interrupt (see DER bit 6) Disable interrupt

7 Enable Underrun Error interrupt (see DER bit 7) Disable interrupt

Table 41. D-Channel Mode Register 3

0 Enable Valid Address/End of Address interrupt (default value) (see DSR1 bit 0) Disable interrupt

1 Enable End of Valid T ransmit Packet interrupt (default value) (see DSR1 bit 6) Disable interrupt

2 Enable Last Byte of Received Packet interrupt (see DSR2 bit 0) Disable interrupt (default value)

3 Enable Receive Byte Available interrupt (see DSR2 bit 1) Disable interrupt (default value)

4 Enable Last Byte Transmitted interrupt (see DSR2 bit 3) Disable interrupt (default value)

5 Enable T ransmit buffer Available interrupt (see DSR2 bit 4) Disable interrupt (default value)

6 Enable Received Packet Lost interrupt (see DSR2 bit 2) Disable interrupt (default value)

7 Enable FCS transfer to FIFO Disable FCS transfer to FIFO

44 Am79C30A/32A Data Sheet

The receiver and transmitter thresholds can only be changed when the Am79C30A/32A is in Idle mode. Table 42. D-Channel Mode Register 4

0 X 1 X X X X X First Received Byte only

1 X 1 X X X X X Second Received Byte only

Table 43. Address Status Register

0 FRAR1/SRAR1 address recognized No FRAR1/SRAR1 address match

1 FRAR2/SRAR2 address recognized No FRAR2/SRAR2 address match

2 FRAR3/SRAR3 address recognized No FRAR3/SRAR3 address match

3 FRAR4/SRAR4 address recognized No FRAR4/SRAR4 address match

DSR1 has the format shown in Table 44. Table 44. D-Channel Status Register 1

0 Valid Address (VA) if the address decode logic is enabled or

1 End of receive packet Not end of packet

2 Packet reception in progress Packet not being received

3 Loopback in operation at Am79C30A/32A No loopback in operation at Am79C30A/32A

4 Loopback in operation at LIU No loopback in operation at LIU

5 D-channel back-off not in operation D-channel back-off in operation

6 End of valid transmit packet No end-of-transmit packet or no transmission

7 Current transmit packet has been aborted No transmit packet abort

Table 45. DSR1 Interrupts

0 Y es, if DMR3 bit 0 = 1 T wo bytes after an opening flag if a VA is

1 Y es, if DMR1 bit 3 = 1 When a closing flag is received When the microprocessor reads DSR1 or

2 No One byte after the opening flag of any packet,

3 No When the operation is in progress When the operation is not in progress

4 No When the operation is in progress When the operation is not in progress

5 No When the operation is in progress When the operation is not in progress

7 No When seven 1s and a 0 have been transmitted When the microprocessor reads DSR1 or when

46 Am79C30A/32A Data Sheet

DSR2 has the format illustrated in Table 46. *Following RESET, the T ransmit buffer Available (bit 4) is set, producing a default value of 10H. Table 46. D-Channel Status Register 2

0 Last byte of received packet Not last byte of received packet

1 Receive byte available Receive byte not available

2 Receive packet lost Receive packet not lost

3 Last byte transmitted Last byte not transmitted

4 Transmit buffer available Transmit buffer not available*

5 Mark idle detected (15 or more contiguous 1s) Mark idle not detected

6 Flag idle detected (more than two contiguous flags) Flag idle not detected

7 Start of second received packet in FIFO Second packet not yet in FIFO

Table 47. DSR2 Interrupts

0 Y es, if DMR3 bit 2 = 1 When last byte of a received packet is read from the

1 Y es, if DMR1 bit 3 = 1 When DCRB contains one or more bytes of data When DCRB is empty

2 Y es, if DMR3 bit 6 = 1 When two outstanding packets are received and not

3 Y es, if DMR3 bit 4 = 1 When the last byte of a transmit packet is transferred from

5 No When 15 contiguous one bits have been detected in the

6 No When more than two contiguous flags are detected on the

The DER has the format illustrated in Table 48. Table 48. D-Channel Error Register

0 Received Packet Abort No abort received

1 Non-integer number of bits have been received Integer number of bits received

2 Collision Detected No error

3 FCS Error No error

4 Overflow Error No error

5 Underflow Error No error

6 Overrun Error No error

7 Underrun Error No error

Table 49. DER Interrupts

0 Y es, if DMR2 bit 0 = 1 When seven consecutive 1s are received

1 Y es, if DMR2 bit 1 = 1 Upon error condition after closing flag has

3 Y es, if DMR2 bit 3 = 1 If error occurs When the microprocessor reads the DER or

4 Y es, if DMR2 bit 4 = 1 If error occurs When the microprocessor reads the DER or

5 Y es, if DMR2 bit 5 = 1 If error occurs When the microprocessor reads the DER or

6 Y es, if DMR2 bit 6 = 1 If error occurs When the microprocessor reads the DER or

7 Y es, if DMR2 bit 7 = 1 If error occurs When the microprocessor reads the DER or when

0 X X X X 0 X X Bits 7 and 2 reserved, must be written to 0

0 X X X X 0 0 X Start of Second Received Packet In FIFO interrupt disabled

0 X X X X 0 1 X Start of Second Received Packet In FIFO interrupt enabled

0 X X X X 0 X 0 Normal mode of FIFO operation

0 X X X X 0 X 1 Extended mode of FIFO operation

48 Am79C30A/32A Data Sheet

peripherals to be connected to the DSC/IDC circuit. free-run at 192 kHz and 8 kHz respectively.

1. Connection of multiple Layer-2 devices to a Layer-1

non-IOM-2 devices is included.

1. Programming and control of Layer-1 or Layer-2 de-

for example, a U-interface transceiver. Table 50. Pin Operation versus Peripheral Port Modes *The Am79C30A is a non-Layer-1 component when operated in the Slave mode; however, it has a microprocessor interface. device and Sub-frame 1 to talk to the DSC circuit. It does not reverse its pins.

50 Am79C30A/32A Data Sheet

intercommunication channels as selected in PPCR1. S Interface is also output on the IOM-2 Interface. terface based on TIC bus access procedures. flow between the DLC and LIU. nels is utilized at any time. the IOM-2 T erminal mode frame (channel 2, byte 4). is free. This bit is driven to zero by the device that gets an address match on the TBA2–0 bits. with highest zero content in its address has the highest priority. Lowest priority address, which is also the default, is 111. E-bits (Echo): D-channel Echo bits from the S-bus. Will not be supported by the DSC. 1, D-channel transmission should be halted. A/B bit (Available/Blocked): supplementary bit for D-channel control. 1 indicates D-channel available, 0 D-channel blocked. Optional, will not be supported by the DSC. Figure 7. TIC Bus Control Bits and Definitions

Figure 8. IOM-2 Master Mode Operation

52 Am79C30A/32A Data Sheet

tion provided by TIC bus capability. Figure 9. IOM-2 Slave Mode Operation with Bus Reversal

Figure 10. IOM-2 Slave Mode Operation without Bus Reversal

54 Am79C30A/32A Data Sheet

Figure 11. IOM-2 Intelligent Configuration

Am79C30A/32A Data Sheet 55 Monitor Channel Procedures The Monitor channel operates on an event-driven ba- sis; although data transfers on the bus are synchro- nized to the frame sync, the flow of data is controlled by a handshake procedure using the outgoing MX and in- coming MR bits. Thus, the actual data rate is not fixed, but is dependent upon the response speed of transmit- ter and receiver. Figure 12 illustrates the sequence of events in the monitor handshake procedure. Idle State The outgoing MX and incoming MR bits held inactive for two or more frames indicates that the Monitor chan- nel is Idle in the outgoing direction. Start of Transmission The PPCR1 register is programmed to select one of the two monitor channels. Data is then loaded into the monitor Transmit Data Register, causing the first data byte to be presented to the bus as well as an inac- tive-to-active transition of outgoing MX. The Monitor channel transmit buffer available interrupt is also gen- erated when data is placed on the bus, indicating that the next data byte may be written to the buffer. Outgo- ing MX remains active, and the data is repeated until an inactive-to-active transition of the incoming MR is re- ceived. Subsequent Transmission Following detection of the first inactive-to-active transi- tion of incoming MR, all following bytes to be transmit- ted will be presented to the bus coincident with an active-to-inactive transition of outgoing MX. The IOM-2 specification defines a general case (Figure 12a) in which the transmitter waits for an inactive-to-active transition of incoming MR, and a maximum speed case (Figure 12c) in which the transmitter achieves a higher transmission rate by anticipating the falling edge of in- coming MR. The DSC/IDC circuit Monitor channel transmitter imple- ments the maximum speed case as follows: the second byte is placed onto the bus at the start of the frame fol- lowing the transition of incoming MR (High to Low), and a Monitor channel transmit buffer available interrupt is generated. Simultaneously, outgoing MX is returned in- active for one frame, then reactivated. Note that two frames of outgoing MX inactive signifies the end of a message. Outgoing MX and the data byte remain valid until incoming MR goes inactive. The next byte is trans- mitted during the next frame, meaning one frame after incoming MR goes inactive. In this manner, the trans- mitter is anticipating incoming MR returning active, which it will do one frame time after it is deactivated, un- less an abort is signaled from the receiver. After the last byte of data has been transmitted, indicated by the Monitor Transmit Data Register being empty and the end-of-transmission (EOM) bit being set in PPCR1, outgoing MX is deactivated in response to incoming MR going inactive, and left inactive. First Byte Reception At the time the receiver sees the first byte, indicated by the inactive-to-active transition of incoming MX, outgo- ing MR is by definition inactive. Outgoing MR is acti- vated in response to the activation of incoming MX, the data byte on the bus is loaded into the Monitor Receive Data Register, and a Monitor channel receive data available interrupt is generated. Outgoing MR remains active until the next byte is received or an end-of-mes- sage is detected (incoming MX held inactive for two or more frames). Subsequent Reception Data is received into the buffer on each falling edge of incoming MX, and a Monitor channel receive data available interrupt is generated. Note that the data was actually valid at the time incoming MX became inactive, one frame prior to becoming active. Outgoing MR is de- activated at the time data is read and reactivated one frame later. The reception of data is terminated by re- ception of an end-of-message indication, which is in- coming MX remaining inactive for two or more frames. End-of-Transmission (EOM) The transmitter sends an EOM in response to the EOM request bit being set in PPCR1. Once the EOM bit is set, the EOM is transmitted as soon as the Monitor T ransmit Data Register becomes empty. This is nor- mally done when the last byte of a message has been transmitted. The DSC/IDC circuit transmits an EOM simply by not reactivating MX after deactivating it in re- sponse to MR going inactive. The EOM request bit in PPCR1 is automatically cleared when the EOM has been transmitted, indicating that the monitor transmit- ter is available for a new message. Abort An abort is a signal from the receiver to the transmitter indicating that data has been missed. The receiver sends an abort by holding MR inactive for two or more frames in response to MX going active. An interrupt is generated when an abort is received. Flow Control The transmitter is held off until the Monitor Receive Data Register is read, since MR is held active until the receive byte is read. The transmitter will not start the next transmission cycle until MR goes inactive.

56 Am79C30A/32A Data Sheet

Figure 12. Monitor Handshake Timing

58 Am79C30A/32A Data Sheet

Register Number 1 (PPCR1). When this bit is cleared, the data output pin (SBOUT) is also forced to High-Z (seen as a High on the system bus due to the external pullup resistor), and the Am79C30A begins monitoring the data input pin (SBIN) for the presence of a timing request from any downstream units. Activation Activation can be initiated locally by the processor or re- motely by one of the downstream units. To activate lo- cally, the processor sets the activation/deactivation bit in PPCR1 (starting the clocks), and then proceeds through the software activation protocol on the C/Ichannel. For remote activation, the upstream device receives a re- quest from the downstream device via the data input pin. When the data input pin (SBIN) goes Low, Am79C30A will generate an IOM-2 timing-request interrupt, bit 6 in the Peripheral Port Status Register (PPSR). The proces- sor must respond to this interrupt, and restart the IOM-2 clocks by setting the activation/deactivation bit in PPCR1. Once the clocks are running, the downstream device can request full activation via the C/I channel using the IOM-2 software protocol. DSC/IDC Circuit as a Downstream Device (Clock Slave) Deactivation Deactivation is normally initiated by the upstream de- vice as described above. When the deactivation re- quest is received by the downstream device over the C/I channel, the processor must respond by sending the deactivation indication over the C/I channel. The upstream device will then send the deactivation confir- mation command over the C/I channel and stop the IOM-2 clocks. The Am79C30A will detect that the clock has stopped (defined as no clock pulse received for 650 ns) and force itself to the deactivated state. In the deactivated state, SBIN, and SBOUT are both forced to a High-Z state, and the SCLK input is monitored for any rising edge that would indicate an activation request from the upstream device. Activation Once again, activation can originate from either the up- stream or the downstream device. To activate the inter- face from the downstream device, the processor sets the activation/deactivation bit in the PPCR1 register. This will force the Am79C30A to pull its data output pin (SBIN in this case, since the I/O pin definition is re- versed when talking to the upstream device) Low, causing the upstream device to start the IOM-2 clocks. Once the clocks are running, as indicated by SCLK input going High, the Am79C30A will generate an IOM-2 timing request interrupt (bit 6 in PPSR). The pro- cessor must respond to the interrupt by loading the proper C/I command response into C/ITRDO, then clearing the activation/deactivation bit in PPCR1. This will release the data output pin (SBIN) from being held Low and allow the processor to complete the activation procedure by sending the proper commands over the C/I channel. When the activation is originated from the upstream device, the Am79C30A will generate an IOM-2 timing request interrupt (bit 6 in PPSR) when the IOM-2clocks become active as indicated by the SCLK input pin going High. The Am79C30A will begin normal IOM-2 transmission/reception as soon as SCLK appears; no intervention from the microprocessor is required. How- ever, the processor must respond to the interrupt and perform the normal C/I channel software handshakes before activation will be complete. TIC Bus Operation C/I0 Channel Arbitration Software control for the IOM-2 Bus Accessed (BAC) bit will be added at bit 7 of CITDR0, which is currently re- served. It will be referred to as the BAR, “Bus Access Request” bit. This bit will be used to gain access to the C/I0 channel when TIC bus support is enabled (PPCR3.3=1). The BAR bit should be set whenever the DSC has C/I0 data available to transmit. When CITDR0.7=1, the TIC bus will arbitrate access to the C/I0 channel with other devices on the IOM-2 interface using the TIC address programmed into PPCR3.2–0. The TIC bus control logic will check to see if the BAC bit on the line is 0 or 1 to determine if another down- stream device currently owns the bus. If zero, the DSC will wait. Once a one is detected in BAC, the logic will place the DSC's TIC bus address on the open drain output. It will then sample this output with the IOM-2 re- ceived data strobe timing to check for conflict with other downstream devices. If the received TIC address and the contents of PPCR3.2–0 match, the logic will set the BAC output to “0” indicating to other downstream de- vices that the DSC has taken control of the D and C/I0 channels. After it sets its BAC output to 0, the logic will compare the TIC address on the line with PPCR3.2–0 in one more frame to ensure ownership of the bus. If a mis- compare occurs, the DSC will set its BAC output to 1 and return to the beginning of arbitration. Once access is gained, the D and C/I0 channels are the possession of the DSC. This allows the DSC to complete C/I0 communication with the Layer 1 device without interruption from other downstream devices. (Since the TIC bus is used for arbitration of both D and C/I0 channel communication, gaining access for one implicitly gives you access to the other). After the DSC completes C/I0 communication, software should set CITDR0.7=0 to allow other downstream devices ac- cess to the D and C/I0 channels. The logic will set the BAC bit output of the DSC back to 1, as long as the

Am79C30A/32A Data Sheet 59 DSC has no D-channel communications also in progress. A priority scheme is included to prevent the DSC from dominating the bus. A new bus access will not be al- lowed until the device detects BAC bit set to 1 in two successive frames. Care must be taken in use of the Bus Access Request bit (CITDR0.7). As stated above, once access is gained through use of this bit, the DSC will control the D and C/I0 channels as long as it remains set. Software must remember to clear this bit to allow other devices access. D-Channel Arbitration When the TIC bus feature is enabled (PPCR3.3=1), the DLC will automatically request TIC bus access without software intervention. The access procedure is much the same as the C/I0 channel above. The TIC bus control logic will check to see if the BAC bit on the line is 0 or 1 to determine if another down- stream device currently owns the bus. If zero, the DSC will wait. Once a one is detected in BAC, the logic will place the DSC's TIC bus address on the open drain output. It will then sample this output at the IOM-2 re- ceived data strobe point to check for conflict with other downstream devices. If the received TIC address and the contents of PPCR3.2-0 match, the logic will set the BAC output to 0 indicating to other downstream de- vices that the DSC has taken control of the D and C/I0 channels. After is sets its BAC output to 0, the logic will compare the TIC address on the line with PPCR3.2-0 in one more frame to ensure ownership of the bus. If a mis- compare occurs, the DSC will set its BAC output to 1 and return to the beginning of arbitration. Once access is gained, the D and C/I0 channels are the possession of the DSC. This allows the DSC to complete D-channel communications with the Layer 1 device without interruption from other downstream de- vices. After the DSC completes D-channel communica- tion, logic will set the DSC's BAC bit output back to 1, as long as the BAC request bit (CITDR0.7) is not set. This allows other downstream devices access to the D and C/I0 channels. If CITDR0.7=1, the device assumes C/I0 communication is still in progress and the BAC output remains 0 until software clears CITDR0.7. A priority scheme is included to prevent the DSC from dominating the bus. A new bus access will not be al- lowed until the device detects BAC bit set to 1 in two successive frames.

60 Am79C30A/32A Data Sheet

The PP contains the following registers: Peripheral Port Control Register 1 (PPCR1) Default = 01 Hex Address = Indirect C0 Hex, Read/Write Registers # of Registers Mnemonic Peripheral Port Control Register 3 PPCR1, PPCR2, PPCR 3 Peripheral Port Status Register 1 PPSR Peripheral Port Interrupt Enable Register 1 PPIER Monitor Transmit Data Register 1 MTDR Monitor Receive Data Register 1 MRDR C/I Transmit Data Register 2 CITDR0, CITDR1 C/I Receive Data Register 2 CIRDR0, CIRDR1 76543210 MONTR ABORT RQST MONTR ENABL MONTR CHANL SELECT MONTR EOM RQST IC CHANL SELECT IOM 2 ACTV/ DEACT PORT MODE SELECT BIT 1 PORT MODE SELECT BIT0 Bit Function 7 Monitor Channel Abort Request— This bit is automatically cleared during RESET or manually by software as follows: to send an ABORT message, software should set this bit, wait at least two frames, then clear the bit. 6 Monitor Channel Enable— This bit only affects IOM-2 operation. When set, the selected monitor channel is enabled. When cleared, both monitor channels are disabled. Whenever the monitor channel is disabled, the Monitor T ransmit and Receive Data Register (MTDR, MRDR) are updated to their default states: MTDR = FFH, MRDR = 00H. 5 Monitor Channel Select— This bit only affects IOM-2 operation. When set, Monitor channel 1 is used (second subframe). When cleared, Monitor channel 0 is used (first subframe). 4 Monitor End-of-Message Request— When set, this bit forces the Monitor channel transmitter to send an EOM once all data written into the Monitor Transmit Data Register has been transmitted. This tells the receiving device that the message is complete. The bit is cleared by hardware when the EOM is sent by reset or by software. 3 IC Channel Select— This bit only affects IOM-2 operation. When set, the IC2 time slot is used (sixth octet after the frame sync). When cleared, the IC1 time slot is used (fifth octet after the frame sync). The unused channel is always placed in a high-impedance state. 2 IOM-2 Activation/Deactivation Bit—This bit only affects IOM-2 operation. Note that this bit controls only the starting and stopping of SCLK, BCL/CH2STRB, SFS, and the state of the SBIN/SBOUT pins; this alone does not constitute activation or deactivation of the IOM-2 bus. The activation/deactivation procedure involves the exchange of a series of commands and indications over the C/I channel. This procedure, including a state diagram, is detailed in the IOM-2 specification. IOM-2 Master mode—This bit is set by software. When deactivated, the master will turn on SCLK, BCL/CH2STRB, and SFS clocks via software by setting this bit when the SBIN pin is pulled Low, indicating that a downstream device wishes to communicate over the interface. The IOM-2 activation/deactivation bit is cleared by software or reset. When cleared, the clocks are stopped, and SBIN is monitored for the reactivation request from the slave (SBIN held Low). [Reset defaults the Peripheral Port to SBP operation.] IOM-2 Slave mode—This bit is set by software to initiate an activation request to the master. When set, the SBIN pin is driven Low, and held Low until the activation/deactivation bit is cleared by software. In response to SBIN going Low the master will start SCLK, which generates a timing request interrupt in the DSC circuit. The activation/deactivation bit is cleared by software in response to this interrupt.

Am79C30A/32A Data Sheet 61 Peripheral Port Control Register 1 (PPCR1) — (continued) Peripheral Port Status Register (PPSR) Default = Bit 1 = 1, Bits 6–2 and 0 = 0, Bit 7 is Indeterminate Address = Indirect C1 Hex, Read The Peripheral Port Status Register presents various status conditions to the user, and is only used in the IOM-2 mode. Each of these conditions can generate an interrupt to the user. The interrupts are enabled via the Peripheral Port Interrupt Enable Register. The state of the respective interrupt enable bits does not affect the setting of bits in this register. Bits 6, 3, and 2 are cleared when this register is read. Bit 1 is cleared when the Data Register is written, and bit 0 is cleared when the Data Register is read. In addition, bits 3, 2, 1, and 0 are cleared when the Monitor channel is disabled (via bit 6 of the PPCR1 Register). Because bit 7 is reserved, the default value of this register is either 02H or 82H. Bit Function 1–0 Port Mode Select Field—These two bits select the configuration of the Peripheral Port as follows. Bit Function10

00 P o r t D i s a b l e d

1 0 IOM-2 Slave mode enabled 1 1 IOM-2 Master mode enabled When the port is disabled, SBOUT , SBIN, and all port-related clocks are placed in a high-impedance state. When the DSC circuit is reset, this bit field is set to 01, and the port is not enabled until a MUX MCR register is written to. If this bit is cleared prior to such a path being programmed, the port will remain disabled until the bit is set via a software write operation. 76543210 RSRVD IOM-2 TIME RQST CHNG IN C/I 1 DATA CHNG IN C/I 0 DATA MONTR ABORT RECVD MONTR EOM RECVD MONTR XMIT BUFFR AVAIL MONTR RECV DATA AVAIL Bit Function 6 IOM-2 Timing Request— When the DSC circuit is the upstream device (master mode), this bit is set by hardware to indicate that a downstream device has requested the starting of the IOM-2 clocks. The clocks are started by software. This bit does not indicate the receipt of an activation request on the C/I channel. When the DSC circuit is the downstream component (slave mode), this bit is set in response to SCLK starting (going High) when the bus is deactivated. Notes: 1. The DSC circuit will not exit Power-Down mode in response to either a timing request or the clocks being started if this interrupt is masked. It is essential that an interrupt be generated when the DSC circuit leaves Power-Down mode. Otherwise, power consumption could increase significantly without the processor’s knowledge. 5 Change in C/I 1 Channel Status— This bit is set by hardware to indicate that the contents on the receive side of C/I channel 1 have changed since the C/I Receive Data Register was last read. 4 Change in C/I 0 Channel Status— This bit is set by hardware to indicate that the contents on the receive side of C/I channel 0have changed since the C/I Receive Data Register was last read. 3 Monitor Channel Abort Request Received— This bit is set by hardware to indicate that an abort request has been received on the monitor channel. This indicates that the receiver on the other end of the Monitor channel has failed to receive the transmitted data correctly and requests that the current transmission be discontinued and the data transmission repeated via software. 2 Monitor Channel End-of-Message Indication Received— This bit is set by hardware to indicate that an abort request has been received on the monitor channel. This indicates that the message currently being received has concluded. 1 Monitor Channel Transmit Buffer Available—This bit is set by hardware to indicate that a new byte of data can be loaded into the Monitor Transmit Data Register. 0 Monitor Channel Receive Data Available— This bit is set by hardware to indicate that a byte of data has been received on the monitor channel and is available in the Monitor Receive Data Register.

62 Am79C30A/32A Data Sheet

Peripheral Port Interrupt Enable Register (PPIER) = 1 Default = Write = 00 Hex, Read = Bit 7 = 1, Bits 6–0 = 0 Address = Indirect C2 Hex, Read/Write The Peripheral Port Interrupt Enable Register provides an individual interrupt-enable bit corresponding with eachof the status conditions in the Peripheral Port Status Register. When set, the interrupt is enabled. Clearing the bit dis- ables the interrupt. These bits are set and cleared by software. Monitor Transmit Data Register (MTDR) Default = FF Hex Address = Indirect C3 Hex, Write The Monitor Transmit Data Register is the user-visible portion of the Monitor channel Transmitter Data buffer. Data is written into this register by the user in response to a monitor transmit buffer available interrupt. It is then transmitted to the receiver on the other side of the IOM-2 bus. The MTDR is emptied when the PP is reset. Monitor Receive Data Register (MRDR) Default = 00 Hex Address = Indirect C3 Hex, Read The Monitor Receive Data Register is the user-visible portion of the Monitor channel Receiver Data buffer. Data is written into this register by the hardware as it is received over the monitor channel. A monitor data available interrupt is generated when the register is loaded. The register is overwritten by hardware only after the register has been read. The default on reset is 00 hex. 76543210 PP/MF INT EN ENABL IOM-2 TIME RQST ENABL CHNG IN C/I1 DATA ENABL CHNG IN C/I0 DATA ENABL MONTR ABORT RECVD ENABL MONTR EOM RECVD ENABL MONTR XMIT BUFFR AVAIL ENABL MONTR RECV DATA AVAIL Bit Function 7 PP/MF Interrupt Enable— When set, this bit enables the Peripheral Port and Multiframing interrupts. When cleared, the PP and MF interrupts are disabled. Notes: T o ensure proper interrupt reporting, software must disable PP/MF interrupts when the interrupt routine is entered and enable them when exiting. 76543210 DATA BIT 7 (MSB) DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0 (LSB) 76543210 DATA BIT 7 (MSB) DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0 (LSB)

Am79C30A/32A Data Sheet 63 C/I Transmit Data Register 0 (C/ITDR0) Default = 0F Hex Address = Indirect C4 Hex, Write The C/I Transmit Data Register 0 is the user-visible portion of the C/I channel 0 transmitter. Data can be written into this register by the user at any time and is transmitted continuously during each subsequent frame until changed.The register is set to its default value, 0F hex (C/I channel idle), by reset or disabling of the Peripheral Port. Bus access request bit-When set, the DSC will attempt to gain access to the C/I0 channel if TIC bus is enabled. C/I Receive Data Register 0 (C/IRDR0) Default = XF Hex Address = Indirect C4 Hex, Read The C/I Receive Data Register 0 contains data valid for two frames from C/I Receive channel 0. The register is set to its default value of XF hex by a reset or the disabling of the Peripheral Port. C/I Transmit Data Register 1 (C/ITDR1) Default = 3F Hex Address = Indirect C5 Hex, Write The C/I Transmit Data Register 1 is the user-visible portion of the C/I channel 1 transmitter. Data can be written into this register by the user at any time. It is transmitted continuously during each subsequent frame until changed. The register is set to its default value, 3F hex (C/I channel idle), by reset or disabling of the Peripheral Port. C/I Receive Data Register 1 (C/IRDR1) Default = Bits 7 and 6 are Indeterminate, Bits 5–0 = 1 Address = Indirect C5 Hex, Read The C/I Receive Data Register 1 contains the data (valid for two frames) from C/I Receive channel 1. The register is set to its default value by a reset or the disabling of the Peripheral Port. 76543210 Bus Access Request RSRVD RSRVD RSRVD C/I0 DATA BIT 3 (MSB) C/I0 DATA BIT 2 C/I0 DATA BIT 1 C/I0 DATA BIT 0 (LSB) 76543210 RSRVD RSRVD RSRVD RSRVD C/I0 DATA BIT 3 (MSB) C/I0 DATA BIT 2 C/I0 DATA BIT 1 C/I0 DATA BIT0 (LSB) 76543210 RSRVD RSRVD C/I1 DATA BIT 5 (MSB) C/I1 DATA BIT 4 C/I1 DATA BIT 3 C/I1 DATA BIT 2 C/I1 DATA BIT 1 C/I1 DATA BIT 0 (LSB) 76543210 RSRVD RSRVD C/I1 DATA BIT 5 (MSB) C/I DATA BIT 4 C/I1 DATA BIT 3 C/I1 DATA BIT 2 C/I1 DATA BIT 1 C/I1 DATA BIT 0 (LSB)

64 Am79C30A/32A Data Sheet

Peripheral Port Control Register 2 (PPCR2) Default = Bits 7, 6, and 0 = 0, Bit 5 = 1, Bits 4–1 are Indeterminate* Address = Indirect C8 Hex, Read/Write The Peripheral Port Control Register 2 controls the inversion of the SCLK output in SBP mode. This provides flexi- bility in the connection of peripheral devices to the DSC circuit. The hardware revision code is also contained in this register, which allows software to identify the revision of the hardware. Note: * The default value is revision-level dependent. Revision J will report a hardware revision code of 110. Peripheral Port Control Register 3 (PPCR3) Default = Bits 7–5 are Indeterminate, Bit 4=1, Bit 3=0, Bits 2-0= 1 Address = Indirect C9 Hex, Read/Write 76543210 REV CODE BIT 2 (MSB) REV CODE BIT 1 REV CODE BIT 0 (LSB) RSRVD RSRVD RSRVD RSRVD SCLK INVRT ENABL Bit Function 7–5 Hardware Revision Code— This read-only field reports the hardware revision level. Revision J of the DSC circuit will report a hardware revision code of 110. The hardware revision codes for E and H are 100, 010, respectively. 0 SCLK Inversion Enable— When set, the SCLK output is inverted in SBP mode. When cleared, the SCLK output is identical to the Revision D DSC circuit. This bit should not be changed while SCLK is enabled. Bit Function 7–5 RESERVED 4 SLAVE Mode Bus Reversal— PPCR3.4 controls the bus reversal function of the DSC’s IOM-2 SLAVE mode. By default (PPCR3.4=1) the Slave bus reverses to ensure backwards compatibility with previous revisions. When PPCR3.4=0 the IOM-2 bus will not reverse in SLAVE mode. This assures slave compatibility of the control function and allows use with devices such as the ISAC-S. 3 TIC Bus Enable— PPCR3.3 controls enabling and disabling of TIC bus operation. When PPCR3.3=0 which is the default condition, the IOM-2 bus will not support the TIC bus feature to ensure backwards compatibility with previous IOM-2 capable revisions of the 79C30A. The TIC bus control logic features are only enabled if PPCR3.3=1. Features enabled when PPCR3.3=1 S/G bit When the DSC is in IOM-2 MASTER mode the CTS output of the LIU is used to drive the transmitted S/G bit. This signal indicates D-channel Clear To Send status and is set when the LIU collision detection logic fulfills the programmed priority level requirements. When in IOM-2 SLAVE mode the received S/G bit is used as the Clear T o Send input into the DLC block. TIC Address Bus and Bus Accessed Refer to TIC bus operation section. 2–0 TIC Bus Address— Device address to be used on TIC bus. Default is 111.

Am79C30A/32A Data Sheet 65

APPLICATIONS

This basic feature phone is the ISDN equivalent to the common analog phone. The keypad can be a simple four-by-four single-pole switch-matrix or a larger-matrix to provide full-key system features. The display option illustrated in Figure 14 can be included in any of theap- plications shown in this section. ISDN Feature Phone with Parallel and Serial Data Ports Plus Other Peripherals Access to the CCITT R reference interface is provided via both the serial and parallel ports in Figure 15. This application may easily have voice capability added by using a DSC circuit in place of the IDC circuit. Figure 16 illustrates applications with increased B-channel data processing requirements. Am79C30A DSC Circuit Audio ProcessorTelephone Speaker PP B-Channel MUX LIU OSC MPI D-Channel DLC Surge Protection S/T Interface Hook Switch MCLK RAM ROM Interrupt Microcontroller Power Reversal Interrupt Power Controller LCD DisplayKeypad 09893H-10 Figure 14. ISDN Telephone

66 Am79C30A/32A Data Sheet

Figure 15. Terminal Adapter (V.110/V.120) With Voice Upgrade Capability

Am79C30A/32A Data Sheet 67 Analog Telephone Interface Am79C30A DSC CircuitAm85C30 or PSB82525 Audio Processor B-Channel MUXPP MPI LIU D-Channel DLC Surge Protection S/T Data Link Controller Data Link Controller Microprocessor Interface DMA Controller 80188 DMA Timers Interrupts Chip CPU Am85C30/PSB82525 Dual-Port RAM Controller Dual-Port RAM Interface ROM Optional DRAM Controller Program Memory Selects DSC Circuit Memory Clock PC Bus PC Bus Interface 09893H-12Figure 16. PC Add-On Board (1 or 2 Data Channels)

68 Am79C30A/32A Data Sheet

ELECTRICAL CHARACTERISTICS

Storage temperature –65°C to +150°C Ambient temperature Supply voltage to ground, Voltage from any pin to V DC input/output current Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maxi- mum ratings for extended periods may affect device reliability. Operating Ranges Commercial (C) devices Operating VCC range with respect Operating Ranges define those limits between which the functionality of the device is guaranteed. DC Characteristics over Commercial Operating Ranges (unless otherwise specified) Parameter Symbol Parameter Descriptions Test Conditions Preliminary Unit Min Max VIH Input High Level, except XTAL2 2.0 V CC + .25 V VIH2 Input High Level XTAL2 0.80 V CC V CC + .25 V VIL Input Low Level V SS – 0.25 0.80 V VOL Output Low Level, except SBOUT Output Low Level, SBOUT only IOL = 2 µA IOL = 7 µA 0.40 0.40 V VOH Output High Level IOH = –400 µA = –10 µA 2.4

0.90 VCC

V IOL Output Leakage Current 0 < VOUT < VCC Output in High-Z State ± 10 µA IIL Input Leakage Current Digital Inputs LIN1/LIN2 XT AL2 0 < VIN < VCC ± 10 µA ± 200 µA 5.5 (TYP) µA CI Input Capacitance Digital Input T emp = 255C Freq = 1 MHz 10 (TYP) pF CO Output Capacitance Digital Input/Output T emp = 255C Freq = 1 MHz 10 (TYP) pF

Table 51. Revision E Power Specifications for CCITT-Restricted Mode Phone Operation All power measurements assume PP disabled or in IOM-2 Deactivated mode. Table 52. MAP Analog Characteristics (Am79C30A only)

70 Am79C30A/32A Data Sheet

parameters shown in Table 54. rameters are applicable for both A- or µ-law conversion. Table 53. MAP Transmission Characteristics (Am79C30A only) Transmit Frequency Response (Attenuation vs. Receive Frequency Response (Attentuation vs.

500 Hz–600 Hz

600 Hz–1000 Hz

1020 Hz (T ransmit Gain = 0 dB)—See Figure 19

1020 Hz (Receive Gain = 0 dB)—See Figure 23

*Measured with the high pass filter and auto-zero enabled in MMR2.

Table 54. Codec Performance Specifications (Am79C30A only)

1020 Hz (Rx gain = 0)

1. An external 1-Kohm ± 5% resistor and 2200-pF ±10% capacitor are connected in series between the CAP1 and CAP2 pins
2. All tests are half-channel with the sidetone path enabled but programmed for infinite attentuation (STG = 9008 hex).
3. Transmit specs are guaranteed for both AINA and AINB inputs with the auto-zero and high-pass filters enabled in MMR2.
4. Transmit specs are tested and guaranteed with the input signal source referenced to AREF; see test circuit below.
5. Receive specs are guaranteed for both EAR1/EAR2 and LS1/LS2 outputs measured differentially. Some degradation in

performance may occur if used single ended rather than differential.

72 Am79C30A/32A Data Sheet

Figure 17. Attenuation/Frequency Distortion (Transmit) Figure 18. Group Delay Variation with Frequency (Transmit)

Figure 19. Gain Tracking Error (Transmit) (CCITT Method 2 at 1020 Hz)

74 Am79C30A/32A Data Sheet

Figure 20. Signal-to-Total Distortion Ratio (Transmit) (CCITT Method 2 at 1020 Hz) Figure 21. Attenuation/Frequency Distortion (Receive)

76 Am79C30A/32A Data Sheet

Figure 24. Signal-to-Total-Distortion Ratio (Receive) (CCITT Method 2 at 1020 Hz)

Am79C30A/32A Data Sheet 77 LIU Characteristics All of the parameters below are measured at the chip terminals and are consistent with 2:1 transformers. Parameter Symbol Parameter Descriptions Preliminary UnitMin Typ Max VLOUT Output mark amplitude measured between LOUT2 and LOUT1 (Note 1) 2.210 2.326 2.442 V VLIN Receivable input level measured between LIN2 and LIN1, with noise added as specified by CCITT I.430 section 8.6.2.1 (Note 2) 530 1800 mV ZOUT Output impedence measured between LOUT2 and LOUT1 spacing condition 20 Kohm ZIN Input impedence measured between LIN2 and LIN1 20 Kohm J Timing extraction jitter on LOUT –7 +7 % PD Total phase deviation (LOUT with respect to LIN) –7 +15 % PU Pulse unbalanced measured between LOUT2 and LOUT1 (Note 1) –5 +5 % PW Output pulse width measured between LOUT2 and LOUT1 (Note 1) 4.7 5.2 5.7 µs Notes: 1. See the equivalent test load circuit and pulse template in Figures 26 and 27. 2. The 530-mV receive input level is equivalent to 9.0 dB of attenuation from a nominal transmit level when measured at the LIN pins. Allowing 0.5-dB loss in the isolation transformer, and 1.0-dB loss in the input isolation resistors, this level will guarantee compliance to the CCITT receiver sensitivity spec of 7.5 dB when measured at the S reference point. 3. T ypical receiver performance is 220 mV.

78 Am79C30A/32A Data Sheet

Figure 25. System Interface to LIU

1. V(s-interface): Transmitter output at the S-interface reference point.
2. RL is the termination impedence at the S interface.
3. CL is the effective capacitance at the S interface.
4. R1 and R2 are the transmitter output series resistors; their value depends upon the characteristics of the pulse transformer
5. R3 and R4 are required for multipoint operation to prevent loading of the line when power is removed from the terminal.

Figure 26. Equivalent Test Load Figure 27. Differential Output Signals

Figure 28. Equivalent DC Circuit at LOUT Pins for Calculation of R1 and R2 Equation 5 should be used to determine the value of R1 and R2 for the particular transformer used by each customer.

1. RSEC is the DC impedance of the transformer secondary (IC side of transformer).
2. RPRIM is the DC impedance of the transformer primary (line side of transformer).
3. RCORD is the DC impedance of the TE connecting cord; typically 4–6 ohms.
4. N is the transformer turns ratio (N = 2 for Am79C30A/32A).
5. RL is the S-interface line impedance (50 ohms).
6. ILOUT is the desired load current for the CCITT transmission templates (7.5 mA for 50-ohm line).
7. VLOUT is the nominal output voltage from the DSC/IDC line driver.

80 Am79C30A/32A Data Sheet

Microprocessor Read/Write Timing Microprocessor Read Timing Microprocessor Write Timing Notes: 1. The read/write recovery time of 200 ns holds in all cases except when a write command register operation is followed by a read data register operation when accessing the MAP coefficient RAM. This operation requires a minimum recovery time of 450 ns. 2. Successive reads of the D-Channel Receive Buffer require a minimum cycle time (tRLRH + tRHRL ) of 480 ns. 3. Read access time is measured from the falling edge of CS or the falling edge of RD, whichever occurs last. 4. CS may go Low before either RD or WR goes Low. 5. In minimal systems, CS may be tied Low. 6. Read and write indirect register operations cannot be mixed without at least one write command register operation between them. 7. CS may go High before either RD or WR goes High. 8. If CS goes High before WR goes High, the minimum Address Hold time becomes 12 ns. 9. RD and WR pulse width, Address setup and hold, and Data setup and hold timing are measured from the points where both CS and RD or WR are Low simultaneously. Parameter Symbol Parameter Description Min Max Units tRLRH RD Pulse Width 200 ns tRHRL Read Recovery Time (Notes 1, 2) 200 ns tAVRL Address Valid to RD Low 20 ns tAHRH Address Hold After RD High 10 ns tRHCH RD High to CS High (Note 7) 0 ns tRACC Read Access Time (Note 3) 80 ns tRHDZ RD High to Data Hi-Z 50 ns tRDCS RD Low to CS Low (Note 4) 30 ns Parameter Symbol Parameter Description Min Max Units tWLWH WR Pulse Width 200 ns tWHWL Write Recovery Time (Note 1) 200 ns tAVWL Address Valid to WR Low 20 ns tAHWH Address Hold After WR High (Note 8) 10 ns tWHCH WR High to CS High (Note 7) 0 ns tDSWH Data Setup to WR High 100 ns tDHWH Data Hold After WR High 10 ns tWRCS WR Low to CS Low (Note 4) 30 ns

Figure 29. Microprocessor Read/Write Timing

82 Am79C30A/32A Data Sheet

Due to clock start-up times, the hookswitch Min and Max Debounce times are approximately 3 ms greater in Power-Down Mode. Figure 31. Reset Timing Figure 32. Hookswitch Debounce Timing

Frequency = 12.288 MHz ±80 ppm. Figure 33. External Clock Driver (XTAL2) Timing

12.288 MHz

6.144 MHz

4.069 MHz

3.072 MHz

1.536 MHz

4.096 MHz

84 Am79C30A/32A Data Sheet

Figure 34. OSC/MCLK Timing internal-phase lock-loop correction.

86 Am79C30A/32A Data Sheet

Notes: *The +163-ns value can occur once per frame for digital phase lock loop correction. **CL = 150 pF Parameter Signal Abbr Test Condition Min Max Units Data Clock Rise/Fall SCLK t R ,tF C L = 150 pF 50 ns Clock Period SCLK t SCL 1.536 MHz 487 815 ns ± 100 PPM ±163 ns* Pulse Width SCLK t WH , tWL 260 ns Frame Sync SFS t R ,tF C L = 150 pF 50 ns Frame Sync Setup/Clock SFS t SF C L = 150 pF 50 ns Frame Sync Delay/Clock SFS t FD C L = 150 pF 0 ns Frame Sync Hold/Clock SFS t FH C L = 150 pF 50 t WL + 50 ns Frame Delay SFS t DF C L = 150 pF –t WL 50 ns Data Delay/Clock SBOUT t DSC C L = 150 pF 100 ns Data Hold/Clock SBOUT t DHC C L = 150 pF 70 ns Data Setup SBIN t SD tWH + 20 ns Data Hold SBIN t HD 50 ns Parameter Signal Abbr Min Max Units Data Clock Rise/Fall SCLK t R ,tF 60 ns Clock Frequency (1/period) SCLK 1/t SCLK 1.536 MHz ±100 PPM ±163 ns* Hz Clock Delay High/Low BCL t BLH , tBHL 30 ns Pulse Width SCLK t WH , tWL 240 ns Frame Sync Rise/Fall SFS t R ,tF 60 ns Frame Set-up SFS t SF 70 ns Frame Hold/Clock SFS t FH 20 ns Frame Delay/Clock SFS t FD 0n s Frame Width High SFS t WFH 130 ns Frame Width Low SFS t WFL tSCLK ns Data Delay/Clock SBOUT t DSC 100** ns Data Hold/Clock SBOUT t DHC 70 ns Data Set-up SBIN t SD tWH + 20 ns Data Hold SBIN t HD 50 ns

Figure 37. IOM-2 Timing

• In Master Mode, SFS is 16 SCLK cycle + setup time + hold time in length.

** SFS width is 16 SCLK cycles + setup and hold time.

88 Am79C30A/32A Data Sheet

V for a logical 1, and a logical 0, respectively. Figure 38. Switching Test Input/Output Waveform Figure 39. Switching Test Load Circuit

Table 1. Coefficients for GX, GR, and STG Attenuators

90 Am79C30A/32A Data Sheet

Table 1. Coefficients for GX, GR, and STG Attenuators (Continued)

92 Am79C30A/32A Data Sheet

Table 2. Coefficients for GER Attenuators

Table 2. Coefficients for GER Attenuators (Continued)

94 Am79C30A/32A Data Sheet

96 Am79C30A/32A Data Sheet

Due to the high level of integration of the Am79C30A/ 32A DSC/IDC circuit, it is easy to overlook important design information when reading the data sheet. The following list of key design hints has been compiled to streamline the design process. A comprehensive se- ries of ISDN application notes and tutorials is available from AMD; please contact an AMD sales office or fac- tory for current information.

• The AREF pint must be used to bias the AINA and AINB inputs. There is a datasheet parameter, Vios, which states that the analog inputs must be biased to within 5 mV of AREF . AREF is nominally 2.4 V; normal device-to-device variation will exceed the 5-mV Vios specification. If a voltage other than AREF is used, transmission performance at very low signal levels will be degraded.
• The recommended method of biasing the AINA and AINB inputs is to use a 15–100 Kohm resistor be- tween the input and AREF . The signal source should be AC-coupled to the analog input. Take care that the RC formed by the biasing resistor and blocking capacitor does not distort the input signal.
• The AREF output must not be loaded with a capac- itor since it may cause the internal buffer amplifier to become unstable. For some applications involving significant gain external to the DSC circuit, the AREF output may require a simple RC noise filter. In this case, the AREF output should be isolated from the capacitor by a resistance of greater than 1 Kohm to ensure stability.
• The analog gain selection value (in MMR3) should be written before the MAP is enabled.
• The MAP auto-zero function (MMR2) should be en- abled before the MAP is enabled.
• The DSC/IDC circuit should be provided with de- coupling capacitors, situated as close as possible to the package power leads. In general, 0.1-µF ce- ramic capacitors are sufficient, but bulk decoupling capacitors will be required if the LS1 and LS2 loud- speaker outputs are driving a heavy load.
• The DSC/IDC circuit is constructed on a single sub- strate, and therefore the device power pins must not be from separate supplies. If there is a DC offset be- tween the analog and digital power-supply pins, ex- cessive current may flow through the device substrate.
• The LS1, LS2, EAR1, and EAR2 outputs are in- tended to be used differentially. Although it is possi- ble to use only a single output, the rejection of power-supply noise and internal digital noise is im- proved if the outputs are used differentially.
• Observe the maximum loading specification for the Ls and EAR outputs. When used differentially, the EAr outputs must see a minimum of 540 ohms be- tween them. Similarly, the LS outputs must see a minimum of 40 ohms. The maximum capacitive loading in either case is 100 pF .
• The LS and EAR outputs need not be matched to the load. The LS and EAR outputs are voltage driv- ers and do not assume the presence of any partic- ular load impedance. If the maximum loading specification is met, the LS and EAR outputs will function satisfactorily. In some cases, an external resistor may be used to center the desired output volume—for instance, while driving a 150-ohm ear- piece with the EAR outputs.
• If using an EAR or LS output in a single-ended fash- ion, AC-couple the pin to the load. If not, the exces- sive DC current will cause signal distortion.
• When using programmable gains and filters in the MAP , consider the dynamic range effects such as truncation error and clipping. In case of questions in any particular application, please contact the AMD applications staff for assistance.
• All MAP tone generators are referenced with re- spect to the +3-dBm0 overload voltage—that is, a 0-dB tone yields a +3-dBm0 output. Take care to avoid clipping when adding tones to signals as, for example, when generating DTMF waveforms.
• The RC connected to CAP1/CAP2 must be situated as close as possible to the DSC circuit package to reduce the amount of noise coupled in from other signal traces.
• Observe the XTAL2 frequency accuracy require- ment of 12.288 MHz ± 80 ppm. Since crystals from different manufacturers will vary, the DSC circuit os- cillator output frequency at the MCLK pin must be measured and, if necessary, the value of the crystal load capacitors should be adjusted as part of the ini- tial design procedure. An application note of oscilla- tor considerations is available from AMD (ISDN Systems Engineering Application Note, order #12557).
• If driving the XTAL2 pin with the external oscillator, it is necessary to observe the datasheet input volt- age and rise/fall time requirements. Note that the XTAL2 levels are not TTL-compatible.
• Take care in board layout of the DSC circuit, as with any sensitive analog device. An application note of DSC circuit board layout hints is available from AMD (ISDN Systems Engineering Application Note, order #12557).

Am79C30A/32A Data Sheet 97

• The sidetone path defaults to –18-dB attenuation. If disabling the sidetone path is desired, the sidetone block must be enabled and programmed for infinite attentuation.
• Consider the LIU transformers, series resistors, and IC LIU output drivers as a functional unit. Transform- ers that meet CCITT I.430 requirements with other transceivers are not necessarily appropriate for use with the DSC circuit, and vice versa.
• Interrupts should be masked when reading or writ- ing any indirect or multibyte DSC circuit registers to prevent the possibility of an interrupt occurring and destroyed the contents of the Command Register.
• If the MAP and secondary tone ringer are disabled, the EAR, AREF , and LS outputs are high-imped- ance. If the MAP is enabled, the unselected audio output is high-impedance.
• The MAP should not be enabled until after the LIU has achieved synchronization. This will eliminate the possibility of audible distortion when the internal device timing is resynchronized to the S Interface.
• To make optimum use of the MAP digital signal pro- cessing chain, use digital gain (GX) for fine adjust- ment, and analog gain (GA) for coarse adjustment.
• The user must program the Secondary Tone Ringer Frequency Register (STFR) with a legal value be- fore enabling the secondary tone ringer.
• In order to exit Power-Down Mode due to LIU acti- vation, both the F7 interrupt and the DSC/IDC cir- cuit interrupt pin must be enabled. In order to exit Power-Down Mode due to IOM-2 activation, both the IOM-2 Timing Request interrupt and the DSC/IDC circuit interrupt pin must be enabled.
• The MAP auto-zero function must be enabled prior to enabling the MAP . For all normal applications, the auto-zero function should always be enabled.
• To ensure proper operation of the filters (X and R) and gains (GX, GR, GER, STGR, and A TGR), these register blocks should not be accessed more fre- quently than 128-µs intervals. This allows the inter- nal buffers to the map to operate properly, since they are updated only once per frame.

98 Am79C30A/32A Data Sheet

Note: Dimensions are measured in inches. .685 .695 .650 .656.685 .695 .650 .656 .026 .032 .050 REF Pin 1 I.D. .042 .056 .062 .083 .590 .630 .500 REF .013 .021 SEATING PLANE TOP VIEW SIDE VIEW .165 .180 .090 .120 .009 .015 PL 044

Am79C30A/32A Data Sheet 99 PHYSICAL DIMENSIONS Note: Dimensions are measured in inches. SIDE VIEW PQT 44 9.80 10.20 11.80 12.20 9.80 10.20 11.80 12.20 -A- -D- -B- TOP VIEW 0.95 1.05 1.00 REF . 0.30 0.45

0.80 BSC

11° – 13°

1.20 MAX

11° – 13°

100 Am79C30A/32A Data Sheet

© 1998 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any warranty of merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or systems without AMD’s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of AMD products, except as provided in AMD’s Terms and Conditions of Sale for such products. Trademarks AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. AmMAP , Digital Subscriber Controller, DSC, and IDC are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

steps of 2 dB with a tolerance of approximately 0.5 dB.