AM79C100 AMD | Alldatasheet
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Publication# 16511 R ev: B Amendment/0 Issue Date: M ay 1994 1 Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX Plus) DISTINCTIVE CHAR ACTERISTICS n CMOS d evice provides IEEE 802.3-compliant operation and low operating current from a single +5 V supply n Power Down mode for reduced power consumption in battery-powered applications n Automatic twisted-pair link integrity n Pin-selectable twisted-pair receive polarity detection and automatic inversion of the receive signal. Polarity indication output pin can directly drive an LED. n Pin-selectable twisted-pair link integrity test capability conforming to the IEEE 802.3 standard. Link status pin can directly drive an LED. n Transmit, receive, and collision status indications available on separate, dedicated pins n Outputs can directly drive LEDs with pulses stretched to ensure LED visibility n Internal twisted-pair transmitter digital predistortion circuit to reduce medium-induced jitter n Pin-selectable SQE Test (heartbeat) enable n AUI loopback, Jabber Control, and SQE Test functions comply with the 10BASE-T standard n Use r-selectable loopback operations n Pin-selectable twisted-pair receive threshold programming for extended distance line lengths GENERAL DESCRIPTION The Am79C10 0 Twisted-Pair Ethernet Transceiver Plus (TPEX Plus) is an integrated circuit that implements the medium attachment unit (MAU) functions for the twisted-pair medium, as specified by the supplement to the IEEE 802.3 standard (Type 10BASE-T). This de- vice provides the necessary electrical and functional interface between the IEEE 802.3 standard attachment unit interface (AUI) and the twisted-pair cable. A network based on the 10BASE-T standard can use unshielded twisted-pair cables, providing an economi- cal solution to netw orking by allowing the use of existing telephone wiring. The Am79C100 provides a minimal component count and a cost-effective solution to the design and implementation of 10BASE-T standard networks. TPEX Plus provides twisted-pair driver and receiver cir- cuits, including on-board transmit digital predistortion, receiver squelch, and an AUI port with pin-selectable SQ E Test enable. The device provides a number of ad- ditional features, including Link Status indication with automatic twisted-pair receive polarity detection/ correction and indication; pin-selectable receive threshold programming for extended distance line lengths; and Receive Carrier Sense, Transmit Active and Collision Present indications. The device provides separate twisted-pair Link Status, Polarity Status, Receive, Transmit, and Collision outputs to drive LEDs directly.
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CI– DI+ DI– PRDN/RST REXT TEST 1 TEST2 TXD+ TXD– TXP+ TXP– RXD+ RXD– DO+ DO– XMT COL RCV LNKST SQE TEST RXPOL LRT Line Receiver and Squelch Circuit Attachment Unit Interface (AUI) Twisted-Pair Interface RELATED AMD PRODUCTS Part No. Description Am7996 IEEE-802.3/Ethernet/Cheapernet Tap Transceiver Am79C90 CMOS Local Area Network Controller for EthernetTM (C-LANCE) Am79C900 Integrated Local Area Communications ControllerTM (ILACCTM ) Am79C940 Media Access Controller for Ethernet (MACETM ) Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) Am79C961 PCnet-ISA Single-Chip Ethernet Controller (with MicrosoftÒ Plug n’ Play support) Am79C965 PCnet-32 Single-Chip Ethernet Controller (for 386DX, 486 and VL buses) Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) Am79C981 Integrated Multiport Repeater PlusTM (IMR+TM ) Am79C987 Hardware Implemented Management Information BaseTM (HIMIBTM )
TXP– TEST2 SQE TEST LRT PRDN/RST DV DD TEST1 AV DD DO– REXT RCV RXPOL RXD– RXD+ DI+ DI– CI– CI+ TXD+ TXD– TXP+ 16511B-2 16511B-3 DO+ DO– DI+ DI– CI+ CI– SQE TEST TEST1 TEST2 REXT PRDN/RST TXD+ TXP+ TXD– TXP– RXD+ RXD– LRT RXPOL LNKST XMT RCV COL Am79C100 DVDD AVDD DVSS AVSS Attachment Unit Interface (AUI) Twisted-Pair Interface
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AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. Valid Combinations Valid combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM79C100 J C DEVICE NUMBER/DESCRIPTION Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX Plus) OPTIONAL P R OCESSING Blank = Standard Processing OPER ATING CONDITIONS C = Commercial (0°C to +70°C) PACK AG E TYPE J = 28-Pin Plastic Leaded Chip Carrier (PL 028) SPEED Not Applicable Valid Combinations AM79C100 JC
This pin supplies +5 V to analog portions of the TPEX Plus circuitry. AV SS Analog Ground This pin is the ground reference for analog portions of TPEX Plus circuitry. CI+, CI– Control In Output AUI port differential driver. COL Collision Output, Open Drain This pin is driven LO W while the TPEX Plus is simulta- neously receiving data on the AUI DO pins and the twisted-pair RXD pins, indicating that a collision condi- tion exists. It is also driven if TPEX Plus enters the jab- ber condition due to excessive length of activity on the DO pair. In this case TPEX Plus will w ait for a period of inactivity on DO for the “unjab” time of 250 to 750 ms, before the 10 MHz pattern on the CI pair is removed and COL returns inactive. COL will not be driven during SQ E Test activity on the AUI CI pair. In the LO W output state, the pin is capable of sinking a maxim um of 12 mA and can be used to drive an LED. The COL output is pulse stretched for 20 to 62 ms after the end of colli- sion, to ensure LED visibility. DI+, DI– Data In Output AUI port differential driver. DO+ , DO– Data Out Input AUI port differential receiver. DV DD Digital Power This pin supplies +5 V to digital portions of the TPEX Plus circuitry, including all transmit drivers. DV SS Digital Ground Tw o pins provide the ground reference for digital por- tions of TPEX Plus circuitry, including all transmit drivers and the status indication LED drivers. LNKST Link Status Input/Output, Open Drain When this pin is tied LOW, the internal Link Test Re- ceive function is disabled, and the Transmit and Receive functions will remain active regardless of arriv- ing idle link pulses and data. TPEX Plus continues to generate idle link pulses irrespective of the status of this pin. As an output, this pin is driven LOW if the link is identi- fied as functional. However, if the link is determined to be nonfunctional due to missing idle link pulses or data packets, then this pin is not driven (internally pulled HIGH). In the LOW output state, the pin is capable of sinking a maximum of 12 mA and can be used to drive an LED. In the absence of an external drive, the pin is internally pulled HIGH when inactive. LR T Low Receive Threshold Input, Active LO W When this pin is tied LO W , the internal twisted-pair re- ceive thresholds are reduced by 4.5 dB from their orig- inal values (approximately 3/5 of the normal 10BASE-T value). With LR T in the HIGH state, the unsquelch threshold for the RXD circuit will be 300 mV to 520 mV peak . With LR T in the LO W state, the unsquelch threshold for the RXD circuit will be 180 mV to 312 mV peak. In either case, the RXD circuit post unsquelch threshold will be approximately one-half of the initial unsquelch threshold. PRDN/RST Power Down/Reset Input, Active LO W D riving this input LO W resets the internal logic of TPEX Plus and places the device in a special Pow er Down mod e. In the Power Down/Reset mode, all output driv- ers are placed in their inactive state. REXT External Resistor Input An external precision resistor is connected betw een this pin and AV DD in order to provide a current refer- ence for the internal voltage-controlled oscillator (VCO). RCV Receive Output, Open Drain This pin is driven LO W while TPEX Plus is receiving data on the twisted-pair RXD pins and is transferring the received signal onto the AUI DI pair. The output is LO W during collision sim ultaneously with the COL pin.
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In the LO W output state, the pin is capable of sinking a maxim um of 12 mA and can be used to drive an LED. The RCV output is pulse stretched for 20 ms to 62 ms after the end of reception, to ensure LED visibility. RXD+ , RXD– Receive Data Input 10BASE-T port differential receiver. RXPOL Receive Polarity Input/Output, Open Drain The twisted-pair receiver is capable of detecting a re- ceive signal with reversed polarity (wiring error). The RXPOL pin is normally in the LO W state, indicating cor- rect polarity of the received signal. If the receiver de- tects a received packet with reversed polarity, then this pin is not driven (goes HIGH) and the polarity of subse- quent packets is inverted. In the LO W output state, this pin can sink up to a maximum of 12 mA and is therefore capable of driving an LED. This feature can be disabled by strapping this pin LO W . In this case, the Receive Polarity correction circuit is disabled and the internal Receive Signal remains non- inverted, irrespective of the received signal. In the absence of an external drive, the pin is internally pulled HIGH when inactive. SQE TEST Signal Quality Test (Heartbeat) Enable Input, Active LO W The SQ E Test function is enabled by tying this input LO W . When ena bled, TPEX Plus will send a 10 MHz burst (heartbeat) on the CI lines after DO has be- come inactive, indicating integrity of the collision detec- tion and AUI circuitry. SQE TEST should be disabled for repeater applications. In the absence of an external drive, the pin is internally pulled HIGH when inactive. TEST1 Test Input, Active HIGH This pin should be tied LO W for normal operation. TEST1 permits system-level diagnostics to be per- formed . If TEST1 is driven HIGH (while TEST2 is main- tained HIGH), TPEX Plus will enter the Loopback Test mod e. The type of loopback is determined by the state of the SQE TEST pin. If SQE TEST is in the LO W state (Station MAU), TPEX Plus transfers data indepen- dently from DO to the TXD/TXP circuits and from RXD to the DI circuit. If the SQE TEST is in the HIGH state (Repeater MAU), then data on the RXD circuit is trans- mitted back onto the TXD/TXP circuits and data on the DO circuit is transmitted onto the DI pair. During either test mode, the Collision Detection and SQ E Test functions are disabled, and CI will remain idle. Link beat pulses will continue to be generated nor- mally in the absence of TXD/TXP output activity, and the Link Test Receive State Machine will be forced into the Link Pass state. The COL pin will be driven LO W when ever a link beat pulse or transmit data activity commence s, and remain low during the output activity. The receive squelch will continue to operate on both the RXD and DO input circuits. In the absence of an external drive, the pin is internally pulled LO W . TEST2 Test Input, Active LO W This pin should be tied HIGH for normal operation. TEST2 is reserved for factory testing, and should be permanently tied HIGH. In the absence of an external drive, the pin is internally pulled HIGH. TXD+ , TXD– Transmit Data Output 10BASE-T port differential drivers. TXP+ , TXP– Transmit Predistortion Output Transmit w aveform differential driver for predistortion. XMT Transmit Output, Open Drain This pin is driven LO W while TPEX Plus is receiving data on the AUI DO pair and is transmitting data on the TXD/TXP pins. The output is LO W du ring collision si- m ultaneously with the COL pin. In the LO W output state, the pin is capable of sinking a maxim um of 12 mA and can be used to drive an LED. The XMT output is pulse stretched for 20 to 62 ms after the end of trans- mission, to ensure LED visibility.
The Twisted-Pair Ethernet Transceiver Plus (TPEX Plus) complies with the requirements specified by the IEEE 802.3 standard for the attachment unit interface (AUI) and the 10BASE-T standard for a twisted-pair medium attachment unit (MAU). TPEX Plus also imple- ments a number of features in addition to the IEEE 802.3 standard. An outline of the functions of the Am79C100 is given below. Attachment Unit Interface (DO , DI , CI The AUI electrical and functional characteristics com- ply with those specified within the IEEE 802.3 docu- ments, Sections 7 and 14. The AUI pins can be wired to an isolation transforme r, for a remote MAU applica- tion, or directly to another device (e.g., Am7992B serial interface adapter), in the case of a local DTE applica- tion. The end-of-packet SQE Test function (heartbeat) can be disabled to allow the device to be employed in a repeater application. Twisted-Pair Transmit Function Data transmission to the 10BASE-T medium occurs when valid AUI signals appear on the DO differential pair. This data stream is routed to the differential driver circuitry in the TXD and TXP pins. The driver circuitry provides the necessary electrical driving capability and the predistortion control for transmitting signals over maxim um length twisted-pair cable, as specified by the IEEE 802.3 10BASE-T standard. During transmission, data is looped back to the DI differential circuit, indi- cating normal operation. The transmit function for data output and loopback operations meets the propagation delays and jitter specified by the standard. During nor- mal transmission, and providing that TPEX Plus is not in a Link Fail or Jabber state, the XMT pin will be driven LO W , and can be used to drive a status LED directly. Twisted-Pair Receive Function The receiver complies with the receiver specifications of the IEEE 802.3 10BASE-T standard, including noise imm unity and received signal rejection criteria (“Smart Squelch”). Signals meeting these criteria appearing at the RXD differential input pair are routed to the DI outputs. The receiver function meets the propagation delays and jitter requirements specified by the stan- dard. The receiver squelch level drops to approximately half its threshold value after unsquelch to allow recep- tion of minimum amplitude signals and to mitigate car- rier fade in the event of w orst-case signal attenuation and crosstalk noise conditions. During receive, the RCV pin is driven LO W and can be used to drive a sta- tus LED directly. Note that the 10BASE-T standard defines the receive input amplitude at the external media-dependent inter- face (MDI). Filter and transformer loss are not speci- fied. The TPEX Plus receiver squelch levels are defined to account for a 1 dB insertion loss at 10 MHz, which is typical for the type of receive filters/transformers rec- ommended (see also Table 1). No rmal 10BASE-T-compatible receive thresholds are employed when the LR T pin is inactive (HIGH). When the LRT pin is externally pulled LO W , the Low Receive Threshold option is invoked, and the sensitivity of the TPEX Plus receiver is increased. This allows longer line lengths to be employed, exceeding the 100 m tar- get distance of normal 10BASE-T (assuming typical 24 AWG ca ble). The additional cable distance contributes directly to increased signal attenuation and reduced signal amplitude at the TPEX Plus receiver. How ever, from a system perspective, making the receiver more sensitive means that it is also more susceptible to extraneous noise, primarily caused by coupling from co-resident services (crosstalk). For this reason, it is recommended that when using the Low Receive Threshold option, the service should be installed on 4-pair cable only. Multipair cables within the same outer sheath have lower crosstalk attenuation, may allow noise emitted from adjacent pairs to couple into the re- ceive pair, and be of sufficient amplitude to falsely un- squelch the TPEX Plus. Link Test Function The Link Test function is implemented as specified by the 10BASE -T standard. During periods of transmit pair inactivity, “link beat” pulses will be sent periodically over the twisted-pair medium to allow constant monitor- ing of medium integrity. When the Link Test function is enabled, the absence of link beat pulses and receive data on the RXD pair will cause the TPEX Plus to go into a Link Fail state. In the Link Fail state, data transmission, data reception, data loopback, and collision detection functions are disabled and remain disabled until valid data or >5 consecutive link pulses appear on the RXD pair. During Link Fail, the LNKST pin is internally pulled HIGH. When the link is identified as functional, the LNKST pin is driven LO W , and is capable of directly driving a “Link OK” LED. In order to interoperate with systems that do not implement Link Test, this function can be disabled by grounding the LNKST pin. With Link Test disabled, the data driver, receiver, and loopback functions, as w ell as collision detection, remain enabled irrespective of the presence or absence of data or link pulses on the RXD pair. Polarity Detection and Reversal The TPEX Plus receive function includes the ability to invert the polarity of the signals appearing at the RXD pair if the polarity of the received signal is reversed (such as in the case of a wiring error). This feature al- lows data packets received from a reverse-wired RXD input pair to be corrected in the TPEX Plus prior to transfer to the DTE via the AUI interface (DI ). The
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polarity detection function is activated following reset or Link Fail, and will reverse the receive polarity based on both the polarity of any previous link beat pulses and the polarity of subsequent packets with a valid end transmit delimiter (ETD). When in the Link Fail state, TPEX Plus will recognize link beat pulses of either positive or negative polarity. Exit from the Link Fail state is caused by the reception of 5 to 6 consecutive link beat pulses of identical polar- ity. On entry to the Link Pass state, the polarity of the last 5 link beat pulses is used to determine the initial re- ceive polarity configuration and the receiver is reconfig- ured to subsequently recognize only link beat pulses of the previously recognized polarity. This link pulse algo- rithm is employed only until SFD polarity determination is made, as described later in this section. Positive link beat pulses are defined as received signal with a positive amplitude greater than 520 mV (LRT = HIGH) with a pulse width of 60 ns to 200 ns. This posi- tive excursion may be followed by a negative excursion. This definition is consistent with the expected received signal at a correctly wired receiver, when a link beat pulse that fits the template of Figure 14-12 in the 10BASE- T standard is generated at a transmitter and passed through 100 m of twisted-pair cable. Negative link beat pulses are defined as received sig- nals with a negative amplitude greater than 520 mV (LR T = HIGH) with a pulse width of 60 ns to 200 ns. This negative excursion may be followed by a positive excursion. This definition is consistent with the ex- pected received signal at a reverse-wired receiver, when a link beat pulse that fits the template of Figure 14-12 in the 10BASE-T standard is generated at a transmitter and passed through 100 m of twisted-pair cable. The polarity detection/correction algorithm will remain “armed ” until tw o consecutive packets with valid ETD of identical polarity are detected. Whe n “armed ,” the re- ceiver is capable of changing the initial or previous po- larity configuration based on the most recent ETD polarity. On receipt of the first packet with valid ETD following reset or Link Fail, TPEX Plus will utilize the inferred po- larity information to configure its RXD input, regard- less of its previous state. On receipt of a second packet with a valid ETD with correct polarity, the detection/cor- rection algorithm will “lock in” the received polarity. If the second (or subsequent) packet is not detected as confirming the previous polarity decision, the most re- cently detected ETD polarity will be used as the default. Note that packets with invalid ETD have no effect on updating the previous polarity decision. Once two con- secutive packets with valid ETD have been received, TPEX Plus will disable the detection/correction algorithm until either a Link Fail condition occurs or PRDN/RST is asserted. During polarity reversal, the RXPOL pin is internally pulled HIGH. During normal polarity conditions, the RXPOL pin is driven LO W , and is capable of directly driving a “Polarity OK” LED using an integrated 12 mA driver. If desired, the Polarity Reversal function can be disabled by grounding the RXPOL pin. Twisted-Pair Interface Status Three outputs (XMT, RCV, and COL) indicate whether the TPEX Plus is transmitting (AUI to twisted-pair), re- ceiving (twisted-pair to AUI), or in a collision state with both functions active sim ultaneously. The TPEX Plus will power up in the Link Fail state. The normal algorithm will apply to allow it to enter the Link Pass state. On power up, the XMT, RCV, and COL LED drivers activate for 20 ms to 62 ms as a lamp test fea- ture, and will then go to their inactive state until TPEX Plus enters the Link Pass state. In the Link Pass state, transmit or receive activity that passes the pulse-width/amplitude requirements of the DO – or RXD– inputs will be indicated by the XMT or RCV pin, respectively, going active. XM T, RCV, and COL are all asserted during a collision. In the Link Fail state, XMT , RCV, and COL are disabled. In Jabber Detect mode, TPEX Plus will activate the COL driver, disable the XMT driver (regardless of DO– activity), and allow the RCV driver to indicate the cur- rent state of the RXD– pair. If there is no receive activity on RXD–, only COL will be active during Jabber Detect. If there is RXD – activity, both COL and RCV will be active. All three outputs are active LO W and incorporate 12 mA d rive capability with 20 ms to 62 ms pulse stretch circuitry, to extend the event to ensure LED visibility. Collision Detect Function Sim ultaneous Carrier Sense (presence of valid data signals) by both the AUI DO– pins and the twisted-pair RX D – pins constitutes a collision, thereby causing a
10 MHz signal to be asserted on the CI– output pair,
and the COL output to be activated. The CI– output meets the drive requirements for the AUI interface. This
10 MHz signal will remain on the CI– pair until one of
the tw o colliding states changes from active to idle. During the collision condition, data presented on the DI– pair will be sourced from the RXD– input. At the end of collision, the data presented on the DI– pair will be sourced from the last remaining active input, either RXD – or DO–. The CI– output pair stays HIGH for 2 bit times at the end of a collision, decreasing to the idle level within 80 bit times after the last transition. The XMT , RCV, and COL pins are driven LO W du ring collision.
Signal Quality Error (SQE) Test (Heartbeat) Function When the SQE TEST pin is driven LO W , TPEX Plus will routinely exercise the collision detection circuitry by generating an SQE Test message at the end of every transmission. This signal is a self-test indication to the DTE that the MAU collision circuitry is functional and the AUI cable/connection is intact. An SQE Test mes- sage consists of a 10 MHz signal on the CI– pair with a duration of 5 to 15 bit times (500 ns to 1500 ns). When enabled, an SQE Test will occur at the end of every transmission, starting 6 to 16 bit times (600 ns to 1600 ns) after the last transition of the transmitted sig- nal. For repeater applications, the SQE Test function can be disabled by tying the SQE TEST pin HIGH or by leaving it disconnected. The COL output will remain in- active during the SQE Test message on CI–. Jabber Function The Jabber function inhibits the twisted-pair transmit function of TPEX Plus if the DO– circuit is active for an excessive period (20 ms to 150 ms). This prevents any one node from disrupting the network due to a “stuck on” or faulty transmitter. If this maxim um trans- mit time is exceeded, the TPEX Plus transmitter cir- cuitry is disabled and a 10 MHz signal is driven onto the C I– pair. Once the transmit data stream is removed from the DO– input pair, an “unjab” time of 250 ms to 750 ms will elapse before the TPEX Plus removes the
10 MHz signal from the CI– pair and re-enables the
transmit circuitry. When jabber is detected, TPEX Plus will activate the COL driver, disable the XMT driver (regardless of DO– activity), and allow the RCV driver to indicate the current state of the RXD– pair. If there is no receive ac- tivity on RXD–, only COL will be active during Jabber Detect. If there is RXD– activity, both COL and RCV will be active. Power Down In addition to on-board power-on-reset circuitry, the PRDN/RST pin is used as the master reset for TPEX Plus. PRDN/RST m ust be driven LO W for a minimum of 2 ms for reset to occur. The PRDN/RST pin can also be used to put the TPEX Plus into an inactive or “sleep” state, causing the device to consume less powe r. This feature is useful in battery-powered or low-duty-cycle systems. Driving PRDN/RST LO W resets the internal logic of TPEX Plus and places the device into idle mod e. In this mode, the twisted-pair driver pins (TXD–, TX P–) are driven LO W , the AUI pins (CI–, DI–) are pulled to AVDD , the LNKST and RXPOL pins are in the inactive state, and the XMT, RCV, and COL pins are in the high-impedance state. TPEX Plus will remain in idle mode as long as PRDN/RST is asserted. Following the rising edge of the signal on PRDN/RST, TPEX Plus will remain in the reset state for up to 10 ms. Immediately after the reset condition is removed, TPEX Plus will drive the XMT, RCV, and COL outputs LO W for 20 ms to 62 ms as a lamp test feature, and will be forced into the Link Fail state. TPEX Plus will move to the Link Pass state only after 5 to 6 link beat pulses and/or a single received message is detected on the RXD – pair. Test Modes TPEX Plus implements tw o types of loopback test modes suitable for Station (DTE) or Repeater applica- tions. The test mode is entered by driving the TEST1 pin HIGH. The TEST2 pin is intended for factory test only and should be tied HIGH for test mode or normal operation. The tw o available test modes are: 1. Station (DTE): SQE TEST pin LO W . Data received on the DO– input pair is transmitted onto the TXD – and TXP– output pairs, and data received on the RXD – input pair is transmitted onto the DI– output pair. 2. Repeater: SQE TEST pin HIGH. Data received on the DO– input pair is looped back onto the DI– out- put pair, and data received on the RXD– pair is looped back and retransmitted on the twisted-pair drivers (TXD– and TXP – pairs). In both modes, TPEX Plus will be forced into the Link Pass state and will not enter the Link Fail state, regard- less of RXD– inactivity. The following functions are dis- abled: jabber circuit, collision detection, and collision oscillator. The functions that remain enabled are: the DO – and RXD– squelch circuits, XMT and RCV out- puts, link beat pulse generation, and polarity detection/ correction. In addition, in both modes, the COL pin (not used to indicate collision during test modes) will go ac- tive for the duration of any transmit activity on the TXD –/TXP– pairs, providing a leading high-to-low edge indicating the start of packet transmission or link beat pulse generation. Upon exiting either of the test modes, the Link Test State Machine will be forced into the Link Fail state. RXPOL m ay be pulled LO W and receive polarity correction will be disabled. TPEX Plus External Components Figure 1 shows a typical twisted-pair port external com- ponents schematic. The resistors used should have a –1% tole rance to ensure interoperability with 10BASE -T-compliant networks. The filters and pulse transformers are necessary devices that have a major influence on the performance and compliance of a TPEX Plus-based MAU . Specifically, the transmitted w aveforms are heavily influenced by filter characteris- tics and the twisted-pair receivers employ several
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when and if to assert the internal carrier sense. tolerances of the external components be as specified. and the pulse transformers into one package. Electronics, and Nano Pulse. Figure 1. Typical Twisted-Pair Port External Components
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- During Loopback, the COL pin does not indicate collision, but instead provides indication of
Figure 3. Am79C100 TPEX Plus Loopback Operation
- Compatible filter modules, with a brief description of package type
and features are included in Table 1 of this section.
- The resistor values are recommended for general purpose use, and should
affected by the transmit filter configuration.
- Compatible AUI transformer modules, with a brief description of package type
and features are included in Table 2 of this section. Figure 4. Am79C100 Stand Alone MAU System Application
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Table 1. TPEX Plus Compatible Media Interface Modules Table 2. Am79C100 TPEX Plus Compatible AUI Transformers
Ambient Temperature Under Bias: 0°C to +70°C. . . . Supply Voltage to AVSS or DVSS Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maxi- mum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Temperature (T All inputs within the range: AV SS –0.5 V £ VIN £ AVDD + 0.5 V, or DV SS –0.5 V£ VIN £ DVDD +0.5 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit Digital Input Voltage VIL Input LOW Voltage 0.8 V VIH Input HIGH Voltage 2.0 V Digital Output Voltage VOL Output LOW Voltage IOL = 12 mA (Open Drain) 0.4 V (XMT, RCV, COL, LNKST and RXPOL) Digital Input Leakage Current IILL Input Leakage Current DV SS < VIN < DVDD 10 mA (PRDN/RST) IILD Input Leakage Current DV SS < VIN < DVDD 500 mA (LNKST/RXPOL, output inactive) Digital Output Leakage Current I OLD Output Leakage Current DV SS < VIN < DVDD 10 mA (XMT, RCV, COL) AUI IIAXD Input Current at DO+, DO– AV SS < Vin < AVDD –500 500 mA VAICM DO – Open Circuit Input IIN = 0 V AV DD –3.0 AV DD –1.0 V Common Mode Voltage (Bias) VAIDV Differential Mode Input AvDD = +5 V –2.5 +2.5 V Voltage Range (DO–) VASQ DO – Squelch Threshold –160 –275 mV VATH DO – Switching Threshold (Note 1) –35 +35 mV VAOD Differential Output Voltage R L = 78 W 620 1100 mV VAODI DI– & CI– R L = 78 W –25 +25 mV Differential Output (Note 1) Voltage Imbalance VAOD OFF DI– & CI– R L = 78 W –40 +40 mV Differential Idle Output Voltage IAOD OFF DI– & CI– R L = 78 W –1 1 mA Differential Idle Output Current (Note 1) VAOCM DI– & CI– Common R L = 78 W 2.5 AV DD V Mode Output Voltage
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DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description Test Conditions Min Max Unit Twisted Pair Interface IIRXD Input Current at RXD– AV SS < VIN < AVDD –500 500 uA R RXD RXD – Differential Input (Note 1) 10 KW Resistance VTIVB RXD+, RXD– Open Circuit IIN = 0 mA AvDD –3.0 AvDD –1.5 V Input Voltage (Bias) VTIDV Differential Mode Input AV DD = +5 V –3.1 3.1 V Voltage Range (RXD–) VTSQ+ RXD Positive Sinusoid 300 520 mV Squelch Threshold (Peak) 5 MH z < f < 10 MHz VTSQ– RXD Negative Sinusoid –520 –300 mV Squelch Threshold (Peak) 5 MH z < f < 10 MHz VTHS+ RXD Post-Squelch Positive Sinusoid 150 293 mV Threshold (Peak) 5 MH z < f < 10 MHz VTHS– RXD Post-Squelch Negative Sinusoid –293 –150 mV Threshold (Peak) 5 MH z < f < 10 MHz VLTSQ+ RXD Positive LRT = LOW 180 312 mV Squelch Threshold (Peak) VLTSQ– RXD Negative LRT = LOW –312 –180 mV Squelch Threshold (Peak) VLTHS+ RXD Post-Squelch Positive LRT = LOW 90 175 mV Threshold (Peak) VLTHS– RXD Post-Squelch Negative LRT = LOW –175 –90 mV Threshold (Peak) VRXDTH RXD Switching Threshold (Note 1) –60 60 mV VTXH TXD – and TXP– DV SS = 0 V DV DD –0.6 DV DD V Output HIGH Voltage (Note 2) VTXL TXD – and TXP– DV SS = +5 V DV SS DV SS + 0.6 V Output LOW Voltage (Note 2) VTXI TXD – and TXP– Differential –40 40 mV Output Voltage Imbalance VTXOFF TXD – and TXP– DV DD = +5 V –40 40 mV Idle Output Voltage R TX TXD – and TXP– Differential (Note 1) 40 W Driver Output Impedance IIREXT Input Current at REXT Pin R EXT = 24.3 kW –1% 120 mA AV DD = +5 V Power Supply Current IDD Power Supply Current PRDN/RST = HIGH 40 mA (Idle) DV DD = AVDD = +5 V Power Supply Current PRDN/RST = LOW 95 mA (Transmitting—No TP load) Power Supply Current PRDN/RST = HIGH 150 mA (Transmitting—with TP load) DV D D = AVDD = +5 V IDDPRDN Power Supply Current PRDN/RST = LOW 4 mA in Power Down Mode Notes: 1. Parameter not tested. 2. Uses switching test load.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Parameter Symbol Parameter Description Min Max Unit Transmit Timing tPWODO DO Pulse Width Accept/ VDO > |VASQ max| 15 35 ns Reject Threshold (Note 3) tPWKDO DO Pulse Width Maintain/ VDO > |VASQ max| 105 200 ns Turn-Off Threshold (Note 4) tTON Transmit Start Up Delay 300 ns tTSD Transmit Static Propagation 120 ns Delay (DO– to TXD–) tTETD Transmit End Transmit Delimiter 250 450 ns tTR Transmitter Rise Time 10 ns (10% to 90%) tTF Transmitter Fall Time 10 ns (90% to 10%) tTM Transmitter Rise and Fall 4 ns Time Mismatch tTHD D O › to TXD+ › Steady State tTSD – 1.0 tTSD + 1.0 ns and TXD– fl Delay (Note 1) tTLD DO fl to TXD+ fl Steady State tTSD – 1.0 tTSD + 1.0 ns and TXD– › Delay (Note 1) tTHDP DO › to TXP+ fl Steady State tTSD + 40 tTSD + 60 ns and TXP– › Delay (Note 1) tTLDP DO fl to TXP+ › Steady State tTSD + 40 tTSD + 60 ns and TXP– fl Delay (Note 1) tXMTON XMT Asserted Delay 100 ns tXMTOFF XMT De-asserted Delay 20 62 ms tPERLP Idle Signal Period 8 24 ms tPWLP Link Beat Pulse Width (Note 1) 75 120 ns tPWPLP Predistortion Idle Link (Note 1) 40 60 ns Beat Width tJA Transmit Jabber 20 150 ms Activation Time tJR Transmit Jabber 250 750 ms Reset Time tJREC Transmit Jabber (Note 1) 1.0 – ms Recovery Time (Minimum time gap between transmitted packets to prevent jabber activation) t DODION DO to DI Startup Delay 300 ns tDODISD DO to DI Static Propagation 100 ns Delay Test Conditions
18 Am79C100
SWITCHING CHARACTERISTICS (Continued) Parameter Symbol Parameter Description Min Max Unit Receive Timing tPWKRD RXD Pulse Width Maintain/ VIN >VTHS min 136 200 ns Turn-Off Threshold (Note 5) tRON Receiver Start Up Delay Tested with 5 MHz 200 400 ns (RXD to DI–) Sinusoid tRVB First Validly Timed Bit tRO N + 100 ns on DI– tRSD Receiver Static Propagation 70 ns Dela y (RXD – to DI–) tRETD DI End of Transmission 200 ns tRHD RXD – › to DI+ › (Not e 1) tRSD – 2.5 tRSD + 2.5 ns and DI– fl Delay tRLD RXD – fl to DI+ fl (Not e 1) tRSD – 2.5 tRSD + 2.5 ns and DI– › Delay tRR DI+, DI–, CI+, CI– Rise Time 5 ns (10% to 90%) tRF DI+, DI–, CI+, CI– Fall Time 5 ns (10% to 90%) tRM DI– and CI– Rise and Fall 2 ns Time Mismatch (tRR – tRF ) tRCVON RCV Asserted Delay tRON – 50 tRON + 100 ns tRCVOFF RCV De-asserted Delay 20 62 ms Collision Detection and SQE Test tCON Collision Turn-On 500 ns Delay (CI–) tCOFF Collision Turn-Off 500 ns Delay (CI–) tPER Collision Period (CI–) 87 117 ns tCPW Collision Output Pulse Width 40 60 ns (CI–) tSQED SQE Test Delay Time 600 1600 ns tSQEL SQE Test Length 500 1500 ns tCOLON COL Asserted Delay tCON – 50 tCON + 100 ns tCOLOFF COL De-asserted Delay 20 62 ms Notes: 1. Parameter not tested. 2. Uses switching test load. 3. DO pulses narrower than tPWODO (min) will be rejected; pulses wider than tPWODO (max) will turn internal DO carrier sense on. 4. DO pulses narrower than tPWKDO (min) will maintain internal DO carrier sense on; pulses wider than tPWKDO (max) will turn internal DO carrier sense off. 5. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense on; pulses wider than tPWKRD (max) will turn internal RXD carrier sense off. Test Conditions
294 W100 pF
TXD– DV SS 294 W Test Point 16511B-8 DV DD TXP+
715 W100 pF
TXP– DV SS 715 W Includes test jig capacitance Test Point Includes test jig capacitance 16511B-9 Twisted Pair Transmit Test Circuit AV DD DI+ DI– CI+ CI–
154 W50 pF
52.3 W Test Point 16511B-10 AUI Transmit Test Circuit
20 Am79C100
KEY TO SWITCHING WAVEFORMS KS000010 Must be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS
Transmit Link Beat Pulse 16511B-12 DO± tPWKDO tXMTOFF TXP+ TXD- TXP- TXD+ TETDt VATH+ VATH- tTON tXMTON tTFtTR tPWODO tTHDP tTLDP VASQ(min) VASQ(max) XMT DI± tDODION tDODISD tPWKDO TXD+ TXP+ TXD- TXP- tPWLP tPERLP tPWPLP
22 Am79C100
RXD± RETDt tRCVOFF tRCVON tRFtRRtRON tRHD VTSQ– VTSQ+ DI– RCV tRF tRR tRLD tPWKRD tPWKRD 16511B-14 Receive Thresholds RXD± VTSQ– VTSQ+ VTHS– VTHS+ RXD± VLTSQ– VLTSQ+ VLTHS– VLTHS+
RXD± DO± CI+ CI– COL Collision Timing 16511B-16 COL = 1 DO± CI+ CI– tSQEL tSQED SQE Test Timing
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY , HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST , PCnet- FAST +, PCnet-Mobile, QFEX, QFEXr, QuASI QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc. Microsoft is a registered trademark of Microsoft Corporation. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.