AM79C03 AMD | Alldatasheet

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Publication# 09875 Rev: J Amendment: /0 Issue Date: December 1999 Am79C02/03/031(A) Dual Subscriber Line Audio Processing Circuit (DSLAC™ ) Devices DISTINCTIVE CHARACTERISTICS I Software programmable: — SLIC impedance — Transhybrid balance — Transmit and receive gains — Equalization — Digital I/O pins — Time Slot Assigner — PCM transmit clock edge options I Adaptive transhybrid balance filter (A suffix only) I A-law or µ-law coding I Dual PCM ports — Up to 8.192 MHz each (128 channels per port) I 2.048 MHz or 4.096 MHz master clock I Direct transformer drive I Built-in test modes I Low power CMOS I Mixed mode (analog and digital) impedance scaling I Performance characteristics guaranteed over 12 dB gain range GENERAL DESCRIPTION The Am79C02/03/031(A) Dual Subscriber Line Audio Processing Circuit (DSLAC device) integrates the key functions of an analog linecard into a single high-per- formance, programmable dual codec/filter device. The DSLAC device is based on the proven design of the reliable Am7901A Subscriber Line Audio Processing Circuit (SLAC ™ device). The advanced architecture of the DSLAC device implements two independent chan- nels and employs digital filters to allow software control of transmission, thus providing a cost effective solution for the analog to PCM function of a linecard. The Am79C02/03/031(A) DSLAC device’s advanced CMOS technology makes this an economical device that has both the functionality and the low power con- sumption needed in linecard designs to maximize line- card density at minimum cost. When used with two AMD SLICs, the DSLAC device provides software config- urable solutions to the BORSCHT function.

2 Am79C02/03/031(A) Data Sheet

4 Am79C02/03/031(A) Data Sheet

Channel 1 (CH 1) Signal Processing Channel 2 (CH 2) PCM Microprocessor Interface (MPI) Microprocessor DXA DRA DXB DRB FS PCLK Time Slot Assigner (TSA) SLIC Interface (SLI) 09875H-001 SLIC Analog VIN1 VOUT 1 VIN2 VOUT 2 TSCA TSCB RST C1 1 C2 1 C3 1 C4 1 C1 2 C2 2 C3 2 C4 2 C5 2 Highway DOUTDIN MCLK CHCLK (02 only) CS2CS1 (02 & 031 only) C5 1(02 & 031 only)

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Am79C02/03/031 J TEMPERATURE RANGE C=C o m m e r c i a l ( 0°C to 70°C; Relative Humidity=15% to 85%)* PACKAGE TYPE J =44-Pin Plastic Leaded Chip Carrier (PL 044) — Am79C02 32-Pin Plastic Leaded Chip Carrier (PL 032) — Am79C03 and 031 DEVICE NUMBER/DESCRIPTION Am79C02/03/031 Dual Subscriber Line Audio-Processing Circuit (DSLAC Device) Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on AMD’s standard military grade products. C Note: * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. Valid Combinations Am79C02 AJC, JCAm79C03 Am79C031 A DEVICE OPTIONS Blank = Standard Device A = Adaptive Transhybrid Balance

6 Am79C02/03/031(A) Data Sheet

18 19 20 21 22 23 24 25 26 27 28 654321 4 4 4 3 4 2 4 1 4 0 44-Pin PLCC C3 1 C2 1 C1 1 C4 1 CHCLK CS 1 CS 2 FS DRA VCCD 1 RST C3 2 C2 2 C1 2 C4 2 C5 2 MCLK DIN DCLK PCLK DGND 2 Am79C02 RSVD AGND 1 VIN1 VOUT 1 VCCA 2 VCCA 1 VEE 2 VOUT 2 VIN2 C5 1 DXB 32-Pin PLCC C3 1 C1 1 CS 1 C4 1 CS 2 FS VIN2 C2 2 C1 2 C4 2 MCLK DCLK PCLK DRB DGND TSCA DXB VCCD TSCB DRA Am79C03 AGND VEE 1 VCCA VOUT 1 VEE 2 VIN1 VOUT 2 C3 2 C2 1 CHCLK DIO21 DXA 32-Pin PLCC C3 1 C1 1 CHCLK C4 1 CS 1 CS 2 VIN2 C2 2 C1 2 C4 2 C5 2 MCLK DCLK DRA DGND TSCA DIO RSVD DXA FS Am79C031 AGND VEE 1 VCCA VOUT 1 VEE 2 VIN1 VOUT 2 C3 2 C2 1 C5 1 PCLK21 VCCD 09875H-00509875H-004 Notes: 1. Pin 1 is marked for orientation. 2. RSVD = Reserved pin; should not be connected externally to any signal or supply.

C1 1–C5 1, C1 2–C5 2 Inputs/Outputs Control. The five SLIC control lines per channel are TTL compatible and bidirectional. They can be used to monitor or control the operation of a SLIC or any other device associated with the subscriber line. Lines C11–C51 are associated with Channel 1, and lines C12–C52 are associated with Channel 2. The C51 and C52 lines are available on the Am79C02(A) and Am79C031(A). C51 and C52 are output only on the Am79C031(A) and must be programmed as outputs. CHCLK Output SLIC Clock. This output provides a 256 kHz or 293 kHz, 50% duty cycle, TTL compatible clock for use by two SLICs. The CHCLK frequency is derived from MCLK and the phase relationship to MCLK is random. CHCLK is capable of driving two TTL inputs. CS 2–CS 1 Input Chip Select. The Chip Select inputs (active Low) enable the device to read or write control data. CS 1 is for the Channel 1 microprocessor interface and CS2 is for the Channel 2 microproces- sor interface. DCLK Input Data Clock. The Data Clock input shifts data into and out of the microprocessor interface of the DSLAC device. The maximum clock rate is 4.096 MHz. DIN Input Data. Control data is serially written into the Am79C02(A) DSLAC device via the DIN pin with the most significant bit first. The Data Clock determines the data rate. DIN and DOUT may be strapped together to reduce the number of connections to the microprocessor. DIO Input/Output Data. Control data is serially written into and read out of the Am79C03(A) and Am79C031(A) DSLAC device via the DIO pin with the most significant bit first. The Data Clock determines the data rate. DIO is high impedance except when data is being transmitted from these DSLAC devices under control of CS 1 or CS2. DIO replaces DIN and DOUT as found on the Am79C02(A). DOUT Output Data. Control data is serially read out of the Am79C02(A) DSLAC device via the DOUT pin with the most significant bit first. The Data Clock determines the data rate. DOUT is high impedance except when data is being transmitted from the DSLAC device under control of CS 1 or CS2. DIN and DOUT may be strapped together to reduce the number of connections to the microprocessor. DRA, DRB Inputs PCM. The PCM data for Channels 1 and 2 is serially received on either the DRA or the DRB port during user programmed time slots. Eight bits are received with the most significant bit first. Data for each channel is received in 8-bit bursts every 125 µs at the PCLK rate. DXA, DXB Outputs PCM. The Transmit PCM data from Channels 1 and 2 is sent serially through either the DXA or DXB port during user programmed time slots. Eight bits are transmitted with the most significant bit first. The output is available every 125 µs and the data is shifted out in 8-bit bursts at the PCLK rate. DXA and DXB are high impedance between bursts and while the device is in the Inactive mode. DXB is not available on the 79C031(A). FS Input Frame Sync. The Frame Sync pulse is an 8 kHz signal that identifies the beginning of a system’s PCM frame. The DSLAC device references individual time slots with respect to this input, which must be synchronized to PCLK. MCLK Input Master Clock. The Master Clock must be a 2.048 MHz or 4.096 MHz clock input for use by the digital signal processor. PCLK Input PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz. RST Input Reset. A logic Low signal to this pin resets the DSLAC device to its default state. (Am79C02(A) only.) TSCA TSCB Outputs Time Slot Control. The Time Slot Control outputs are open drain (requiring pull-up resistors) and are normally inactive (high impedance). TSCA is active (Low) when PCM data is output on the DXA pin and TSCB is active (Low) when PCM data is output on the DXB pin. (TSCB is available on the Am79C02 and Am79C03 only.) VIN1, VIN2 Inputs Analog. The analog input is applied to the transmit path of the DSLAC device. The signal is sampled, digitally processed, and encoded for the PCM output. VIN1 is the input for Channel 1 and VIN2 is the input for Channel 2. VOUT 1, VOUT 2 Outputs Analog. The received PCM data is digitally processed and converted to an analog signal at the VOUT pin. VOUT1 is the output from Channel 1 and VOUT2 is the output for Channel 2. These outputs can directly drive a transformer SLIC.

8 Am79C02/03/031(A) Data Sheet

Power supply for the Am79C02: AGND 1 Analog Ground (Channel 1) AGND 2 Analog Ground (Channel 2) DGND 1 Digital Ground (Channel 1) DGND 2 Digital Ground (Channel 2) PGND PCM I/O Ground VCCA 1 +5 V Analog Power Supply (Channel 1) VCCA 2 +5 V Analog Power Supply (Channel 2) VCCD 1 +5 V Digital Power Supply Internally connected to substrate VCCD 2 +5 V Digital Power Supply Internally connected to substrate VCCP +5 V PCM I/O Power Supply Internally connected to substrate VEE 1 –5 V Power Supply (Channel 1) VEE 2 –5 V Power Supply (Channel 2) Power supply for the Am79C03 and Am79C031: AGND Analog Ground DGND Digital Ground VCCA +5 V Analog Power Supply VCCD +5 V Digital Power Supply Internally connected to substrate VEE 1 –5 V Power Supply (Channel 1) VEE 2 –5 V Power Supply (Channel 2) The many separate power supply inputs are intended to provide for good power supply decoupling techniques. Note that all of the +5 V inputs should be connected to the same source, all of the ground inputs should be con- nected to the same source, and both of the –5 V inputs should be connected to the same source. FUNCTIONAL DESCRIPTION The DSLAC device performs the codec/filter functions associated with the four-wire section of the subscriber line circuitry in a digital switch. These functions involve converting an analog voice signal into digital PCM sam- ples and converting digital PCM samples back into an analog signal. During conversion, digital filters are used to bandlimit the voice signals. Independent channels allow the DSLAC device to func- tion as two SLAC devices. All of the digital filtering is performed in digital signal processors operating from either a 2.048 MHz or 4.096 MHz external clock. The A/D, D/A, and signal processing is separate for each channel and each channel has its own Chip Select (CS1 and CS2) to allow separate programming. The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing func- tion, permit adjustment of the two-wire termination im- pedance, and provide equalization of the receive and transmit paths. All programmable digital filter coeffi- cients can be calculated using the AmSLAC2 software. The PCM codes can be either 8-bit companded A-law or µ-law. The PCM data is read and written to the PCM highway in user-programmable time slots at rates of 128 kHz to 8.192 MHz. The output hold time and the transmit clock edge can be selected for com- patibility with other devices that can be connected to the PCM highway. Four configurations of the DSLAC device are offered with the PCM interface described above. The Am79C02(A), the original version of the DSLAC device, is available in the 44-pin PLCC package. The Am79C03(A) and Am79C031(A) are reduced pin count versions obtained by consolidating a number of ground and power supply buses on chip, and eliminating the hardware reset function. The Am79C03(A) is available in 32-pin PLCC packages. The Am79C031(A) is avail- able in a 32-pin PLCC package. The “A” version of both devices (e.g., Am79C02A) offers the adaptive transhy- brid balance feature described in the Adaptive B Filter overview.

Ambient operating temperature . .–40°C ≤ TA ≤ +85°C (noncondensing) (VEE = –5 V) (VCCA = +5 V) Total combined C1–C5 current per channel: Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices VCCA 1, VCCA2, or VCCA VCCP , VCCD1, VCCD2, or VCCD Operating Ranges define those limits between which the functionality of the device is guaranteed. * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units.

10 Am79C02/03/031(A) Data Sheet

ELECTRICAL CHARACTERISTICS over operating range unless otherwise noted Typical values are for TA = 25°C and nominal supply voltages. Minimum and maximum specifications are over the temperature and supply voltage ranges shown in Operating Ranges. Notes: 1. When the DSLAC device is in the Inactive mode, the analog output presents a 0 V output level through a ~3 kΩ resistor. 2. The C1–C5 outputs are resistive for less than a 1 V drop. Total current must not exceed absolute maximum ratings. 3. If there is an external DC path from VOUT to VIN with a gain of GDC and the AISN has a gain of hAISN, then the output offset is multiplied by 1/[1 – (hAISN  GDC)]. 4. Power Dissipation in the Inactive mode is measured with all digital inputs at VIH = VCC and VIL = VSS and with no load connected to VOUT1 or VOUT2. Symbol Parameter Descriptions Min Typ Max Unit Note VIL Input Low voltage –0.5 0.8 V VIH Input High voltage 2.0 V CC IIL Input leakage current ±10 µA VOL Output Low voltage C1 –C5 (IOL = 6 mA) C1 –C5 (IOL = 15 mA) TSCA , TSCB (IOL = 14 mA) Other digital outputs (IOL = 2 mA) 0.4 1.0 0.4 0.4 V V OH Output High voltage C1 –C5 (IOH = 4 mA) C1 –C5 (IOH = 10 mA) Other digital outputs (IOH = 400 µA) VCC – 0.4 VCC – 1.0 2.4 IOL Output leakage current (HI-Z State) ±10 µA VIR Analog input voltage range (AX = 0 dB) (AX = 6.02 dB) ±3.12 ±1.56 V VIOS Offset voltage allowed on VIN ±160 mV IIL (VIL) Input leakage current on VIN ±10 µA ZIN Analog input impedance 300 Hz to 3400 Hz 5 M Ω ZOUT VOUT output impedance 1 10 Ω IOUT VOUT output current (f < 3400 Hz) ±6.3 mA 1 VOR VOUT voltage range (AR = 0 dB) (AR = 6.02 dB) ±3.12 ±1.56 V VOOS VOUT offset voltage (AISN off) ±40 mV VOOSA VOUT offset voltage (AISN on) ±80 3 LINAISN Linearity of AISN circuity (input = 0 dBm0) ± ¼ LSB PD Power dissipation Both channels active (MCLK, PCLK = 2.048 MHz) 1 channel active Both channels inactive 180 120 240 160 mW PD Power dissipation Both channels active (MCLK, PCLK > 2.048 MHz) 1 channel active Both channels inactive 190 130 270 175 ICC Total +5 V current Both channels active 1 channel active Both channels inactive 24.0 18.0 2.5 mA IEE Total –5 V current Both channels active 1 channel active Both channels inactive 10.0 5.0 0.05 C I Input capacitance (Digital) 15 pF C O Output capacitance (Digital) 15 PSRR Power supply rejection ratio (1.02 kHz, 100 mVrms, either supply or path, GX = GR = 0 dB) 40 dB

Transmission Characteristics The gain of the receive path is defined to be 0 dB when a 0 dBm0, 1014 Hz PCM sine wave input results in a nominal 1.55 Vrms for µ-law or 1.56 Vrms for A-law analog output. The gain of the transmit path is 0 dB when a 1.55 Vrms for µ-law or 1.56 Vrms for A-law, 1014 Hz sine wave analog input results in a level of 0 dBm0 at the digital output. When relative levels (dBm0) are used in any of the following transmission specifications, the specification holds for any setting of the AX + GX gain from 0 to 12 dB and the AR + GR loss from 0 to 12 dB. Performance specification for settings of the AX + GX gain from 12 to 18 dB and the AR + GR loss from 12 to 18 dB is determined as the device is characterized. Notes: 1. AMD guarantees less than 0.1% of units fall into the last 0.05 dB of these specification numbers. 2. See Figure 1. 3. With f swept between 0 to 300 Hz and 3400 to 12 kHz, any generated output signals other than f are less than –28 dBm0. This specification is valid for either transmission path. 4. AMD guarantees < 0.2% of units are above –46 dB. This relaxed specification applies to only the third harmonic. 5. Intermodulation distortion specification for two signals of same level in the range of –4 dBm0 to –21 dBm0 does not produce 2  (f1 – f2) component above specified level. 50 Hz IMD specified with 50 Hz signal at –23 dBm0 and signal between 300 Hz to 3400 Hz at –9 dBm0. 6. No single frequency component in the range above 3800 Hz may exceed a level of –55 dBm0. 7. The Group Delay specification is defined as the sum of the minimum values of the group delays for the transmit and the receive paths when the transmit and receive time slots are identical and the B, X, R, and Z filters are disabled. For PCLK frequencies between 1.03 MHz and 1.53 MHz, the group delay may vary from one cycle to the next. See Figure 2. Description Test Conditions Min Typ Max Unit Note Gain accuracy D to A or A to D 0 dBm0, 1014 Hz 25 °C to 85°C 0 dB < |path gain| < 6 dB 0 °C –40°C –0.20 –0.25 –0.35 +0.20 +0.25 +0.35 dB Gain accuracy D to A or A to D 0 dBm0, 1014 Hz 70 °C to 85°C 6 dB < |path gain| < 12 dB 25 °C 0°C –40°C –0.20 –0.25 –0.30 –0.35 +0.20 +0.25 +0.30 +0.35 Gain accuracy analog to analog or digital to digital 25°C to 85°C 0°C –40°C –0.20 –0.25 –0.35 +0.20 +0.25 +0.35 Attenuation distortion 300 Hz to 3400 Hz –0.125 +0.125 2 Single frequency distortion, A to D –46 3 Single frequency distortion, D to A–6 dB < (GR + AR) < 0 dB –40°C to 85°C –12 dB < (GR + AR) < –6 dB 70 °C to 85°C –12 dB < (GR + AR) < –6 dB 25 °C –12 dB < (GR + AR) < –6 dB 0 °C –12 dB < (GR + AR) < –6 dB –40°C –46 –46 –45 –43 –40 3, 4 3, 4 3, 4 Intermodulation distortion –42 –56 dBr 5 Analog out Idle channel noise Digital out digital looped back weighted unweighted digital input = 0 A-law µ-law analog V IN = 0 A-law µ-law –68 –55 –78 –68 dBm0p dBm0p dBm0p dBrnc0 dBm0p dBrnc0 Crosstalk TX to RX same channel RX to TX 0 dBm0 300 Hz to 3400 Hz –75 –75 TX to TX Crosstalk TX to RX between channels RX to TX RX to RX 0 dBm0 300 Hz to 3400 Hz –76 –78 –76 –78 Group delay PCLK ≥ 1.53 MHz PCLK ≤ 1.03 MHz B, X, R, and Z filters disabled 630 695 µs 7

12 Am79C02/03/031(A) Data Sheet

the group delay is taken as the reference. The signal level should be 0 dBm0. Figure 1. Attenuation Distortion (Single Ended)

420 DSLAC Device Specification

Figure 2. Group Delay Distortion

14 Am79C02/03/031(A) Data Sheet

signal with a level of A dBm0 also applied to the analog input. The minimum specifications are shown in Figure 5.

16.6 Hz < f < 45 Hz –25 dBm0 < A ≤ 0 dBm0 18 dB

45 Hz < f < 65 Hz –25 dBm0 < A ≤ 0 dBm0 25 dB

65 Hz < f < 100 Hz –25 dBm0 < A ≤ 0 dBm0 10 dB

3400 Hz < f < 4600 Hz –25 dBm0 < A ≤ 0 dBm0 see Figure 5

4600 Hz < f < 100 kHz –25 dBm0 < A ≤ 0 dBm0 32 dB

Figure 5. Discrimination against Out-of-Band Signals

the components are reduced by more than 70 dB. fective in reducing these tone levels. limits shown in the following table. Figure 6. Spurious Out-of-Band Signals

16 Am79C02/03/031(A) Data Sheet

Figure 7 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). PCM input; and (4) measurement analog-to-analog. Figure 7. A/A Overload Compression

SWITCHING CHARACTERISTICS over operating range unless otherwise noted Microprocessor Interface Min and max values are valid for all digital outputs with a 150 pF load, except C1–C5 with a 30 pF load. Pull-up resistors of 360 Ω are attached to TSCA and TSCB. PCM Interface PCLK not to exceed 4.096 MHz when PCM delay is used. No. Symbol Parameter Min Typ Max Units 1t DCY Data Clock Period 244 ns 2t DCH Data Clock High Pulse Width (Note 1) 97 3t DCL Data Clock Low Pulse Width (Note 1) 97 4t DCR Rise Time of Clock 25 5t DCF Fall Time of Clock 25 6t ICSS Chip Select Setup Time, Input Mode 70 t DCY – 10 7t ICSH Chip Select Hold Time, Input Mode 0 t DCH – 20 8t ICSL Chip Select Pulse Width, Input Mode 8t DCY 9t ICSO Chip Select Off Time, Input Mode (Note 7) 5 µs 10 t IDS Input Data Setup Time 30 ns 11 t IDH Input Data Hold Time 30 12 t OLH SLIC Output Latch Valid 20 1000 13 t OCSS Chip Select Setup Time, Output Mode 70 t DCY – 10 14 t OCSH Chip Select Hold Time, Output Mode 0 t DCH – 20 15 t OCSL Chip Select Pulse Width, Output Mode 8t DCY 16 t OCSO Chip Select Off Time, Output Mode (Note 7) 5 µs 17 t ODD Output Data Turn On Delay (Note 5) 50 ns 18 t ODH Output Data Hold Time 0 19 t ODOF Output Data Turn Off Delay 50 20 t ODC Output Data Valid 0 50 No. Symbol Parameter Min Typ Max Units 21 t PCY PCM Clock Period (Note 2) 0.122 7.8125 µs 22 t PCH PCM Clock High Pulse Width 48 3890 ns 23 t PCL PCM Clock Low Pulse Width 48 3890 24 t PCF Fall Time of Clock 15 25 t PCR Rise Time of Clock 15 26 t FSS FS Setup Time 25 t PCY – 50 27 t FSH FS Hold Time 50 28 t TSD Delay to TSC Valid (with Programmable Delay) (Note 3) 150 29 t TSO Delay to TSC Off (with Programmable Delay) (Note 6) 150 30 t DXD PCM Data Output Delay (with Programmable Delay) (Note 4) 150 31 t DXH PCM Data Output Hold Time (with Programmable Delay) (Note 4) 150 32 t DXZ PCM Data Output Delay to HI-Z (with Programmable Delay) (Note 4) 150 33 t DRS PCM Data Input Setup Time 25 34 t DRH PCM Data Input Hold Time 5

18 Am79C02/03/031(A) Data Sheet

For 2.048 MHz ±100 ppm or 4.096 MHz ±100 ppm operation: Notes: 1. DCLK may be stopped in the High or Low state indefinitely without loss of information. If CS makes a transition to the Low state, the last byte received is interpreted by the Microprocessor Interface logic. 2. The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency and synchronous to the MCLK frequency. The actual PCLK rate is dependent on the number of channels allocated within a frame. The DSLAC supports 2– 128 channels. A PCLK of 1.544 MHz can be used for standard US transmission systems. The minimum clock frequency is 128 kHz. 3. TSC is delayed from FS by a typical value of N  tPCY , where N is the value stored in the time/clock-slot register. 4. There is a special conflict detection circuitry that prevents high-power dissipation from occurring when the DXA or DXB pins of two DSLAC devices are tied together and one DSLAC device starts to transmit before the other has gone into a high- impedance state. 5. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last. 6. tTSO is defined as the time at which the output achieves the open circuit condition. 7. The DSLAC device requires 40 cycles of the 8 MHz internal clock (5 µs) between SIO operations. If the MPI is being accessed while the MCLK input is not active, a Chip Select Off time of 20 µs is required. SWITCHING WAVEFORMS Input and Output Waveforms for AC Tests Master Clock Timing No. Symbol Parameter Min Typ Max Units 35 t MCY Master Clock Period (2.048 MHz) 488.23 488.28 488.33 ns Master Clock Period (4.096 MHz) 244.11 244.14 244.17 36 t MCR Rise Time of Clock 15 37 t MCF Fall Time of Clock 15 38 t MCH MCLK High Pulse Width (2.048 MHz) 200 MCLK High Pulse Width (4.096 MHz) 80 39 t MCL MCLK Low Pulse Width (2.048 MHz) 200 MCLK Low Pulse Width (4.096 MHz) 80 Te st Points 2.0 0.8 2.0 0.8 2.4 0.45 09875H-012 09875H-013 VIH VIL

Microprocessor Interface (Input Mode) Microprocessor Interface (Output Mode) Data Valid Data Valid Outputs C5 –C1 Data Valid Data Valid VIH VIL DCLK Data Valid DIN CS VIH VIL 09875H-014 DCLK Data Valid Data Valid DOUT Three-State VOL VOH Data Valid Three-State 17 18 VIH VIL CS 09875H-015

20 Am79C02/03/031(A) Data Sheet

PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) 09875H-016 23 22 33 34 Time Slot Zero Clock Slot Zero First Bit PCLK FS DXA/DXB DRA/DRB First Bit Second Bit VOL VOH TSCA / TSCB VIH VIL VIH VIL

PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) 23 22 33 34 Time Slot Zero Clock Slot Zero First Bit PCLK FS DXA/DXB DRA/DRB First Bit Second Bit VOL VOH TSCA / TSCB VIH VIL VIH VIL 09875H-017 Note: In this mode, the PCM transmit timing is compatible with other CODEC IC’s.

22 Am79C02/03/031(A) Data Sheet

Operating the DSLAC Device The following describes the operation of either channel of the DSLAC device. The description is valid for either Channel 1 or 2. VIN in this data sheet refers to either VIN 1 or VIN2, VOUT refers to either VOUT1 or VOUT2, and CS refers to either CS1 or CS2. Power-Up Sequence from VCC = 0 V The recommended power-up sequence is to apply: 1. Power supply grounds 2. VCC /VEE 3. Signal connections 4. Hardware Reset (02 only) The software initialization should then include: 1. Select MCLK (Command 6) 2. Software Reset (Command 2) 3. Program filter coefficients and other parameters 4. Activate (Command 5) Software initialization of the DSLAC device should al- ways follow any power-up or hardware reset. Upon initial application of power, a minimum of 1 ms is needed before CS1 or CS2 may go Low and an MPI command initiated. If the power supply (VCCD1 or VCCD 2) falls below approximately 2.0 V, the device is reset and requires complete reprogramming with the above sequence. Bit 7 of the SLIC Direction Register reads back as a logical 1 to indicate that a power inter- ruption has been detected. This bit is cleared when a software reset command is sent to the DSLAC device. The RST pin may be tied to +5 V if it is not needed in the system (Am79C02 only). Active Mode Each channel of the DSLAC device can operate in either the Active (operational) or Inactive (standby) mode. In the Active mode, the DSLAC device is able to transmit and receive PCM and analog information. This is the normal operating mode when a telephone call is in progress. The Activate command, Microprocessor In- terface (MPI) Command 5, puts the device into this state. Bringing the DSLAC device into the Active mode is possible only through the MPI. Inactive Mode The DSLAC device is forced into the Inactive (standby) mode after a powerup, hardware or software reset, or is programmed into this mode by the Deactivate com- mand (Command 1). Power is switched off from all non- essential circuitry, though the MPI remains active to receive new commands. The analog output is tied to ground through an approximate 3 k Ω resistor. All cir- cuits, which contain programmed information, retain their data in the Inactive mode. Reset State An active Low, hardware Reset pin (RST ) is available on the Am79C02, which resets the device to the fol- lowing default state. (For the Am79C02, Am79C03, and Am79C031, when power is first applied, an internal power-up reset puts the device into the following de- fault state.) 1. A-law is selected 2. B, X, R, and Z filters disabled; AISN gain is zero. 3. Digital (GX and GR) gain blocks are disabled, resulting in unity gain, and analog (AX and AR) gains are set to unity. 4. SLIC input/output direction is set to the Input mode. 5. Normal conditions are selected (see Command 4). 6. The B-filter Adaptive mode is turned off. 7. Both channels placed in Inactive (standby) mode. 8. Transmit time, receive time, and clock slots are set to zero. 9. DXA/DRA ports are selected for Channel 1. 10. DXB/DRB ports are selected for Channel 2. Note: Must be reassigned to DXA/DRA for Am79C031. 11. MCLK is selected to be 4.096 MHz. 12. Transmit on the negative edge of PCLK. (XE = 0) 13. PCM Delay is inserted. Reset states 1 to 7 are identical to those of the software reset (Command 2). The software reset command af- fects only those channels that have their CS asserted. Signal Processing Overview of Digital Filters Several of the blocks in the signal processing section are user programmable. These allow the user to opti- mize the performance of the DSLAC device for the sys- tem. Figure 8 shows the DSLAC device signal processing and indicates the programmable blocks. The advantages of digital filters are: I High reliability I No drift with time or temperature I Unit-to-unit repeatability I Superior transmission performance Two-Wire Impedance Matching Two feedback paths on the DSLAC device modify the effective two-wire input impedance of the SLIC by pro- viding programmable feedback from V IN to VOUT . The Analog Impedance Scaling Network (AISN) is a pro- grammable analog gain of –0.9375 to +0.935 from V IN to VOUT . The Z filter is a programmable digital filter, also connecting VIN to VOUT .

uation distortion caused by the Z filter. provide a net gain in the range of 0 dB to 18 dB. or 6.02 dB, located immediately after the D/A converter. This provides a net loss in the range of 0 dB to 18 dB. pressed code from the digital A-law/µ-law compressor. clock slot control circuitry. Transmit Time Slot and Transmit Clock Slot registers. 128 kHz and 8.192 MHz (2 to 128 channels) in a system. PCLK periods to eliminate any clock skew in the system. Figure 8. DSLAC Block Diagram

24 Am79C02/03/031(A) Data Sheet

fractional time slot after the last full time slot in the frame contains random information and has the TSC output turned on. For example, if the PCLK frequency is 1.544 MHz (R = 1) and the transmit clock slot is greater than 1, the 1-bit fractional time slot after the last full time slot in the frame contains random information, and the TSC output remains active during the fractional time slot. The data is transmitted in bytes, with the most significant bit first. The PCM data may be user programmed for output onto either the DXA or DXB port. Correspondingly, either TSCA or TSCB is Low during transmission. The DXA/DXB and TSCA/TSCB outputs can be pro- grammed to change either on the negative or positive edge of PCLK. In the first case, an extra delay (PCM delay) in the timing of the DXA and DXB signals may be programmed to allow timing compatibility with other de- vices on the PCM highway. Receive Signal Processing In the receive path, the digital signal is expanded, fil- tered, converted to analog, and passed to the VOUT pin. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The Z, R, and GR blocks are user-programmable filter sections with their coefficients stored in the coefficient RAM, while AR is an analog amplifier that can be programmed for a 0 dB or 6.02 dB loss. The filters may be made transparent when not required in a system. The low-pass filter band limits the signal. The R filter is a six tap FIR section operating at a 16 kHz sampling rate and is part of the frequency response correction network. The Analog Impedance Scaling Network (AISN) is a user-programmable gain block providing feedback from V IN to VOUT to emulate different ZSLIC impedances from a single external ZSLIC impedance. The Z filter provides feedback from the transmit signal path to the receive path and is used to modify the effec- tive input impedance to the system. The interpolator increases the sampling rate prior to D/A conversion. Receive PCM Interface The receive PCM interface logic controls the reception of data bytes from the PCM highway, transfers the data to the A-law/µ-law expansion logic, and then passes the data to the receive path of the signal processor. The frame sync (FS) pulse identifies the beginning of a re- ceive frame, and all channels (time slots) are referenced to it. The logic contains user-programmable Receive Time Slot and Receive Clock Slot registers. The Time Slot register is 7 bits wide and allows up to 128 8-bit chan- nels (using a PCLK of 8.192 MHz) in each frame. This feature allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system. The Clock Slot register is 3 bits wide and may be pro- grammed to offset the time slot assignment by 0 to 7 PCLK periods to eliminate any clock skews in the sys- tem. An exception occurs when division of the PCLK frequency by 64 kHz produces a nonzero remainder, R (R = f PCLK modulo 64 kHz, R > 0) and when the receive clock slot is greater than R. In that case, the last receive time slot in the frame is not usable. For example, if the PCLK frequency is 1.544 MHz (R = 1), the receive clock slot can be only 0 or 1 if the last time slot is to be used. The PCM data may be user programmed for input from either the DRA or DRB port. Analog Impedance Scaling Network (AISN) The AISN is incorporated in the DSLAC device to scale the value of the external ZSLIC impedance. Scaling this external impedance with the AISN (along with the Z fil- ter) allows matching of many different line conditions using a single impedance value. Linecards may be de- signed for many different specifications without any hardware changes. The AISN is a programmable gain that is connected across the DSLAC device input from V IN to VOUT . The gain can be varied from –0.9375 to +0.9375 in 31 steps of 0.0625. The AISN gain is given by the follow- ing equation: where A, B, C, D, and E = 1 or 0. The AISN gain is used to alter the input impedance of the DSLAC device from the SLIC as given by: where G 440 (defined as G24 G42 + G44) is the echo gain into an open circuit and G44 is the echo gain into a short circuit. There are two special cases to the formula for hAISN : 1) value of ABCDE = 00000 specifies a gain of 0 (or cutoff), and 2) a value of ABCDE = 10000 is a special case where the AISN circuitry is disabled and the V OUT pad is connected internally to VIN with a gain of 0 dB. This allows a digital-to-digital Loopback mode wherein a digital PCM input signal is completely processed through the receive section all the way to the VOUT pin. The signal then is connected internally to V IN where it is processed through the transmit section and output as digital PCM data. Speech Coding The A/D and D/A conversion follows either the A-law or the µ-law as they are defined in CCITT Rec. G.711. A- law or µ-law operation is programmed using MPI Com- mand 19. Alternate bit inversion is performed as part of the A-law coding. hAISN 0.0625 A2 4 B2 3 C2 2 D2 1 E2 0++++() 16–[]= Z IN Z SL 1G 44hAISN–() 1G 440hAISN–()

Command Description and Formats Microprocessor Interface Description A microprocessor may be used to program the DSLAC device and control its operation using the Microproces- sor Interface (MPI). Data programmed previously may be read out for verification. For each channel, com- mands are provided to assign values to the following parameters. – Transmit time slot – Receive time slot – Transmit clock slot – Receive clock slot – Transmit gain – Receive loss – B-filter coefficients – X-filter coefficients – R-filter coefficients – Z-filter coefficients – Adaptive B filter parameters – AISN coefficient – Read/Write SLIC Input/Output – Select A-law or µ-law code – Select Transmit PCM Port A or B – Select Transmit PCM clock edge – Select Transmit PCM delay – Select Receive PCM Port A or B – Enable/disable B filter – Enable/disable Z filter – Enable/disable X filter – Enable/disable R filter – Enable/disable GX filter – Enable/disable GR filter – Enable/disable AX amplifier – Enable/disable AR amplifier – Enable/disable adaptive B filter – Select test modes – Select Active or Inactive (standby) mode The following description of the MPI is valid for either Channel 1 or 2. Whenever CS is specified, it refers to either CS1 or CS2. If desired, both channels may be programmed simultaneously with identical information by activating CS1 and CS2 at the same time. Com- mands that affect both channels simultaneously are not- ed as such. The MPI consists of serial data input (DIN or DIO), out- put (DOUT or DIO), data clock (DCLK), and a separate chip select (CS1 and CS2) input for each channel. The serial input consists of 8-bit command words that may be followed with additional bytes of input data or may be followed by the DSLAC device sending out bytes of data. All data input and output is MSB (D7) first and LSB (D0) last. All data bytes are read or written one at a time, with CS going High for at least the minimum off period before the next byte is read or written. All commands that require additional input data to the device must have the input data as the next N words written into the device (for example, framed by the next N transitions of CS ). All commands that are followed by output data causes the device to output data for the next N transitions of CS going Low. The DSLAC device does not accept any input commands until all the data is shifted out. Unused bits in the data bytes are read out as zeros. A command sequence to one channel must be finished before a command can be sent to the channel. The NOP Command 2 is recommended to follow any set of com- mands to the DSLAC device. The NOP is executed in the event of any anamolous CS assertion. An MPI cycle is defined by transitions of CS and DCLK. If the CS lines are held in the High state between ac- cesses, the DCLK may run continuously with no change to the internal control data. Using this method, the same DCLK may be run to a number of DSLAC devices and the individual CS lines selects the appropriate device to access. Between command sequences, DCLK can stay in the High state indefinitely with no loss of internal control information regardless of any transitions on the CS lines. Between bytes of a multibyte read or write command sequence, DCLK also can stay in the High state indefinitely; however, each low-going transition of the CS line still advances the byte counter. DCLK can stay in the Low state indefinitely with no loss of internal control information, provided the CS lines remain at a high level.

26 Am79C02/03/031(A) Data Sheet

Summary of MPI Commands** Notes: 1. *Code changes with function. 2. **All codes not listed are reserved by AMD and should not be used. C# Hex Description C# Hex Description 1. 00 Deactivate (Standby mode) 24. 80 Write GX Filter Coefficients 2. 02 Reset 25. 81 Read GX Filter Coefficients 3. 06 No Operation 26. 82 Write GR Filter Coefficients 4. 08 Reset to Normal Conditions 27. 83 Read GR Filter Coefficients 5. 0E Activate 28. 84 Write Z Filter Coefficients 6. 1* MCLK Selection 29. 85 Read Z Filter Coefficients 7. 40 Write TX Time Slot & PCM Highway 30. 86 Write B Filter Coefficients 8. 41 Read TX Time Slot & PCM Highway 31. 87 Read B Filter Coefficients 9. 42 Write RX Time Slot & PCM Highway 32. 88 Write X Filter Coefficients 10. 43 Read RX Time Slot & PCM Highway 33. 89 Read X Filter Coefficients 11. 44 Write RX & TX Clock Slot and TX Edge 34. 8A Write R Filter Coefficients 12. 45 Read RX & TX Clock Slot and TX Edge 35. 8B Read R Filter Coefficients 13. 50 Write AISN, PCM delay, Analog Gains 36. 8C Write Echo Path Gain 14. 51 Read AISN, PCM delay, Analog Gains 37. 8D Read Echo Path Gain 15. 52 Write SLIC Input/Output Register 38. 8E Write Error Level Threshold 16. 53 Read SLIC Input/Output Register 39. 8F Read Error Level Threshold 17. 54 Write SLIC Input/Output Direction 40. 92 Write GZ Filter Coefficient 18. 55 Read SLIC I/O Direction, Power Interrupt Bit, and Channel Status Bit41. 93 Read GZ Filter Coefficient 19. 60 Write Operating Functions 42. 90 Write Adaptive B Filter Control 20. 61 Read Operating Functions 43. 91 Read Adaptive B Filter Control 21. 70 Write Operating Conditions 44. 64 Write Operating Functions II 22. 71 Read Operating Conditions 45. 65 Read Operating Functions II 23. 73 Read Revision Code Number

This section describes in detail each of the MPI commands. Each of the commands is shown along with the format of any additional data bytes that follow. For details of the filter coefficients of the for Cxym xy, please refer to the Description of Coefficients section. 1. Deactivate (Standby State) (00h) During the Inactive state (of one or more channels): a) All of the programmed information is retained. b) The Microprocessor Interface (MPI) remains active. c) The PCM outputs are in high impedance and the PCM inputs are disabled. d) The analog output is tied to 2.1 V through an internal resistor (~3 k Ω ). 2. Software Reset (02h) The software reset state of the device is: a) The channel is placed in the Inactive (standby) mode. b) GX, GR, X, R, B, and Z filters are disabled with coefficients retained. c) AX and AR are set to unity and AISN gain is set to 0. d) The Adaptive B feature is disabled. e) A-law is selected. f) All SLIC I/O lines are configured as inputs. g) Normal conditions are selected (see Command 4). 3. No Operation (06h) 4. Reset to Normal Conditions (08h) Reset to Normal Conditions performs the following operations: a) Does not insert 6 dB loss in receive path. b) Receive and transmit paths are not cutoff. c) High-pass filter is enabled. d) Test modes are turned off. 5. Activate (Operational State) (0Eh) This command places the device in the Active mode. No valid PCM data is transmitted until after the second FS pulse is received following the execution of the Activate command. D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 0 0 0 0 0 0 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 0 0 0 0 0 1 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 0 0 0 0 1 1 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 0 0 0 1 0 0 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 0 0 0 1 1 1 0

28 Am79C02/03/031(A) Data Sheet

  1. MCLK Selection (10h/12h) MCLK may be selected to operate from a 2.048 MHz or 4.096 MHz external clock. MCLK selection on either channel affects both channels. A = 0: 2.048 MHz A = 1: 4.096 MHz 7. Write Transmit Time Slot and PCM Highway Selection (40h) PCM = 0: Highway A PCM = 1: Highway B TS: Time slot number 0 to 127 The PCM Highway B is not available on the Am79C031(A). The Transmit section of both channels must not be set to the same time slot on the same output port simultaneously. 8. Read Transmit Time Slot and PCM Highway Selection (41h) 9. Write Receive Time Slot and PCM Highway Selection (42h) PCM = 0: Highway A PCM = 1: Highway B TS: Time slot number 0 to 127 The PCM Highway B is not available on the Am79C031(A). 10. Read Receive Time Slot and PCM Highway Selection (43h) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 0 0 1 0 0 A 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 0 0 0 0 0 Output Data PCM TS TS TS TS TS TS TS D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 0 0 0 0 1 Output Data PCM TS TS TS TS TS TS TS D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 0 0 0 1 0 Output Data PCM TS TS TS TS TS TS TS D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 0 0 0 1 1 Output Data PCM TS TS TS TS TS TS TS
  1. Write Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge (44h) TCS: Transmit Clock Slot number 0–7 RCS: Receive Clock Slot number 0–7 XE=0 Transmit on negative edge of PCLK XE = 1 Transmit on positive edge of PCLK RSVD: Reserved. Always write as 0, but 0 is not guaranteed when read. Note: XE = 1 should not be programmed unless the PCM delay is removed (i.e., PCD = 1). The XE bit is set for both channels when written to either channel. If XE = 1, the maximum PCM clock rate becomes 4.096 MHz. 12. Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge (45h) RSVD: Reserved. Always write as 0, but 0 is not guaranteed when read. 13. Write AISN, PCM Delay, and Analog Gains (50h) PCM Delay: PCD = 0* Delay inserted (SLAC device compatible) PCD = 1 Delay removed (high speed) Transmit Analog Gain: AX = 0* 0 dB gain AX = 1 6.02 dB gain Receive Analog Loss: AR = 0* 0 dB loss AR = 1 6.02 dB loss AISN coefficient: A, B, C, D, E The Analog Impedance Scaling Network (AISN) gain can be varied from –0.9375 to 0.9375 in multiples of 0.0625. The gain coefficient is decoded using the follow- ing equation: where h AISN is the gain of the AISN and A, B, C, D, and E = 0 or 1. A value of ABCDE = 10000 implements a special digital Loopback mode, and a value of ABCDE = 00000 indicates a gain of 0 (cutoff). * Power-up default value. Note: Maximum PCLK frequency with PCM delay inserted (PCD = 0) is: 4.096 MHz. D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 0 0 1 0 0 Input Data RSVD XE RCS RCS RCS TCS TCS TCS D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 0 0 1 0 1 Output Data RSVD XE RCS RCS RCS TCS TCS TCS D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 1 0 0 0 0 Input Data PCD AX AR A B C D E

30 Am79C02/03/031(A) Data Sheet

  1. Read AISN, PCM Delay, and Analog Gains (51h) 15. Write SLIC Output Register (52h) C1 through C5 are set to 1 or 0. The data appears latched on the C1 through C5 SLIC I/O pins, provided they are set in the Output mode (see Command 17). The data sent to any of the pins set to the Input mode are latched, but do not appear at the pins. RSVD Reserved. Always write as 0, but 0 is not guaranteed when read. 16. Read SLIC Pins (53h) The logic state of pins C1 through C5 is read regardless of the direction programmed into the Input/Output register. 17. Write SLIC Input/Output Direction (54h) Pins C1x through C5x are set to input or output modes individually. Pins C51 and C52 are not available on the Am79C03(A). C51 and C52 pins are output only on the Am79C031(A) and must be programmed as outputs with this command. All unused SLIC I/O pins should be programmed as outputs to reduce power consumption. Data bit A sets pins C51 or C52. Data bit B sets pins C41 or C42. Data bit C sets pins C31 or C32. Data bit D sets pins C21 or C22. Data bit E sets pins C11 or C12. Data bit = 0; Pin mode = Input.* Data bit = 1; Pin mode = Output. RSVD Reserved. Always write as 0, but 0 is not guaranteed when read. * Power up default value D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 1 0 0 0 1 Output Data PCD AX AR A B C D E D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 1 0 0 1 0 Input Data RSVD RSVD RSVD C5 C4 C3 C2 C1 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 1 0 0 1 1 Output Data RSVD RSVD RSVD C5 C4 C3 C2 C1 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 1 0 1 0 0 Input Data RSVD RSVD RSVD C5 C4 C3 C2 C1
  1. Read SLIC Input/Output Direction, Channel Status Bit, and Power Interrupt Bit (55h) Power Interruption PI = 0 There has not been a power interruption since the last software reset command. PI = 1 A power interruption has been previously detected requiring the DSLAC device to be completely reprogrammed. This bit is cleared by issuing a software reset command. Channel Status CSTAT = 0 Channel is inactive (Standby mode). CSTAT = 1 Channel is active. D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 0 1 0 1 0 1 Output Data PI CSTAT RSVD A B C D E

32 Am79C02/03/031(A) Data Sheet

  1. Write Operating Functions (60h) Adaptive B Filter ABF = 0* B filter Nonadaptive mode PCD = 1 B filter Adaptive mode A-law/µ-law A/m = 0* A-law coding A/m = 1 µ-law coding GR Filter EGR = 0* GR filter disabled EGR = 1 GR filter enabled GX Filter EGX = 0* GX filter disabled EGX = 1 GX filter enabled X Filter EX = 0* X filter disabled EX = 1 X filter enabled R Filter ER = 0* R filter disabled ER = 1 R filter enabled Z Filter EZ = 0* Z filter disabled EZ = 1 Z filter enabled B Filter EB = 0* B filter disabled EB = 1 B filter enabled * Power up default value. Note: The enable adaptive B filter command only is effective when used with the enable B filter command. 20. Read Operating Functions (61h) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 1 0 0 0 0 0 Input Data ABF A/µ EGR EGX EX ER EZ EB D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 1 0 0 0 0 1 Input Data ABF A/µ EGR EGX EX ER EZ EB
  1. Write Operating Conditions (70h) Cut off Transmit Path CTP = 0* Transmit path connected CTP = 1 Transmit path cut off (see note) Cut off Receive Path CRP = 0* Receive path connected CRP = 1 Receive path cut off High-Pass Filter HPF = 0* High-pass filter enabled HPF = 1 High-pass filter disabled Receive Path Gain RG = 0* 6 dB loss not inserted RG = 1 6 dB loss inserted Analog Loopback ALB = 0* Analog loopback disabled ALB = 1 Analog loopback enabled TSA Loopback TLB = 0* TSA loopback disabled TLB = 1 TSA loopback enabled RSVD = Reserved. Always write as 0, but 0 is not guaranteed when read. * Power up default value. Note: The B Filter still is connected across the PCM highway during Receive Cut off. Accompany Receive Cut off with a B Filter disable command. 22. Read Operating Conditions (71h) 23. Read Revision Code Number (73h) This command returns an 8-bit number describing the revision number of the DSLAC device. It can be read on either channel. D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 1 1 0 0 0 0 Input Data CTP CRP HPF RG ALB TLB RSVD RSVD D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 1 1 0 0 0 1 Output Data CTP CRP HPF RG ALB TLB RSVD RSVD D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 0 1 1 1 0 0 1 1

34 Am79C02/03/031(A) Data Sheet

  1. Write GX Filter Coefficients (80h) The coefficient for the GX filter is defined as: 25. Read GX Filter Coefficients (81h) 26. Write GR Filter Coefficients (82h) The coefficient for the GR filter is defined as: 27. Read GR Filter Coefficients (83h) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 1 0 0 0 0 0 0 0 Input Data Byte 1 C40 m40 C30 m30 Input Data Byte 2 C20 m20 C10 m10 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 1 0 0 0 0 0 0 1 Output Data Byte 1 C40 m40 C30 m30 Output Data Byte 2 C20 m20 C10 m10 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 1 0 0 0 0 0 1 0 Input Data Byte 1 C40 m40 C30 m30 Input Data Byte 2 C20 m20 C10 m10 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Command 1 0 0 0 0 0 1 1 Output Data Byte 1 C40 m40 C30 m30 Output Data Byte 2 C20 m20 C10 m10
  1. Write Z Filter Coefficients (84h) The Z-transform equation for the Z filter is defined as: The coefficients are defined as: 29. Read Z Filter Coefficients (85h) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10000100 Input Data Byte 1 C45 m45 C35 m35 Input Data Byte 2 C25 m25 C15 m15 Input Data Byte 3 C40 m40 C30 m30 Input Data Byte 4 C20 m20 C10 m10 Input Data Byte 5 C41 m41 C31 m31 Input Data Byte 6 C21 m21 C11 m11 Input Data Byte 7 C42 m42 C32 m32 Input Data Byte 8 C22 m22 C12 m12 Input Data Byte 9 C43 m43 C33 m33 Input Data Byte 10 C23 m23 C13 m13 Input Data Byte 11 C44 m44 C34 m34 Input Data Byte 12 C24 m24 C14 m14 Input Data Byte 13 C46 m46 C36 m36 Input Data Byte 14 C26 m26 C16 m16 D

7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Output Data Byte 1 C45 m45 C35 m35 Output Data Byte 2 C25 m25 C15 m15 Output Data Byte 3 C40 m40 C30 m30 Output Data Byte 4 C20 m20 C10 m10 Output Data Byte 5 C41 m41 C31 m31 Output Data Byte 6 C21 m21 C11 m11 Output Data Byte 7 C42 m42 C32 m32 Output Data Byte 8 C22 m22 C12 m12 Output Data Byte 9 C43 m43 C33 m33 Output Data Byte 10 C23 m23 C13 m13 Output Data Byte 11 C44 m44 C34 m34 Output Data Byte 12 C24 m24 C14 m14 Output Data Byte 13 C46 m46 C36 m36 Output Data Byte 14 C26 m26 C16 m16 H z z() Z 0 Z 1z 1– Z 2z 2– Z 3z 3– Z 4z 4– Z 5 1Z 6z 1–– Z i Cli 2 m1i–• 1C 2 i2 m2i– 1C 3 i2 m3i– 1C 4 i2 m4i–•+()•+[]•+{}=

36 Am79C02/03/031(A) Data Sheet

  1. Write B Filter Coefficients (86h) The Z-transform equation for the B filter is defined as: The coefficients for the FIR B section and the gain of the IIR B section are defined as: The feedback coefficient of the IIR B section is defined as: Warning: Not all B filter coefficients are “valid” to initiate adaptive balance. One valid coefficient is set as: 2A F2 AF 2A F2 AF 2A F2 AF 2A F2 AF 0A 80, which corresponds to all FIR coefficients (B0–B7) equal to zero, and the IIR denomination coefficient (B8) equal to 1/2. Other valid coefficients that may reduce the time to convergence of the algorithm may be obtained by reading back the registers after adaptive balance has been run (see Command 31). D

Input Data Byte 1 C30 m30 C20 m20 Input Data Byte 2 C10 m10 C31 m31 Input Data Byte 3 C21 m21 C11 m11 Input Data Byte 4 C32 m32 C22 m22 Input Data Byte 5 C12 m12 C33 m33 Input Data Byte 6 C23 m23 C13 m13 Input Data Byte 7 C34 m34 C24 m24 Input Data Byte 8 C14 m14 C35 m35 Input Data Byte 9 C25 m25 C15 m15 Input Data Byte 10 C36 m36 C26 m26 Input Data Byte 11 C16 m16 C37 m37 Input Data Byte 12 C27 m27 C17 m17 Input Data Byte 13 C48 m48 C38 m38 Input Data Byte 14 C28 m28 C18 m18 H B z() B 0 B 1z 1– B 2z 2– B 3z 3– B 4z 4– B 5z 5– B 6z 6– B 7z 7– 1B 8z 1–– B i Cli 2 m1i–• 1C 2 i2 m2i– 1C 3 i2 m3i–•+()•+[]=

  1. Read B Filter Coefficients (87h) 32. Write X Filter Coefficients (88h) The Z-transform equation for the X filter is defined as: The coefficients for the X filter are defined as: D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10000111 Output Data Byte 1 C30 m30 C20 m20 Output Data Byte 2 C10 m10 C31 m31 Output Data Byte 3 C21 m21 C11 m11 Output Data Byte 4 C32 m32 C22 m22 Output Data Byte 5 C12 m12 C33 m33 Output Data Byte 6 C23 m23 C13 m13 Output Data Byte 7 C34 m34 C24 m24 Output Data Byte 8 C14 m14 C35 m35 Output Data Byte 9 C25 m25 C15 m15 Output Data Byte 10 C36 m36 C26 m26 Output Data Byte 11 C16 m16 C37 m37 Output Data Byte 12 C27 m27 C17 m17 Output Data Byte 13 C48 m48 C38 m38 Output Data Byte 14 C28 m28 C18 m18 D

Input Data Byte 1 C40 m40 C30 m30 Input Data Byte 2 C20 m20 C10 m10 Input Data Byte 3 C41 m41 C31 m31 Input Data Byte 4 C21 m21 C11 m11 Input Data Byte 5 C42 m42 C32 m32 Input Data Byte 6 C22 m22 C12 m12 Input Data Byte 7 C43 m43 C33 m33 Input Data Byte 8 C23 m23 C13 m13 Input Data Byte 9 C44 m44 C34 m34 Input Data Byte 10 C24 m24 C14 m14 Input Data Byte 11 C45 m45 C35 m35 Input Data Byte 12 C25 m25 C15 m15 H x z() X 0 X 1z 1– X 2z 2– X 3z 3– X 4z 4– X 5z 5–+++++= X i Cli 2 m1i–• 1C 2 i2 m2i– 1C 3 i2 m3i–• 1C 4 i2 m4i–•+()+[]•+{}=

38 Am79C02/03/031(A) Data Sheet

  1. Read X Filter Coefficients (89h) 34. Write R Filter Coefficients (8Ah) The Z-transform equation for the R filter is defined as: The coefficients for the R filter are defined as: D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10001001 Output Data Byte 1 C40 m40 C30 m30 Output Data Byte 2 C20 m20 C10 m10 Output Data Byte 3 C41 m41 C31 m31 Output Data Byte 4 C21 m21 C11 m11 Output Data Byte 5 C42 m42 C32 m32 Output Data Byte 6 C22 m22 C12 m12 Output Data Byte 7 C43 m43 C33 m33 Output Data Byte 8 C23 m23 C13 m13 Output Data Byte 9 C44 m44 C34 m34 Output Data Byte 10 C24 m24 C14 m14 Output Data Byte 11 C45 m45 C35 m35 Output Data Byte 12 C25 m25 C15 m15 D

Input Data Byte 1 C40 m40 C30 m30 Input Data Byte 2 C20 m20 C10 m10 Input Data Byte 3 C41 m41 C31 m31 Input Data Byte 4 C21 m21 C11 m11 Input Data Byte 5 C42 m42 C32 m32 Input Data Byte 6 C22 m22 C12 m12 Input Data Byte 7 C43 m43 C33 m33 Input Data Byte 8 C23 m23 C13 m13 Input Data Byte 9 C44 m44 C34 m34 Input Data Byte 10 C24 m24 C14 m14 Input Data Byte 11 C45 m45 C35 m35 Input Data Byte 12 C25 m25 C15 m15 H R z() R 0 R 1z 1– R 2z 2– R 3z 3– R 4z 4– R 5z 5–+++++= R i Cli 2 m1i–• 1C 2 i2 m2i– 1C 3 i2 m3i–• 1C 4 i2 m4i–•+()+[]•+{}=

  1. Read R Filter Coefficients (8Bh) 36. Write Echo Path Gain (8Ch) The equation for the Echo Path Gain is defined as: 37. Read Echo Path Gain (8Dh) 38. Write Error Level Threshold (8Eh) The equation for the Error Level Threshold is defined as: D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10001011 Output Data Byte 1 C40 m40 C30 m30 Output Data Byte 2 C20 m20 C10 m10 Output Data Byte 3 C41 m41 C31 m31 Output Data Byte 4 C21 m21 C11 m11 Output Data Byte 5 C42 m42 C32 m32 Output Data Byte 6 C22 m22 C12 m12 Output Data Byte 7 C43 m43 C33 m33 Output Data Byte 8 C23 m23 C13 m13 Output Data Byte 9 C44 m44 C34 m34 Output Data Byte 10 C24 m24 C14 m14 Output Data Byte 11 C45 m45 C35 m35 Output Data Byte 12 C25 m25 C15 m15 D

Input Data Byte 1 C80 m80 C70 m70 Input Data Byte 2 C60 m60 C50 m50 I n p u t D a t a B y t e 3 00000000 I n p u t D a t a B y t e 4 00000011 D Output Data Byte 1 C80 m80 C70 m70 Output Data Byte 2 C60 m60 C50 m50 O u t p u t D a t a B y t e 3 00000000 O u t p u t D a t a B y t e 4 00000011 D Input Data Byte 1 C20 m20 C10 m10 ELT C10 2 m10–• 1C 2 02 m20–•+()=

40 Am79C02/03/031(A) Data Sheet

  1. Read Error Level Threshold (8Fh) 40. Write GZ Filter Coefficient (92h) RSVD Reserved. Always write as 0, but 0 is not guaranteed when read. The coefficient, GZ, is defined as: The default value after any reset is GZ = 0 hex for a gain of 1. 41. Read GZ Filter Coefficient (93h) 42. Write Adaptive B Filter Control Coefficients (90h) The equations for the decorrelation threshold coefficients are: The equation for the low level signal threshold coefficient is: The equation for the digital prebalance threshold coefficient is: D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10001111 Output Data Byte 1 C20 m20 C10 m10 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10010010 Input Data C10 m10 RSVD RSVD RSVD RSVD D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10010011 Output Data C10 m10 RSVD RSVD RSVD RSVD New to Revision E D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10010000 Input Data C20 m20 C10 m10 Input Data C21 m21 C11 m11 Input Data C32 m32 C22 m22 Input Data C12 m12 C33 m33 Input Data C23 m23 C13 m13 GZ C10 2 m10–•= DCR1 C10 2 m10–• 1C 2 02 m20–•+()= DCR2 C11 2 m11–• 1C 2 12 m21–•+()=
  1. Read Adaptive B Filter Coefficients (91h) 44. Write Operating Functions 2 (64h) Chopper Clock Control CHP = 0 Chopper Clock is 256 kHz CHP = 1 Chopper Clock is 292.571 kHz Adaptation Control EAC = 0 LST, DCR1, and DCR2 are disabled EAC = 1 LST, DCR1, and DCR2 are enabled EPB = 0 DPB is disabled EPB = 1 DPB is enabled 45. Read Operating Functions 2 (65h) RSVD Reserved. Always write as 0, but 0 is not guaranteed when read. Programmable Filters General Description of CSD Coefficients The filter functions are performed by a series of multi- plications and accumulations. A multiplication is accom- plished by repeatedly shifting the multiplicand and summing the result with the previous value at that sum- mation node. The method used in the DSLAC device is known as Canonic Signed Digit (CSD) multiplication and splits each coefficient into a series of CSD coefficients. Each programmable FIR filter section has the following general transfer function: Eq. (1) where the number of taps in the filter = n + 1. The transfer function for IIR part of Z and B filters is: Eq. (2) The values of the user-defined coefficients (hi) are as- signed via the MPI. Each of the coefficients (hi) is de- fined in the following general equation: Eq. (3) where: M i = the number of shifts ≤ Mi + 1 Bi = sign = ±1 N = number of CSD coefficients New to Revision E D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 10010001 Output data C20 m20 C10 m10 Output data C21 m21 C11 m11 Output data C32 m32 C22 m22 Output data C12 m12 C33 m33 Output data C23 m23 C13 m13 New to Revision E D

Input data RSVD RSVD RSVD RSVD RSVD CHP EAC EPB New to Revision E D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C o m m a n d 01100101 Output data RSVD RSVD RSVD RSVD RSVD CHP EAC EPB HF z() h0 h1z 1– h2z 2– … hnz n–+++ += HI z() 1 1h n1+() z 1–– hi B 12 M1– B 22 M2– … B N 2 MN–++ +=

42 Am79C02/03/031(A) Data Sheet

The value of hi in Equation 3 represents a decimal number that is broken down into a sum of successive values of: ±1.0 multiplied by 2 or The limit on the negative powers of 2 is determined by the length of the registers in the ALU. The coefficient hi in Equation 3 can be considered to be a value made up of N binary 1s in a binary register where the leftmost part represents whole numbers, the right- most part represents decimal fractions, and a decimal point separates them. The first binary 1 is shifted M1 bits to the right of the decimal point, the second binary 1 is shifted M2 bits to the right of the decimal point, the third binary 1 is shifted M3 bits to the right of the decimal point, and so on. Note that when M1 is 0, the resulting value is a binary 1 in front of the decimal point, that is, no shift. If M2 also is 0, the result is another binary 1 in front of the decimal point, giving a total value of binary 10 in front of the dec- imal point (i.e., a decimal value of 2.0). The value of N, therefore, determines the range of values the coefficient h i can take (e.g., if N = 3, the maximum and minimum values are ±3, and if N = 4, the values are between ±4). Detailed Description of DSLAC Device Coefficients The CSD coding scheme in the DSLAC device uses a value called mi, where m1 represents the distance shift- ed right of the decimal point for the first binary 1. m2 represents the distance shifted to the right of the previ- ous binary 1, and m3 represents the number of shifts to the right of the second binary 1. Note that the range of values determined by N is unchanged. Equation 3 now is modified (in the case of N = 4) to: Eq. (4) Eq. (5) Eq. (6) where: and In the DSLAC device, a coefficient, h i, consists of N CSD coefficients, each being made up of 4 bits and formatted as Cxymxy, where Cxy is one bit (MSB) and mxy is 3 bits. Each CSD coefficient is broken down as follows: C xy is the sign bit (0 = positive, 1 = negative). mxy is the 3-bit shift code. It is encoded as a binary number as follows: 000: 0 shifts 001: 1 shifts 010: 2 shifts 011: 3 shifts 100: 4 shifts 101: 5 shifts 110: 6 shifts 111: 7 shifts y is the coefficient number (the i in h i). x is the position of this CSD coefficient position of the binary 1 represented by this CSD coef- ficient within the hi coefficient. The most sig- nificant binary 1 is represented by x = 1. The next most significant binary 1 is represented by x = 2, and so on. Thus, C13m13 represents the sign and the relative shift position for the first (most significant) binary 1 in the 4th (h3) coefficient. The number of CSD coefficients, N, is limited to 4 in the GR, GX, R, X, Z, and the IIR part of the B filter, and 3 for the FIR part of the B filter. Note also that the GX filter coefficient equation is slightly different from that of the other filters. Eq. (7) Please refer to the section detailing the commands for complete details on the programming of the coefficients. Adaptive B Filter Overview The DSLAC device B filter is designed to work with pre- programmed coefficients or with coefficients deter- mined by an adaptive algorithm (Note: The adaptive transhybrid balance feature is guaranteed only on the Am79C02A/03A/031A versions). The adaptive algo- rithm can be operated in a mode where it continuously adapts or where it adapts for a short period, and then holds its value. Operation with preprogrammed coefficients requires only the use of MPI Command 30 to feed in the coeffi- cients. The Adaptive mode uses some preprogrammed coefficients and generates new ones using an algo- rithm, which by a series of iterations, minimizes the re- ceive signal that is echoed in the transmit signal (due to mismatches in the SLIC, hybrid, and line). Adaptation applies to the FIR part of the filter only. Preprogrammed coefficients used to initiate the adaptive algorithm must be “valid” (shown under Command 30). Other valid co- efficients may be obtained by using this coefficient, run- ning adaptive balance, and then reading back the registers (refer to #30 in command structure). hi B 12 M1– B 22 M2– B 32 M3– B 42 M4–+++= hi C 12 m1– C 1C 22 m1 m2+()– C 1C 2C 32 m1 m2 m3++()– C 1C 2C 3C 42 m1 m2 m3 m4+++()– hi C 12 m1– 1C 22 m2– 1C 32 m3– 1C 42 m4–+()•

  • +{ M 1 m 1 M 2 m 1 m 2 M 3 m 1 m 2 m 3 M 4 m 1 m 2 m 3 m 4+++= ++= = B 1 C 1 B 2 C 1 C 2• B 3 C 1 C 2• C 3 B 4 C 1 C 2• C 3• C 4• hiGX 1h i+=

In the continuous Adaptation mode, the algorithm is switched on (via MPI Command 19) after a call is con- nected and remains on until the call ends. In this way, the B filter is continually being optimized to the re- ceived signal. In the Adapt and Freeze modes, the algorithm is used only when a line is brought into service and the DSLAC device is activated. The algorithm is switched on and is allowed to converge with the received signal, which is a bandlimited white noise signal generated in the ex- change for this purpose. The noise signal need only be injected for less than a second to yield converged coef- ficients. The Adaptive mode then is switched off (via Command 19). The converged coefficients may be read out of the DSLAC device (using MPI Command 31) and stored for future reference. The DSLAC device is now optimized for general input signals. Adaptive Filter Programming The purpose of the B filter is to cancel the received signal that leaks across the hybrid into the transmit path. The B filter transfer function must match (as closely as possible) the transfer function of the echo path. There are two programmable registers associated with the adaptive B filtering. The Echo Path Gain (EPG) is a programmable value that predicts the amount of the receive signal leaking across the hybrid to the transmit path. The EPG is used as part of an algorithm, which stops the adaptive filter from iterating in the presence of signals from the subscriber line (nearend talker). The Error Level Threshold (ELT) is a programmable val- ue that determines the transhybrid loss the adaptive filter attempts to meet. The adaptive algorithm contin- ues to iterate until it meets the loss requirement speci- fied by the ELT. Both the EPG and ELT values are generated by the WinSLAC™ software program (for- merly AmSLAC2 ™ software). Please refer to the soft- ware technical documentation. User Test Modes The DSLAC device supports testing by providing both digital and analog loopback paths as shown in Figure 8. In the TSA Loopback mode, the DR input is connected to the DX output in the Time Slot Assigner circuitry. The TSA Loopback mode is programmed via Command 21. A different type of digital loopback is provided when the AISN register is programmed with a value of 10000. In this case, the AISN circuitry is disabled and the VOUT pad is connected internally to VIN. This allows the D/A and A/D converters to be included in the digital loopback test. This mode is programmed via Command 13. Note that the signal, which is connected internally from VOUT to VIN, also is present on the VOUT pin. The VIN input can be connected to the VOUT output through the Z filter for analog loopback. The response of the line to low frequencies can be tested by disabling the high-pass filter. Additionally, the receive and trans- mit paths may be cut off.

44 Am79C02/03/031(A) Data Sheet

Table 1 and Table 2 show the companding definitions used for A-law and µ-law PCM encoding. Table 1. A-Law: Positive Input Values

  1. 4096 normalized value units correspond to TMAX = 3.14 dBm0.
  2. The character signals are obtained by inverting the even bits of the signals of column 6. Before this inversion, the character

is 128+n, expressed as a binary number. 128 is a virtual decision value.

  1. Bit 1 is a 0 for negative input values.

Table 2. µ-Law: Positive Input Values

  1. 8159 normalized value units correspond to TMAX = 3.17 dBm0.
  2. The character signal corresponding to positive input values between two successive decision values numbered n and n+1

(see column 4) is 255-n, expressed as a binary number.

  1. x128 is a virtual decision value.
  2. Bit 1 is a 0 for negative input values.

46 Am79C02/03/031(A) Data Sheet

APPLICATIONS

The DSLAC device performs a programmable codec/ filter function for two telephone lines. It interfaces to the telephone lines through either a transformer or an electronic SLIC, such as the AMD SLIC devices. The DSLAC device provides latched digital I/O to control and monitor two SLICs and has a selectable clock out- put to operate the switched mode regulator in an Am795XX family SLIC. When several line conditions must be matched, a single SLIC design can be used. The line characteristics (such as apparent impedance, attenuation, and hybrid balance) can be modified by programming each DSLAC channel’s coefficients to meet desired performance. The DSLAC device can drive a transformer SLIC device without a buffer. Connection to a PCM highway backplane is implement- ed by means of a simple buffer chip. Several DSLAC devices can be bused together into one bus interface buffer. An intelligent bus interface chip is not required because each DSLAC device provides its own buffer control. The DSLAC device can be controlled through the Microprocessor Interface, either by a microproces- sor on the linecard or by a central processor. Controlling the SLIC SLIC Chopper Clock The CHCLK output pin on the DSLAC device drives the CHCLK inputs for AMD switcher type SLICs. The CHCLK output is a 256 kHz or 293 kHz, TTL compatible signal that can drive two SLICs. It is active only when one or both channels are activated; otherwise, it is held high internally. SLIC Input/Output The Am79C02(A) and Am79C031(A) DSLAC device have five TTL compatible I/O pins (C1 to C5) for each channel. The Am79C03(A) DSLAC device has only C1 through C4 available. The outputs are programmed us- ing Command 15 and the status is read back using Command 16. The direction of the pins (input or output) is specified by programming the SLIC I/O direction reg- ister (Command 17). The C5 pins of the Am79C031(A) are output only and must be programmed as outputs to be used. Calculating Coefficients with WinSLAC Software The WinSLAC software is a program that models the DSLAC device, the line conditions, the SLIC, and the linecard components to obtain the coefficients of the programmable filters of the DSLAC device and some of the transmission performance plots. The following parameters relating to the desired line con- ditions and the components/circuits used in the linecard are to be provided as input to the program: 1. Line impedance or the balance impedance of the line is specified by the local PTT. 2. Desired two-wire impedance that is to appear at the linecard terminals of the exchange. 3. Tabular data for templates describing the frequency response and attenuation distortion of the design. 4. Relative analog signal levels for both the transmit and receive two-wire signals. 5. Component values and SLIC device selection for the analog portion of the line circuits. 6. Two-wire return loss template is usually specified by the local PTT. 7. Four-wire return loss template is usually specified by the local PTT. The output from the WinSLAC program includes the coefficients of the GR, GX, Z, R, X, B, and EPG filters as well as transmission performance plots of two-wire return loss, receive and transmit path frequency re- sponse, and four-wire return loss. The software supports the use of the AMD SLICs or allows entry of a SPICE netlist describing the behavior of any type of SLIC circuit.

 The physical dimensions (PL032 and PL044) were added to the Physical Dimensions section.  Deleted the Plastic DIP pin and references to it.  Updated the Pin Description table to correct inconsistencies. Also, deleted the last sentence in the MCLK and PCLK rows.  Minor changes were made to the data style and format to conform to AMD standards.  In Note #2 on page 18, the first sentence was modified and the second sentence was deleted. .050 REF..026 .032 TOP VIEW Pin 1 I.D. .485 .495.447 .453 .585 .595 .547 .553 16-038FPO-5 PL 032 DA79 6-28-94 ae SIDE VIEW SEATING PLANE .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 REF. .490 .530 TOP VIEW SEATING PLANE .685 .695 .650 .656Pin 1 I.D. .685 .695 .650 .656 .026 .032 .050 REF .042 .056 .062 .083 .013 .021 .590 .630 .500 REF .009 .015 .165 .180 .090 .120 16-038-SQ PL 044 DA78 6-28-94 ae SIDE VIEW

48 Am79C02/03/031(A) Data Sheet

 Page 45, Table 2, changed values in column 7. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifi- cations and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intel- lectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD ’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. © 1999 Advanced Micro Devices, Inc. All rights reserved. Trademarks AMD, the AMD logo, and combinations thereof, and AmSLAC2, DSLAC, SLAC, and WinSLAC are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.