AM7992B AMD | Alldatasheet
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Publication# 03378 R ev: I Amendment/0 Issue Date: M ay 1993 1 Am7992B Serial Interface Adapter (SIA) DISTINCTIVE CHAR ACTERISTICS n Compatible with lEEE 802.3/Ethernet/Cheapernet specifications n Crystal/TTL oscillator-controlled Manchester encoder n Manchester decoder acquires clock and data within four bit times with an accuracy of 3 ns n Guaranteed carrier and collision detection squelch threshold limits — Carrier/collision detected for inputs greater than –275 mV — No carrier/collision for inputs less than –175 mV n Input signal conditioning rejects transient noise — Transients <10 ns for collision detector inputs — Transients <20 ns for carrier detector inputs n Receiver decodes Manchester data with w orst case 19 ns of clock jitter (at 10 MHz) n TTL-compatible host interface n Transmit accuracy +0.01% (without adjustments) GENERAL DESCRIPTION The Am7992B Se rial Interface Adapter (SIA) is a Manchester encoder/decoder compatible with IEEE 802.3, Cheapernet, and Ethernet specifications. In an IEEE 802.3/Ethernet application, the Am7992B inter- faces the Am7990 Local Area Network Controller for Ethernet (LANCE) to the Ethernet transceiver device, acquires clock and data within four bit times, and de- codes Manchester data with worst case 19 ns phase jitter at 10 MHz. SIA provides both guaranteed signal threshold limits and transient noise suppression cir- cuitry in both data and collision paths to minimize false start conditions. BLOCK DI AGRAM 03378I-1 Manchester Decoder Data Receiver Noise Reject Filter Carrier Detect Noise Reject Filter Collision Detect Manchester Encoder C rystal OSC Receive Data (RX) Receive Clock (RCLK) Carrier Present (RENA) Collision (CLSN) Transmit Data (TX) Transmit Enable (TENA) Transmit Clock (TCLK)
20 MHz
Receive– Collision+ Transmit+ Transmit– Collision– Controller Interface Transceiver Interface
2 Am7992B
RELATED PRODUCTS
Part No. Description Am7990 Local Area Network Controller for Ethernet (LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet/Transceiver Am79C900 Integrated Local Area Communications ControllerTM (ILACCTM ) CONNECTION DIAGRAMS Receive+ Collision– DIP CLSN TCLK Collision+ TEST Transmit+ TX GND1 RCLK RX Receive– V CC1 PF TENA RENA TSEL GND2 RF GND3 Transmit– V CC2 Note: Pin 1 is marked for orientation. PLCC 03378I-2 03378I-3 1234 28 27 26 255 18171615 12 13 14 RCLK NC TSEL GND1 GND2 Receive- TEST V CC1 NC VCC2 PF RF GND3 Transmit+ Transmit- NC TX TCLK TENA NC CLSN RX RENA Colision+ Colision- Receive+
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. Valid Combinations Valid combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM7992B D C DEVICE NUMBER/DESCRIPTION Am7992B Serial Interface Adapter OPTIONAL P R OCESSING Blank = Standard Processing B = Burn-In OPER ATING CONDITIONS C = Commercial (0°C to +70°C) PACK AG E TYPE D = 24-Pin (Slim) Ceramic DIP (CD3024) J = 28-Pin PLCC (PL 028) P = 24-Pin (Slim) Plastic DIP (PD3024) SPEED Not Applicable B Valid Combinations AM7992B D C, DCB, JC, JCTR, PC
4 Am7992B
Collision (Output, TTL Active HIGH) Signals at the Collision terminals meeting threshold and pulse-width requirements will produce a logic HIGH at CLSN output. When no signal is present at Collision , CLSN output will be LO W . RX Receive Data (Output) A MOS/TTL output, recovered data. When there is no signal at Receive and TEST is HIGH, RX is HIGH. RX is actuated with RCLK and remains active until RENA is deasserted at the end of the message. During recep- tion, RX is synchronous with RCLK and changes after the rising edge of RCLK. Whe n TEST is LO W , RX is enabled. RENA Receive Enable (Output, TTL Active HIGH) When there is no signal at Receive+, RENA is LO W . Signals meeting threshold and pulse-width “on” re- quirements will produce a logic HIGH at RENA. When RENA is HIGH, Receive+ signals meeting threshold and pulse-width “off” requirements will produce a LO W at RENA. RCLK Receive Clock (Output) A MOS/TTL output, recovered clock. When there is no signal at Receive and TEST is HIGH, RCLK is LO W . RCLK is activated 1/4 bit time after the second negative Manchester preamble clock transition at Receive and remains active until after an end of message. When TEST is LO W , RCLK is enabled and meets minim um pulse-width specifications. TX Transmit (Input) TTL-compatible input. Whe n TENA is HIGH, signals at TX meeting setup and hold time to TCLK will be encoded as normal Manchester at Transmit+ and Transmit–. n TX HIGH : Transmit+ is negative with respect to Transmit– for first half of data bit cell. n TX L O W : Transmit+ is positive with respect to Transmit– for first half of data bit cell. TENA Transmit Enable (Input) TTL-compatible input. Active HIGH data encoder enable. Signals meeting setup and hold time to TCLK will allow encoding of Manchester data from TX to Transmit+ and Transmit–. TCLK Transmit Clock (Output) MOS/TTL output. TCLK provides symmetrical HIGH and LO W clock signals at data rate for reference timing of data to be encoded. It also provides clock signals for the controller chip (Am7990—LANCE) and an internal timing reference for receive path voltage-controlled oscillators. Transmit+, Transmit– Transmit (Outputs) A differential line output. This line pair is intended to op- erate into terminated transmission lines. For signals meeting setup and hold time to TCLK at TENA an d TX, Manchester clock and data are outputted at Transmit+/ Transmit–. When ope rating into a 78 W terminated transmission line, signaling meets the required output levels and skew for both Ethernet and IEEE 802.3 drop cables. Receive+, Receive– Receiver (Inputs) A differential input. A pair of internally biased line re- ceivers consisting of a carrier detect receiver with offset threshold and noise filtering to detect the line activity, and a data recovery receiver with no offset for Manchester data decoding. Collision+, Collision– Collision (Inputs) A differential input. An internally biased line receiver input with offset threshold and noise filtering. Signals at Collision have no effect on data-path functions. TSEL Transmit Mode Select (Output, Open Collector; Input, Sense Amplifier) n TSEL LO W : Idle transmit state Transmit+ is positive with respect to Transmit–. n TSEL HIGH : Idle transmit state Transmit+ and Transmit– are equal, providing “zero” differential to operate transformer-coupled loads. When connected with an RC netw ork, TSEL is held LO W du ring transmission. At the end of transmission the open collector output is disabled, allowing TSEL to rise and provide a smooth transmission from logic HIGH to “zero” differential idle. Delay and output return to zero are externally controlled by the RC network at TSEL and Transmit load inductance.
X , X Biased Crystal Oscillator (Input) X is the input and X is the bypass port. When con- nected for crystal operation, the system clock that ap- pears at TCLK is half the frequency of the crystal oscillator. X may be driven from an external source of two times the data rate. RF Frequency Setting Voltage-Controlled Oscillator CO ) Loop Filter (Output) This loop filter output is a reference voltage for the re- ceive path phase detector. It also is a reference for tim- ing noise immunity circuits in the collision and receive enable path. Nominal reference V CO gain is 1.25 TCLK frequency MHz/V. PF Receive Path V CO Phase-Locked Loop Filter (Input) This loop filter input is the control for receive path loop damping. Frequency of the receive V CO is internally lim- ited to transmit frequency 12% . Nominal receive V CO gain is 0.25 reference V CO gain MHz/V. TEST Test Control (Input) A static input that is connected to V CC for Am7992B/ Am7990 ope ration and to ground for testing of Receive path threshold and RCLK output HIGH parameters. Whe n TEST is grounded, RX is enabled and RCLK is enabled except during clock acquisition, when RCLK is HIGH. GND1 High Current Ground GND2 Logic Ground GND3 Voltage-Controlled Oscillator Ground V CC1 High Current and Logic Supply V CC2 Voltage-Controlled Oscillator Supply
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20 MHz and 10 MHz clocks are fed into the Manchester
Figure 1. Transmit Section Figure 2. Transmit Mode Select (TSEL) Connection
Figure 3. TTL Clock Driver Circuit for X
1.5 V input
stream into clock and NRZ data. Figure 4. Receiver
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ception Clock Acquisition w aveform diagram). to RX output at 1/4 bit time in bit cell 6. Figure 5. Receiver Section Detail
40.0 MHz
to minimize noise sensitivity to the Receive– inputs. same w ay as the receive inputs (see Figure 6).
- Connect R1, R2, C1, C2 for 0 differential nontransmit. Connect to ground for logic 1 differential nontransmit.
- Pin 20 shown for normal device operation.
- The inclusion of C4 and C5 is necessary to reduce the common-mode loading on certain transceivers that are direct
- C2 reduces the amount of noise from the power supply and crosstalk from RCLK that can be coupled from TSEL through to
Figure 6. External Component Diagram
40.2 W 1%
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Jitter Tolerance Definition and Test The Receive Timing—Start of Reception Clock Acqui- sition w aveform diagram shows the internal timing rela- tionships implemented for decoding Manchester data in the Am7992B. The Am7992B utilizes a clock capture circuit to align its internal data strobe with an incoming bit stream. The clock acquisition circuitry requires four valid bits with the values 1010. Clock is phase locked to the negative transition at BCC of the second “0” in thepattern. Since data is strobed at 1/4 bit time, Manchester tran- sitions that shift from their nominal placement through 1/4 bit time will result in improperly decoded data. For IEEE 802.3/Ethernet, this results in the loss of a mes- sage. With this as the criterion for an error, a definition of “jitter handling” is: That peak deviation from nominal input transition approaching or crossing 1/4 bit cell position for which the Am7992B will properly decode data. Four events of signal are needed to adequately test the ability of the Am7992B to decode data properly from the Manchester bit stream. For each of the four events, two time points within a received message are tested (See Input Jitter Timing W aveforms): 1. Jitter tolerance at clock acquisition, the measure of clock capture (case 1–4). 2. Jitter tolerance within a message after the analogue PLL has reduced clock acquisition error to a mini- m um (case 5–8). The four events to test are shown in the Input Jitter Timing W aveform diagram. They are: 1. BCC jitter for a 01-bit pattern 2. BCC jitter for a 10-bit pattern 3. BCB jitter for an 11-bit pattern 4. BCB jitter for an X0-bit pattern The test signals utilized to jitter the input data are arti- ficial in that they may not be realizable on networks (ex- amples are cases 2, 3, and 4 at clock acquisition). H ow ever, each pattern relates to setup and hold time measurements for the data decode register (Figure 5). Receive+ and Receive– are driven with the inputs shown to produce the zero crossing distortion at the dif- ferential inputs for the applicable test. Cases 4 and 8 require only a single zero to implement when tested at the end of message. Levels used to test jitter are within the common-mode and differential-mode ranges of the receive inputs and also are available from automatic test equipment. It is assumed that the incoming message is asynchronous with the local TCLK frequency for the Am7992B. This ensures that proper clock acquisition has been estab- lished with random phase and frequency error in in- coming messages. An additional condition placed on the jitter tolerance test is that it m ust meet all test re- quirements within 10 ms after power is applied. This forces the Am7992B crystal oscillator to start and lock the analog PLL to within acceptable limits for receiving from a cold start. Case 1 of the test corresponds to the expected Manchester data at clock acquisition, and average val- ues for clock leading jitter tolerance are 21.5 ns. For cases 5 through 8, average values are 24.4 ns. Cases 5 through 8 are jittered at bit times 55 or 56 as applica- ble. The Am7992 B, then, has on average 0.6 ns static phase error for the noise-free case.
Figure 7. Typical ETHERNET Node
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DC Voltage Applied to Outputs –0.5 V to V CC Max. . . DC Input Voltage Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (T Operating ranges define those limits between which the func- tionality of the device is guaranteed.
DC CHARACTERISTICS over operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage RX, IOH = –1.0 mA, VCC = Min 2.4 V RENA, CLSN, TCLK, RCLK VOL Output LOW Voltage IOL = 16 mA, VCC = Min 0.5 V RCLK, TSEL, TCLK, RENA, RX, CLSN IOL = 1 mA, VCC = Min 0.4 V VOD Differential Output Voltage TX+ > TX– for VO R L = 78 W 550 770 mV (Transmit+) – (Transmit–) TX+ < TX– for VO –550 –770 mV VOD OFF Transmit Differential Output Idle Voltage VCC = Min, RL = 78 W (Note 1) –20 20 mV IOD OFF Transmit Differential Output Idle Current TSEL = HIGH (Note 2) –0.5 0.5 mA VCMT Transmit Output Common-Mode Voltage R L = 78 W , VCC = Min 0 5 V VODI Transmit Differential Output Voltage (Note 1) 20 mV VIH Input HIGH Voltage TX, TENA 2.0 V IIH Input HIGH Current TX, TENA, TEST VCC = Max, VIN = 2.7 V +50 mA VIL Input LOW Current TX, TENA 0.8 V IIL Input LOW Current TX, TENA, TEST VCC = Max, VIN = 0.4 V –400 mA VIRD Differential Input Threshold (Receive Data) VCM = 0 V, (Note 4) Ceramic Package –35 +35 mV Plastic Package –65 +65 mV V IRVD Differential Mode Input Voltage Range (Note 3) –1.5 +1.5 V (Receive –/Collision –) VIRVC Receive – and Collision – Common (Note 2) 0 5.5 V Mode Voltage VIDC Differential Input Threshold to Detect Carrier VCM = 0 V (Note 4) –175 –275 mV ICC Power Supply Current VCC = Max (Note 5) 180 mA VIB Input Breakdown Voltage (TX, TENA, TEST) II = 1 mA, VCC = Max 5.5 V VIC Input Clamp Voltage IIN = –18 mA, VCC = Min –1.2 V VODP Undershoot Voltage on Transmit (Note 3) –100 mV Return to Zero (End of Message) ISC Short Circuit Current VCC = Max (Note 6) –40 –150 mA RCLK, RX, TCLK, CLSN, RENA R IDF Differential Input Resistance VCC = 0 to Max (Note 3) 6 kW R ICM Common Mode Input Resistance VCC = 0 to Max (Note 3) 1.5 kW VICM Receive and Collision Input Bias Voltage IIN = 0, VCC = Max 1.5 4.2 V IILD Receive and Collision Input LOW Current VIN = –1 V, VCC = Max –1.64 mA IIHD Receive and Collision Input HIGH Current VIN = 6 V, VCC = Min +1.10 mA IIHZ Receive and Collision Input HIGH VCC = 0, VIN = +6 V 1.86 mA Current Power Off IIHX Oscillator (X1) Input HIGH Current VIN = 2.4 V, VCC = Max +800 mA IILX Oscillator (X1) Input LOW Current VIN = 0.4 V, VCC = Max –1.2 mA VIHX Oscillator (X1) Input HIGH Voltage (Note 3) 2.0 V VILX Oscillator (X1) Input LOW Voltage (Note 3) 0.8 V Com’l Note: See notes following Switching Characteristics table.
14 Am7992B
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified (Note 8) (Note 4) (Note 4) No. Parameters Description Test Conditions Min Max Unit Receiver Specification 1 tRCT RCLK Cycle Time 85 118 ns 2 tRCH RCLK HIGH Time 38 ns 3 tRCL RCLK LOW Time 38 ns 4 tRCR RCLK Rise Time 8 ns 5 tRCF RCLK Fall Time 8 ns 6 tRDR RX Rise Time 8 ns 7 tRDF RX Fall Time 8 ns 8 tRDH RX Hold Time (RCLK › to RX Change) 5 ns 9 tRDS RX Prop Delay (RCLK › to RX Stable) 25 ns 10 tDPH RENA Turn-On Delay (VIDC Max on 80 ns Receive – to RENAH ) 11 tDPO RENA Turn-On Delay (VIDC Min on (Note 9) 300 ns Receive – to RENAL) 12 tDPL RENA LOW Time (Note 10) 120 ns 13 tRPWR Receive – Input Pulse Width to Reject 20 ns 14 tRPWO Receive – Input Pulse Width to Turn-On 45 ns 15 tRLT Decoder Acquisition Time 450 ns 16 tREDH RENA Hold Time (RCLK › to RENAL) 40 80 ns 17 tRPWN Receive – Input Pulse Width to 165 ns Not Turn-Off INTCARR Collision Specification 18 tCPWR Collision – Input Pulse Width to Not 10 ns Turn-On CLSN (|Input| > |VIDC Min|) 19 tCPWO Collision – Input Pulse Width to Turn-On 26 ns CLSN (|Input| > |VIDC Max|) 20 tCPWE Collision – Input Pulse Width to Turn-Off 160 ns CLSN (|Input| > |VIDC Max|) 21 tCPWN Collision – Input Pulse Width to Not 80 ns Turn-Off CLSN (|Input| < |VIDC Max|) 22 tCPH CLSN Turn-On Delay (VIDC Max on 50 ns Collision – to CLSNH ) 23 tCPO CLSN Turn-Off Delay (VIDC Max on 160 ns Collision – to CLSNL)
SWITCHING CHARACTERISTICS (continued) *Min = 4.5 V, Max = 5.5 V, TOSC = 50 ns; in production test, all differential input test conditions are done single-ended, non-VIRD levels are forces on DUT for waveform swing (levels chosen are due to tester limitations) and a distortion-free preamble is applied to Receive– inputs. Notes: 1. Tested but to values in excess of limits. Test accuracy not sufficient to allow screening guardbands. 2. Correlated to other tested parameter: IOD OFF = VOD OFF/RL. 3. Not tested. 4. Test done by monitoring output functionally. 5. Receive, Collision and Transmit functions are inactive: X1 driven by 20 MHz. 6. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 7. TCLK changes state on X1 rising edge, but initial state of TCLK is not defined. When TENA is High, TX data is Manchester encoded on the falling edge of X1 after the rising edge of TCLK. 8. Assumes 50 pF capacitance loading on RCLK and RX. 9. Test is done only for last BIT = 1, which is worst case. 10. Test done from 0.8 V of falling to 2.0 V of rising edge. 11. Test correlated to TTCH . 12. Measured from 50% point of X1 driving the input in production test. No. Parameters Description Test Conditions Min Max Unit Transmitter Specification 24 tTCL TCLK LOW Time (Note 11) 45 ns 25 tTCH TCLK HIGH Time 45 ns 26 tTCR TCLK Rise Time 8 ns 27 tTCF TCLK Rise Time 8 ns 28 tTDS , tTES TX and TENA Setup Time to TCLK 5 ns 29 tTDH , tTEH TX and TENA Hold Time to TCLK 5 ns 30 tTOCE Transmit – Output, (Bit Cell Center to Edge) 49.5 50.5 ns 31 tOD TCLK HIGH to Transmit – Output 100 ns 32 tTOR Transmit – Output Rise Time 4 ns 33 tTOF Transmit – Output Fall Time 4 ns 34 tXTCH X1 to TCLK Propagation Delay for HIGH 5 18 ns 35 tXTCL X1 to TCLK Propagation Delay for LOW 5 18 ns 36 tEJ1 Clock Acquisition Jitter Tolerance VCC = 5.0 V (Note 1) 16 21.5 ns 37 tEJ51 Jitter Tolerance After 50 Bit Times VCC = 5.0 V (Note 1) 19 24.4 ns (Note 1) 20% – 80% (Notes 7 & 12)
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KEY TO SWITCHING WAVEFORMS KS000010 Must be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS
(Note A)(Note E) Bit Cell 1 Bit Cell 2 Bit Cell 3 Bit Cell 4 Bit Cell 5 BCC BCB BCC BCB BCC BC B BCC BCB BCC BCB (Note D) (Note B) (Note C) (Note F) Receive– (Measured Differentially) INTCARR RENA VCO Enable VCO INTRCLK RCK Enable RCLK RX INTPLLCLK 03378I-12 Notes: A. Minimum Width > 45 ns. B. RCLK = INTRCLK when TEST LOW. C. RX undefined until bit time 5 (1st decoded bit). D. Oscillator Interrupt may occur at 2nd INTRCLK after Bit 2 Clock Transition. E. Timing Diagram does not include Internal Propagation Delays. F. First valid data at RX (Bit 5). Receive Timing – Start of Reception Clock Acquisition
18 Am7992B
Bit (N – 1) Bit N BCC BCB BCC BCB (Note A) (Note B) 11 12 Bit (N – 1) Bit N Receive+ (Measured Differentially) INTCARR RENA VCO Enable VCO INTRCLK RCK Enable RCLK RX PLL CLK 03378I-13 Notes: A. INTCARR deasserts 1.55 bit times after last Receive– Rising Edge. B. Start of Next Packet. Receive Timing – End of Reception (Last Bit = 0)
Bit (N – 1) Bit N (Note A) Bit (N – 1) Bit N BCC BCB Receive– (Measured Differentially) INTCARR VCO Enable VCO INTRCLK RCK Enable RCLK RX PLL CLK RENA Note: A. INTCARR deasserts 1.55 bit times after last Receive– Rising Edge. 03378I-14 BCC Receive Timing – End of Reception (Last Bit = 1)
20 Am7992B
(Note A) TCLK TENA TSEL Transmit+ Transmit– Transmit– (Measured Differentially) TX 03378I-15 VH VH VL VL (Note B) (Note C) (Note C) (Note B) Notes: A. X1 20 MHz Sine Wave from Crystal Oscillator or driven with X1 driven from External Source Waveform. B. TSEL connected as shown in Figure 2B. For Figure 2A, Transmit+ is HIGH when TENA is LOW. C. When Idle Transmit– Zero Differential is 1/2 (VH + VL). Transmit Timing – Start of Packet
0.5 VO at 2 ms
Bit (N – 2) Bit (N – 1) Bit N BCC BCB BCC BCB BCC BCB TCLK TENA TSEL CASE 1 TX (Last Bit = 0) Transmit+ Transmit– Transmit– (Measured Differentially) CASE 2 TX (Last Bit = 1) Transmit+ Transmit– VO VO Transmit– (Measured Differentially) Transmit Timing – End of Transmission* *TSEL Components (see Figure 2B). See Typical Performance Curve for Response at End of Transmission with Inductive Loads.
22 Am7992B
2.0 V .8 V VIDC Max VIDC Max 0 V Collision Presence– CLSN 03378I-17 Collision Timing 33 32
2 V2 V
80% 80% 50% 20% 20% TCLK TENA 03378I-18 Transmit– (Measured Differentially) Transmit Timing (at start of packet)
2.0 V Receive– (Measured Differentially) 03378I-19
0 V0 V
VIRVD +1.5 V VIRVD –1.5 V VIDC Min (–175 mV) VIDC Max (–275 mV) RENA 0 V Receive– Input Pulse Width Timing 2.0 V Collision– (Measured Differentially) 03378I-20
0 V 0 V0 V
VIRVD +1.5 V VIRVD –1.5 V VIDC Min (–175 mV) VIDC Max (–275 mV) CLSN Collision– Input Pulse Width Timing 0.8 V 0.2 V 0.8 V
2.0 VRCLK
24 Am7992B
2.0 V 0.8 V 2.0 0.8 2.0 0.8 0.8 V 0.8 V 0.8 V 2.0 V 25 24 26 27 28 29 TCLK TX TENA TCLK and TX Timing TOSC 0.8 2.0 1.51.51.5 1.5 Driving Input TCLK Transmit+, Transmit– (Note A) tR * tF*tHIGH * tLOW * 0.8 2.0 35 34 ‘A’ ‘B’ 0 V BCC (Bit Cell Center) BCB (Bit Cell Boundary) 03378I-23 Note: A. Encode Manchester clock transition (BCC) at Point ‘A’ and bit cell edge (BCB) at point ‘B’. *See Specification for External TTL Level in Functional Description section. X1 Driven from External Source
4.5 V 1.5 V 3 V +4.5 V 1.5 V –1.5 V Receive+ Receive– Receive– RX +3 V +4.5 V +1.5 V –1.5 V +1.5 V –4.5 V Receive+ Receive– Receive– RX +3 V +4.5 V +1.5 V –1.5 V +1.5 V Receive+ Receive– Receive– RX +4.5 V +1.5 V +3 V +1.5 V –1.5 V Receive+ Receive– Receive– RX 55 56 57 58 BCC BCC BCC BCC BCC BCC BCC BCC BCB 1/4 Bit Cell 0 V 4.5 V Strobe RX BCB Strobe RX Strobe RX Strobe RX 1/4 Bit Cell BCB 03378I-24 (Note A) (Note B) (Note C) (Note D) Notes: A. Case 1, 5 Data Bit Pattern 0, 1 Rising clock edge moved toward 1/4 bit cell RCLK data strobe. Case 1 uses bit 5, Case 5 uses bit 55. B. Case 2, 6 Data Bit Pattern 1, 0 Falling clock edge moved toward 1/4 bit cell RCLK data strobe. Case 2 uses bit 6, Case 6 uses bit 56. C. Case 3, 7 Data Bit Pattern 1, 1 Falling bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 3 uses bit 6, Case 7 uses bit 56. D. Case 4, 8 Data Bit Pattern X, 0 Rising bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 4 uses bit 5, Case 8 uses bit 55. tEJI tEJ51 D tEJI tEJ51 C tEJI tEJ51 B A tEJI tEJ51 Input Jitter Timing
26 Am7992B
–100 03378I-25Time (ms) Differential Output Voltage (VO ) (mV) End of Transmission – Differential Output Voltage* Notes: R = 78 W * R = 78 W L = 95 mH R = 78 W L = 75 mH R = 78 W L = 60 mH LR L TestR Test 60 mH Am7992B 75 mH NOM. AUI VO80.4 Am7996 75 mH NOM. Am7992B 80.4 VO Am7996 95 mH 1. 802.3 Test Load: 2. 802.3 10BASE5 Network Connection: 3. 802.3 10BASE2 Network Connection: *Equivalent Load: 03378I-26
Transmit– R L = 78 W Transmit+ 03378I-27 03378I-28 DUT 03378I-29 DC Voltage A. Test Load for RX, RENA, RCLK, TCLK, CLSN B. Transmit– Output C. Receive– and Collision– Input