AM7945

AM7945 AMD | Alldatasheet

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Publication# 18408 Rev: D Amendment: /0 Issue Date: October 1999 Am7945 Subscriber Line Interface Circuit DISTINCTIVE CHARACTERISTICS I Programmable constant-current feed I Current gain = 200 I Programmable loop-detect threshold I Low power Standby state I Ground-key detector I Tip Open state for ground-start lines I –19 V to –56.5 V battery operation I On-chip Thermal Management (TMG) feature I Two-wire impedance set by single external impedance I On-hook transmission I On-chip ring relay driver and relay snubber circuit I Ideal for low cost PABX and key telephone systems BLOCK DIAGRAM VCC VEE AGND/DGND RSN VTX RD RDC CAS DET Two-Wire Interface HPA HPB DA DB BGND VBAT A(TIP) B(RING) TMG Ground-Key Detector Signal Transmission Off-Hook Detector Power-Feed Controller Ring-Trip Detector RINGOUT Ring Relay Driver Input Decoder and Control

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Note: * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. Am7945 J C TEMPERATURE RANGE C = Commercial (0°C to 70°C)* PACKAGE TYPE DEVICE NUMBER/DESCRIPTION Am7945 Subscriber Line Interface Circuit Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations, and to obtain additional data on AMD’s standard military grade products. J = 32-pin Plastic Leaded Chip Carrier (PL 032) Valid Combinations Am7945 JC

Notes: 1. Pin 1 is marked for orientation. 2. TP is a thermal conduction pin tied to substrate. 3. NC = No Connect NC BGND NC B(RING) A(TIP) DB NC NC AGND/DGND VCC CAS RDC

Description

A(TIP) Output Output of A(TIP) power amplifier BGND Gnd Battery (power) ground B(RING) Output Output of B(RING) power amplifier C3–C1 Input Decoder. TTL compatible. C3 is MSB and C1 is LSB. CAS Capacitor Anti-saturation pin for capacitor to filter reference voltage when operating in anti-saturation region. DA Input Ring-Trip Negative. Negative input to ring-trip comparator. DB Input Ring-Trip Positive. Positive input to ring-trip comparator. DET Output Switchhook Detector. When enabled, a logic Low indicates the selected detector is tripped. The detect condition is selected by the logic inputs (C3–C1, E0, E1). The output is open- collector with a built-in 15 kΩ pull-up resistor. Input Ground-Key Enable. A logic High enables DET. A logic Low disables DET (PLCC only). Input Ground-Key Enable. E1 = Low connects the ground-key or ring-trip detector to DET. E1 = High connects the off-hook or ring-trip detector to DET (PLCC only). HPA Capacitor High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor. HPB Capacitor High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor. RD Resistor Detect Resistor. Threshold modification and filter point for the off-hook detector. RDC Resistor DC Feed Resistor. Connection point for the DC feed current programming network. The other end of the network connects to the receiver summing node (RSN). VRDC is negative for normal polarity and positive for reverse polarity. RINGOUT Output Ring Relay Driver. Open-collector driver with emitter internally connected to BGND. RSN Input Receive Summing Node. The metallic current (both AC and DC) between A(TIP) and B(RING) is equal to 200 times the current into this pin. Networks that program receive gain, two-wire impedance, and feed resistance all connect to this node. TMG Thermal Management. Connect an external resistor between this pin and the VBAT pin to reduce on-chip power dissipation in the normal polarity, Active state only. See Table 2. TP Thermal Thermal pin. Connection for heat dissipation. Internally connected to substrate (QBAT). Leave as open circuit or connected to QBAT. In both cases, the TP pins can connect to an area of copper on the board to enhance heat dissipation. VBAT Battery Battery supply VCC Power +5 V power supply VEE Power –5 V power supply VTX Output Transmit Audio. This output is a unity gain version of the A(TIP) and B(RING) metallic voltage. VTX also sources the two-wire input impedance programming network.

With respect to AGND/DGND: VBAT A(TIP) or B(RING) with respect to BGND: Voltage on RINGOUT: DA and DB inputs C3–C1, E0, E1 Maximum power dissipation, TA = 85°C No heat sink (See note): Note: Thermal limiting circuitry on chip will shut down the cir- cuit at a junction temperature of about 165°C. The device should never be exposed to this temperature. Operation above 145°C junction temperature may degrade device reliability. See the SLIC Packaging Considerations for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices BGND with respect to The Operating Ranges define those limits over which the functionality of the device is guaranteed by production testing. * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of pro- duction units.

ELECTRICAL CHARACTERISTICS

The Am7945 device is tested under the following conditions unless otherwise noted: BAT = –48 V, VCC = +5 V, VEE = –5 V, RL = 900 Ω. The device is not tested in Polarity Reversal state. Test Conditions (See Note 1) Min Typ Max Unit Note Analog output (VTX) impedance Ω Analog output (VTX) offset 0°C to +70°C –40°C to +85°C –37 –40 +37 +40 mV Analog (RSN) input impedance 300 Hz to 3.4 kHz Ω Longitudinal impedance at A or B Ω Overload level 4-wire and 2-wire, Active state –2.5 +2.5 Vpk On hook, RLAC = 900 Ω, Active or OHT state 0.95 Vrms Transmission Performance 2-wire return loss (See Test Circuit D) 200 to 3.4 kHz dB 4, 8 Longitudinal Balance (2-Wire and 4-Wire, See Test Circuit C); RL = 740 Ω at BAT = 48 V Longitudinal to metallic L-T, L-4 normal polarity

200 Hz to 1 kHz

0°C to +70°C –40°C to +85°C dB 1 kHz to 3.4 kHz 0°C to +70°C –40°C to +85°C Longitudinal signal generation 4-L

300 Hz to 800 Hz, normal polarity

Longitudinal current per pin Active state and OHT state mArms Insertion Loss (2- to 4-Wire and 4- to 2-Wire, See Test Circuits A and B) BAT = –48 V, RL = 900 Ω Gain accuracy 0 dBm, 1 kHz 0°C to +70°C –40°C to +85°C –0.15 –0.20 +0.15 +0.20 dB Gain accuracy, OHT state –10 dBm, On hook, RLAC = 900 Ω –1.0 +1.0 Variation with frequency 300 to 3.4 kHz, relative to 1 kHz 0°C to +70°C –40°C to +85°C –0.10 –0.15 +0.10 +0.15 Gain tracking +7 dBm to –55 dBm, reference 0 dBm 0°C to +70°C –40°C to +85°C –0.10 –0.15 +0.10 +0.15 Balance Return Signal (4- to 4-Wire, See Test Circuit B) BAT = –48 V, RL = 900 Ω Gain accuracy 0 dBm, 1 kHz 0°C to +70°C –40°C to +85°C –0.15 –0.20 +0.15 +0.20 dB Variation with frequency 300 to 3.4 kHz, relative to 1 kHz 0°C to +70°C –40°C to +85°C –0.10 –0.15 +0.10 +0.15 Gain tracking +3 dBm to –55 dBm, reference 0 dBm 0°C to +70°C –40°C to +85°C –0.10 –0.15 +0.10 +0.15 3, 4 Group delay f = 1 kHz µs 4, 8 Total Harmonic Distortion (2- to 4-Wire or 4- to 2-Wire, See Test Circuits A and B) BAT = –48 V, RL = 900 Ω Harmonic distortion 300 Hz to 3.4 kHz 2-wire level = 0 dBm 2-wire level = +7 dBm –64 –55 –50 –40 dB

ELECTRICAL CHARACTERISTICS (continued) Test Conditions (See Note 1) Min Typ Max Unit Note Idle Channel Noise (2-Wire and 4-Wire) C-message weighted 2-wire, 0°C to +70°C –40°C to +85°C +10 +12 dBrnc 4-wire, 0°C to +70°C –40°C to +85°C +10 +12 Psophometric weighted 2-wire, 0°C to +70°C –40°C to +85°C –83 –83 –78 dBmp 4-wire, 0°C to +70°C –40°C to +85°C –83 –83 –75 Line Characteristics, Active State (See Figure 1) Short loops, Active state BAT = –48 V, RLDC = 600 Ω 24.7 29.3 mA Long loops, Active state BAT = –48 V, RLDC = 1.9 kΩ 17.5 OHT state BAT = –48 V, RLDC = 600 Ω 15.5 20.5 Standby state TA = 25°C 0.7IL IL 1.3IL RL = 600 Ω, BAT = –48 V TA = 70°C 15.0 17.4 Loop current Tip Open state, RL = 0 Ω 100 µA Disconnect state, RL = 0 Ω 100 Tip Open state, Bwire to GND mA Tip Open state, Bwire = BAT + 6 V ILLIM (ITIP + IRING) Tip and ring shorted to GND 100 130 Ground-start signaling (tip voltage) Active state, RTIP to –48 V = 7.0 kΩ RRING to GND = 100 kΩ –7.5 –5.0 V Open circuit voltage Active and OHT state, BAT = –48 V 40.5 42.0 Power Dissipation, BAT = –48 V On hook, Open Circuit state 100 mW On hook, OHT state 120 210 On hook, Active state RTMG = Open RTMG = 1700 Ω 160 195 230 280 On hook, Standby state 100 Off hook, OHT state RL = 300 Ω, RTMG = ∞, BAT = –48 V 735 1100 Off hook, Active state RL = 300 Ω, RTMG = ∞, BAT = –48 V RL = 300 Ω, RTMG = ∞ 1.25 0.57 1.60 0.85 W Off hook, Standby state RL = 600 Ω, TA = 25°C 0.68 1.0 IL VBAT 3 V RL 1800

Supply Currents, BAT = –48 V VCC, On-hook supply current Open Circuit state OHT state Standby state Active state 1.7 4.9 2.2 6.3 2.5 7.5 3.0 8.5 mA VEE, On-hook supply current Open Circuit state OHT state Standby state Active state 0.7 2.0 0.77 2.1 2.0 3.5 2.0 5.0 VBAT, On-hook supply current Open Circuit state OHT state Standby state Active state 0.18 1.9 0.45 4.2 1.0 4.7 1.5 5.7 Power-Supply Rejection Ratio (VRIPPLE = 50 mVrms), Active Normal State VCC 50 Hz to 3.4 kHz dB VEE 50 Hz to 3.4 kHz VBAT 50 Hz to 3.4 kHz Effective internal resistance CAS pin to GND 170 255 kΩ RFI rejection 100 kHz to 30 MHz (See Figure E) 1.0 mVrms Off-Hook Detector Current threshold –12 +12 Ground-Key Detector Thresholds, Active State, BAT = –48 V Ground-key resistance threshold B(RING) to GND 2.0 5.0 10.0 kΩ Ground-key current threshold B(RING) to GND mA Ring-Trip Detector Input Bias current –0.5 –0.05 µA Offset voltage Source resistance = 2 MΩ –50 +50 mV Logic Inputs (C3–C1, E0, E1) Input High voltage 2.0 V Input Low voltage 0.8 Input High current All inputs except C3 and E1 –75 µA Input C3 –75 200 Input E1 –75 Input Low current –0.4 mA Logic Output (DET) Output Low voltage IOUT = 0.8 mA 0.4 V Output High voltage IOUT = –0.1 mA 2.4 ELECTRICAL CHARACTERISTICS (continued) Test Conditions (See Note 1) Min Typ Max Unit Note IDET 375 RD

(32-Pin PLCC only) Relay Driver Output (RINGOUT) On voltage 35 mA sink +0.25 +0.4 V Off leakage VOH = +5 V 100 µA Zener breakover 100 µA 7.2 V Zener On voltage 30 mA Symbol Parameter Test Conditions Temperature Ranges Min Typ Max Unit Note tgkde E1 Low to DET High (E0 = 1) E1 Low to DET Low (E0 = 1) Ground-Key Detect state RL open, RG connected (See Figure H) 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 3.8 4.0 1.1 1.6 µs tgkdd E0 High to DET Low (E1 = 0) 0°C to +70°C –40°C to +85°C 1.1 1.6 tgkd0 E0 Low to DET High (E1 = 0) 0°C to +70°C –40°C to +85°C 3.8 4.0 tshde E1 High to DET Low (E0 = 1) E1 High to DET High (E0 = 1) Switchhook Detect state RL = 600 Ω, RG open (See Figure G) 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 1.2 1.7 3.8 4.0 tshdd E0 High to DET Low (E1 = 1) 0°C to +70°C –40°C to +85°C 1.1 1.6 tshd0 E0 Low to DET High (E1 = 1) 0°C to +70°C –40°C to +85°C 3.8 4.0 ELECTRICAL CHARACTERISTICS (continued) Test Conditions (See Note 1) Min Typ Max Unit Note BGND RINGOUT

Notes: 1. Unless otherwise noted, test conditions are VCC = +5 V, VEE = –5 V, CHP = 0.33 µF, RDC1 = RDC2 = 9.26 kΩ, CDC = 0.33 µF, RD = 35.4 kΩ, CCAS = 0.33 µF, no fuse resistors, BAT = –48 V, RL = 900 Ω, and RTMG = 1700 Ω. 2. a. Overload level is defined when THD = 1%. b. Overload level is defined when THD = 1.5% 3. Balance return signal is the signal generated at VTX by VRX. This specification assumes the two-wire AC load impedance matches the programmed impedance. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. This parameter is tested at 1 kHz with a termination impedance of 900 Ω and an RL of 600 Ω in production. Performance at other frequencies is guaranteed by characterization. 6. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only. 7. Assumes the following ZT networks: 8. Group delay can be considerably reduced by using a ZT network such as that shown in Note 7 above. The network reduces the group delay to less than 2 µs. The effect of group delay on the linecard performance may be compensated for by using the QSLAC™ or DSLAC™ device. DET tgkde DET tshdd Note: All delays measured at 1.4 V level. E1 to DET E0 to DET tshde tgkde tshde tshd0 tgkdd tgkd0 VTX RSN 90 kΩ 150 pF 90 kΩ (900 Ω): VTX RSN 60 kΩ 150 pF 60 kΩ (600 Ω):

Note: E0 High enables DET. Table 1. SLIC Decoding DET Output State 2-Wire Status E1 = 1 E1 = 0 Open Circuit Ring trip Ring trip Ringing Ring trip Ring trip Active Loop detector Ground key On-Hook TX (OHT) Loop detector Ground key Tip Open Loop detector Ground key Standby Loop detector Ground key Reserved Reserved Table 2. User-Programmable Components ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain. RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1 and RDC2 are approximately equal. ILOOP is the desired loop current in the constant-current region. RD and CD form the network connected from RD to –5 V and IT is the threshold current between on hook and off hook. OHT loop current (constant-current region). CCAS is the regulator filter capacitor and fc is the desired filter cutoff frequency. Thermal Management Equations (Normal Active and Tip Open States) RTMG is connected from TMG to VBAT and is used to limit power dissipation within the SLIC in Normal Active and Tip Open states only. Power dissipated in the TMG resistor, RTMG, during Active and Tip Open states. Power dissipated in the SLIC while in Active and Tip Open states. ZT

200 Z2WIN

1.5 ms RDC1 RDC2 RDC1 RDC2 RD 375 IT CD 0.5 ms RD IOHT 500 V 0.66 RDC1 RDC2 CCAS 3.4 105πfc RTMG VBAT 6 V ILOOP PRTMG VBAT 6 V IL RL RTMG PSLIC VBAT IL PRTMG RL IL 0.12 W

VBAT = –51.3 V VBAT = –47.3 V RDC1 + RDC2 = RDC = 18.52 kΩ Active state OHT state Notes: 1. Constant-current region: Active state: OHT state: 2. Anti-sat (battery tracking) turn-on: 3. Open circuit voltage: 4. Anti-sat (battery tracking) region: IL 500 RDC IL 3-- 500 RDC VAB

1.017 VBAT

10.7 VAB 6.3 VAB 6.3 IL RDC 120 a. VA–VB (VAB) Voltage vs. Loop Current (Typical)

DC FEED CHARACTERISTICS (continued) RDC1 + RDC2 = RDC = 18.52 kΩ VBAT = –47.3 V b. Loop Current vs. Load Resistance (Typical) 1000 2000 3000 4000 5000 6000 Loop Current (mA) Load Resistance (Ω) A B IL RSN RDC RDC1 RDC2 CDC SLIC RL a b Feed current programmed by RDC1 and RDC2 c. Feed Programming Figure 1. DC Feed Characteristics

IL2-4 = 20 log (VTX / VAB) A. Two- to Four-Wire Insertion Loss VAB RL RL A(TIP) B(RING) VTX RSN AGND SLIC B. Four- to Two-Wire Insertion Loss and Balance Return Signal RT RRX VL VAB A(TIP) B(RING) VTX RSN AGND SLIC VL S2 Open, S1 Closed L-T Long. Bal. = 20 log (VAB / VL) L-4 Long. Bal. = 20 log (VTX / VL) S2 Closed, S1 Open 4-L Long. Sig. Gen. = 20 log (VL / VRX) C. Longitudinal Balance RT RRX VRX RL RL VL C ωC << RL Note: ZD is the desired impedance (e.g., the characteristic impedance of the line). RL = –20 log (2 VM / VS) VM A(TIP) B(RING) VTX RSN AGND SLIC RT1 RRX RT2 ZD R R ZIN CT1 VS D. Two-Wire Return Loss Test Circuit VAB RL RSN AGND VTX VRX RRX SLIC B(RING) A(TIP) RT IL4-2 = 20 log (VAB / VRX) BRS = 20 log (VTX / VRX)

TEST CIRCUITS (continued) E. RFI Test Circuit HF GEN VTX B(RING) A(TIP) CAX 33 nF CBX 33 nF RF1 RF2 50 Ω 50 Ω 200 Ω 200 Ω 50 Ω SLIC F. Loop-Detector Switching VCC A(TIP) B(RING) DET 6.2 kΩ RL = 600 Ω 15 pF A(TIP) B(RING) 2 kΩ at VBAT = –48 V RG G. Ground-Key Switching

1.5 Vrms

80% Amplitude Modulated 100 kHz to 30 MHz under test

TEST CIRCUITS (continued) BATTERY GROUND ANALOG GROUND DIGITAL GROUND VCC VEE RD RD VTX AGND/ DGND RSN RRX RDC2 RDC1 CDC RT RDC –5 V +5 V VBAT DET BGND RINGOUT HPB CHP A(TIP) DB DA A(TIP) B(RING) CAS CCAS 2.2 nF 2.2 nF VTX VRX H. Am7945 Test Circuit HPA B(RING) BAT TMG RTMG 1700 Ω

Minor changes were made to the data sheet style and format to conform to AMD standards. Revision B to Revision C In the Pin Description table, inserted/changed TP pin description to: “Thermal pin. Connection for heat dissipa- tion. Internally connected to substrate (QBAT). Leave as open circuit or connected to QBAT. In both cases, the TP pins can connect to an area of copper on the board to enhance heat dissipation.” Revision C to Revision D Deleted information on the Ceramic DIP and Plastic DIP packages. The PL032 package was added to the new Physical Dimension section. Updated the Pin Description table to correct inconsistencies. .050 REF. .026 .032 TOP VIEW Pin 1 I.D. .485 .495 .447 .453 .585 .595 .547 .553 16-038FPO-5 PL 032 DA79 6-28-94 ae SIDE VIEW SEATING PLANE .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 REF. .490 .530

The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci- fications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any in- tellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. © 1999 Advanced Micro Devices, Inc. All rights reserved. Trademarks AMD, the AMD logo, and combinations thereof, and DSLAC and QSLAC are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.