AM7905A

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Am7905A _ ; Advanced Subscriber Line Audio-Processing Micro Circuit (SLAC™) Device Devices DISTINCTIVE CHARACTERISTICS = Combination CODEC and Filter 1 4.096-MHz, 64-channel expanded mode ™@ No trimming or adjustments required operation ™ Uses digital signal processing @ Built-in test modes

1 Six user-programmable digital filters 1 Microprocessor-compatible Serial Interface

Dynamic Time Slot assignment ™@ Control interface to SLIC Only two external components (non-precision) © Low standby power = Dual PCM ports 1 Selectable j1-law or A-law @ 24-pin DIPS GENERAL DESCRIPTION The Subscriber Line Audio-Processing Circuit(SLAC™) The transmit section contains an anti-aliasing filter, an performs the codec and filtering functions necessary in interpolative A/D converter and a digital signal proces- digital voice switching machines. In this application, the sor. The analog signals received are converted and digi- SLAC processes voiceband analog signals into Pulse- _tally processed to generate either 8-bit u-law or A-law Code Modulated (PCM) outputs and processes PCM —_codes. Either one of two output ports may be selected inputs into analog outputs. The SLAC’s performance —_for PCM data transmission. is compatible with applicable AT&T® and CCITT specifi- cations. The device consists of three main sections: transmit processor, receive processor, and control logic. BLOCK DIAGRAM CAP, CAP, 9 90 y © TSCA N Pre- Transmit Signal Digital Output © TSCB ° Filter AD [> “Processor nm Compressor ~ Register © DXA _ © DXB FS MCLK © ) ° Control, cso Timing and ° OV DCLK O Interface ° O-V Dio O ° © Analog Ground t ° © Digital Ground Vout Wi Receive Signal 7 Digital W Input © DRA ° DIA KI “Processor KK] expander KQ—4 Register O ORB 07004B-01 el M™ 0257527 OO35b42 7T2 mm

GENERAL DESCRIPTION (continued) The receive section contains a digital signal processor —_The control /O provides a microprocessor-compatible and a D/A converter. Either 8-bit y-law or A-law codes _serial interface and allows the user bidirectional access are received, processed and converted to analog sig- to many programmable features and the capability to nals. Either one of two input ports may be selected for compietely control the operation of the device via a reception of PCM data. comprehensive set of commands. CONNECTION DIAGRAMS Top View 24-Pin DIP Vee TL1¢ 2401} Voc rs 2 23(7] eLk c2[)3 227] os era 21[) pio Vour C] 5 2017] ocik acno (J 6 19[-) pGND Va 7 18) TSCB cap, [8 7 TStK cap, C] 9 16[-) DXA cs J 10 157] ox cM 14{-] RA c3 Cf 2 13,7) ORB 28-Pin PLCC $ x Geog se@e2e83 318 Pi fi fi fifi fit 43 2 1 28 27 26 er Os . 251] Do Vor O16 24 1 RSRAVD acnp []7 23 [] pDcLk Vw O18 22 0 ocNo cap, (9 a1 TSB cap, [10 20[) TStA es Qt 19 L) RsRVO 12 13 14 16 16 17 18 CW UoUUdOUC 88 2222s 68@886 Note: Pin 1 is marked for orientation. 2-40 Am7905A Data Sheet ma o25752? 0035643 b39

1 Ves MCLK 23

24 Vee

8 CAP,

9 CAP,

7 Vin

6 AGND

5 Vour Fs 2

19 DGND

" ca 12 c3 TSCA 17 3 ce DXB 15 4 ct TSB Dp 18 DRA 14 22 —q tS DRB 13

20 DcLK Do 2

@ 02 5752? oo3s5Kyy S75 @

ORDERING INFORMATION

AMD® standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM7905A P c B tL OPTIONAL PROCESSING Blank = Standard Processing ‘TEMPERATURE RANGE C = Commercial (0 to +70°C) PACKAGE TYPE P= 24-Pin Plastic DIP (PD 024) D. = 24-Pin Ceramic DIP (CD 024) J = 28-Pin Plastic Leaded Chip Carrier (PLCC 028) SPEED OPTION Not Applicable DEVICE NUMBER/DESCRIPTION ‘Am7905A Subscriber Line Audio-Processing Circuit (SLAC) Valid Combinations Valid Combinations Valid Combinations list configurations planned to AM7905A PG, DG, JC be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on AMD's standard military grade products. 2-42 Am7905A Data Sheet mo25752e7 0035645 401 mf

FINAL amo © PIN DESCRIPTIONS DXA, DXB PCM Outputs AGND ‘The transmit-PCM data is serially fed out to either the Analog ground. DXA or the DXB port. The port selection is under user program control. For both y-law and A-law, 8 bits are Cc5-C1 transmitted. The output is available every 125 us and Latched Outputs the data is shifted out in 2.048-MHz or 4.096-MHz The serial intertace may be used to write data to a regis- bursts. DXA and DXB are high impedance between ter whose outputs are brought out to C5-C1. These 5 bursts and also in the standby mode. lines are TTL-compatible and may be usedto controlthe operation of a SLIC or any other device associated with © FS the subscriber line. C5 is used as an output inthe Auto- Frame Sync zero Speedup Mode. The Frame Sync pulse input is an 8-kHz signal which identifies the beginning of a frame. The SLAC refer- CAP,, CAP; ences individual time slots with respect to the Frame ‘An external series resistor and capacitor are connected Sync pulse. The FS pulse must not be longer than 8- tothese pins. These components are partof the integra- __clock periods. tor in the A/D converter. The recommended values of these non-precision components are 1K ohm +5% and MCLK 2000 pF 220%. Master Clock The Master Clock is a 2.048- or 4,096-MHz +100 ppm cs clock input. MCLK is used by the digital signal Chip Select processors and by the PCM interface. Loss of MCLK The Chip Select input enables the device to either input ‘should be treated like a loss of power. or output control data. A level of -5 V on this input places the device in the Auto-zero Speedup Mode. TSCA, TSCB Time Siot Control DCLK The Time Slot Control outputs are open-drain outputs Data Clock and are normally High. TSCA is Low when PCM data is ‘The Data Clock input shifts control data either into orout _presentonthe DXA output and TSCB is Low when PCM of the SLAC. The maximum clock rate is 2.048 MHz. A _data is present on the DXB output. level of -5 V on this input forces the device into the Reset state. Veo -5-V power supply. Dio Data Input/Output Veo Control data is serially written and read via the Data —_45-V power supply. Input/Output port. The input and output rate is deter- mined by the Data Clock. Vin Analog Input DGND The analog input is applied to the transmit path of the Digital ground. SLAC. The signal is sampled, digitally processed and encoded for the PCM output. DRA, DRB PCM Inputs Vour The receive-PCM data is serially received from either © Analog Output the DRA or the DRB port. The port selection is under —_— The received-PCM data is digitally processed and con- user program control. For both y-law and A-law, 8 bits verted to an analog signal at the Vour pin. are received. The data is received in 2.048- or 4.096-MHz bursts. SLAC Products 2-43 M™@ 0257527 OOSSL4L 348 mw

FUNCTIONAL DESCRIPTION Transmit PCM Interface Devi ration The Transmit PCM interface receives either 8-bit evice Ope compressed i-law or A-law code from the digital com- General pressor. This code is loaded into the output register. The The Am7905A performs the codec and filter functions Transmit PCM interface logic (see Figure 4) controls associated with the four-wire section of the subscriber _the transmission of data onto the PCM highway through line circuitry in a digital switch. When used with the _the output port-selection circuitry and the Time Slot Con- ‘Am795XX Subscriber Line Interface Circuit (SLIC), the trol block. Pair provide a complete solution to the BORSCHT (Bat- berate " tery feed, Overvoltage protection, Ringing, Supervision, The Frame Sync (FS) pulse identifies the beginning Coding, Hybrid, and Tast) functions (cee Figure 1) of a Transmit frame and all channels (time slots) are 19, Hybrid, ) igure 1). referenced to it. The logic contains user-programmable The SLAC contains auto-zeroed A/D and D/Aconvert- Transmit Time Slot and Transmit Clock Slot registers. ers. A microprocessor-compatible interface is provided The Time Slot register is normally 5 bits wide and allows to program the device into a variety of modes. These —_up to thirty-two 8-bit channels (using MCLK = 2.048 operating modes include companded operation, MHz) in each frame. But in the expanded mode, 6 bits dynamic time-slot assignment, and PCM-port selection. may be programmed to give sixty-four 8-bit channels The SLAC samples the analog signal at the Va pinand (Using MCLK = 4.096 MHz) in each frame. The digitally processes It to produce either a companded _©*Panded mode bit becomes the sixth bit of the Time igtally mpal Slot register. If this bit is Low, one of channels 0 to 31 is law or A-law PCM code at the DXA or DXB output (see Y ' i i selected and if it is High, one of channels 32 to 64 is Figure 2). Conversely, it receives either a companded , 4 \\ 7 selected. This only applies it MCLK is 4.096 MHz. This u-law or A-law PCM code at the DRA or DRB input and : a 4 feature allows clock frequencies of 2.048 or 4.096 MHz digitally processes it to produce an analog output at the s . ° ina system, For u-law and A-law operation, 8 bits/chan- Vour pin. The processing is accomplished at the frame s iM on ‘ ean nel are output. The data is transmitted Most Significant rate (8 kHz), and the digital output/input is available for a natod’ Wiost Sign transmissionvreception every 125 Bit (MSB) first. The Clock Slot registers 3 bits wide and ry 125 us. may be programmed to offset the Time Slot assignment Transmit Signal Processor by 0 to 7 MCLK periods to eliminate any clock skew in In the transmit path (see Figure 3), the analog signal is the system (see Figure 5). Converted, ftered, compressed, and made availablefor In the Am7905A, the POM data may be user-pro- output. grammed to be output onto one of two ports, DXA The prefilter is an integrated anti-aliasing filter which | of DXB. Correspondingly, either TSCA or TSCB is prevents signals near the sample rate fromfoldingback also Low. into the voiceband during decimation. The AD is Receive PCM Interface designed to have a wide dynamic range and excellent +1. Feceive PCM interface logic (see Figure 6) controls signal-to-noise performance. It uses a modified sigma " , delta loop with a D/A convertertotrack the input signalat_ ‘the reception of data trom the PCM highway and trans- a512-khiz sampling rate fers it for expansion (1-law or A-law) to the Receive impling Signal Processor. The operation of this interface is iden- The Signal Processor contains an ALU, RAM, ROM and tical to the Transmit section. comroyagic fo mplement Fue s soe eer prcora 2 The Frame Syne (FS) pulse identifies the beginning of mable filter sections and their coefficients are stored in 2 Receive frame and all channels (time slots) are refer- 4 enced to it. The logic contains user-programmable the coefficient RAM. These filters may be made trans- ee a ae oe aime Clock Sled rool rent when not required in a system feceive Time Slot and Receive Clock Slot registers. pa The Time Slot registeris normally 5-bits wide and allows The decimator reduces the high input sample rate. The _up to thirty-two 8-bit channels (using MCLK = 2.048 X filter is a 4-tap Finite Impulse Response (FIR) section MHz) in each frame. But in the expanded mode, 6 bits and is part of the frequency response correction net- may be programmed to give sixty-four 8-bit channels work, The GX filter allows the user to program up to (using MCLK= 4.096 MHz) in each frame. The 12-dB gain in the transmit path with an accuracy of expanded mode bit becomes the sixth bit of the Time B filter has 8 taps and operates on sampled input from —_selected and it it is High, one of channels 32 to 63 is the Receive Signal Processor in order to provide trans- _ selected. This only applies if MCLK is 4.096 MHz. This hybrid balancing inthe loop. The low-passfilterlimitsthe feature allows clock frequencies of 2.048 MHz or output bandwidth to meet the transmission require- 4,096 MHz in a system. The MSB of the code must be ments. The high-pass filter rejects 15-Hz and 50/60-Hz —_received first. The Clock Slot register is 3-bits wide and frequencies, and may be disabled for testing. may be programmed to offset the Time Slot assignment 2-44 ‘Am7905A Data Sheet mm 0257527 0035647 234 mm

• Component values are user-programmable. Refer to SLIC product specifications.

Figure 1. Single-Channel Subscriber Line System

Table 1. Command Summary

SSSA’ Am7905A Detailed Serial Read Transmit Time and Clock Slots Command Definitions Command MSB .sB inactivate (Standby Mode) COREE RT) MsB usB Lote Te TeTe toto te} Output Data Inthe inactive made, none of the programmed informa Bret tion is changed and the analog output is set to 0 V ‘1 through a moderate series impedance. The Serial vo he wansmittime and clock slots are read out time slot remains active, the SLIC control outputs remain valid, _fiSt followed by clock slot. and the PCM outputs are high impedance. Receive Time Slot Selection Activate (Operational Mode) MSB LSB MsB i) Lot: To [up ute [ nt] GCE Ett ts tsts] Bits T, through T, select one of 32 time slots. Valid PCM data is not transmitted until after the second FS pulse is received following the execution of the Acti- Receive Clock Slot Selection vate command. MsB LsB Transmit Time Slot Selection Let: diet ey aye) MsB LsB Bits Ce through oe select one of eight clock slot offsets feTe Ts Teele sanainenime set Bits T, through T, select one of 32 time slots. Read Receive Time and Clock Slots Command Transmit Clock Slot Selection MSB LsB MsB LsB Lot: T+ [titi Tey: ) Ceti Ti TeTeta tate Output Data Bits C, through C, select one of eight clock slot offsets within te time sll ay The receive time and clock slots are read out time slot first, followed by clock slot. SSS SLAC Products 2.51 M™ 025752? oo3snsy im |

Pa | AMD FINAL Write GX Filter Coefficients Write PCM Mode Selection Command MSB LSB MSB. LSB C+ To To Ts Te [x] Rex] Tex] Cot: TT fete ts] eo) Fcelve Port: Dn 0; PCM dati input on DRA. Input Data DO, =1; PCM data is input on DRB. Transmit Port: Dx = 0: PCM data is output on DXA. Byte 1 Dye 1: PCM data is output on OXB. Byte2 Receive Rex= 0: Reset Receive Expanded Mode. Expanded Mode: Rex = 1: Set Receive Expanded Mode. Read GX Filter Coefficients Transmit Tex =0: Reset Transmit Expanded Mode. Command Expanded Mode: Tex = 1: Set Transmit Expanded Mode. MsB use Cots Ti Ti teote Tey +) Read PCM Mode Selection Output Data Command G, ro mm, Byte1 MSB LsB Ce OO Byte2 Output Data Write GR Filter Coefficients command ee es MSB LsB Cette tte tei te) Enable Filters MSB LSB Input Data [+ To To To Tee f ex] er] ez] Byte1 Brite: EB=0: Biter disabled. Byte2 €B=1: Biter enabled. X Filter: EX=0: Xtiter disabled. 7 EX=1: X fitter enabled. Read GR Filter Coefficients R Filter: ER=0: R filter disabled. Command ER=1: R filter enabled. MSB LSB Z Filter: E—Z=0: Zfilter disabled. CoTi Ti titi fefet:) EZ=1: Zfiter enabled. Output Data Byte 1 Byte2 252 "Am7905A Data Sheet we 0257527 0035655 350

Write Test Mode Selection Read B Filter Coefficients MSB. LSB Command CTT TT Telets] SB ise T3 T2 T1 Function © © 0 Resetto normal conditions as follows. Receive gain is set to the value stored in the GR register. Analog. and digital loopback modes are reset. The high-pass filter is enabled and Output Data ‘the auto-zero circuit is operational. The receive path is not cutoff. 0 0 1 Add -6 dB receive gain. aye 0 1 0 Cutoff receive path. © 1 1 Disable high-pass filter (set to 1) and freeze | | | | | | auto-zero Circuit. 1 0 0 Activate digital loopback. | | | | | |

111 Aatvate analog loopback ayte 12

Select PCM Coding . se LsB Write X Filter Coefficients Command Cee TTT Te] MSB LSB Bit B selects the type of PCM code to be used, Cito T+Tofo[:]ofo] Forthe Am7905A: B =0: A-Law. Input Data B=1: p-Law. Byte 1 Wile SLC Output Registers ye 2 MSB Ls Bytes

8 Byte 4

Write B Filter Coefficients Byte 6 Command re sa ts a Read X Filter Coefficients Input Data Command MSB LsB Byte 1 eee Cie? tT Tete Ty Tt) Bye? Output Data Byte 4 Bytes ayt61 Bytes rT rT Byte7 Bytes | td | I Byte9 Byte Byte 10 Byte 11 Byte 12 ee SLAC Products 2-53 @™ 0257527? OO35b5b 297

Write R Filter Coefficients Write Z Filter Coefficients Command Command MSB LsB MSB LsB CTeT Tet Tetete| CeTeT+ Te Ts Ti tot 2) Input Data Input Data Byte 1 Bytes Byte2 Byte 2 ee a ayes axe a Byte 6 Bye 6 ates [Cw me | ome Bre Read R Filter Coefficients Read Z Filter Coefficients Command Command MSB LsB MSB LSB (Tet Tet Tet ts) CeTe T+ Tet: Ti tit] Output Data Output Data 1 to 1 tol 1 to 1 tol | ti Lt Lod | tot Select MCLK Frequency MSB LSB Cte: Tite ts] Bit C selects the MCLK frequency to be used. C=0: MCLK = 2.048 MHz C=1: MCLK = 4,096 MHz ee 2-54 Am7905A Data Sheet me 0257527 0035657 123

Figure 11. SLAC Signal Processing Flow The advantages of digital filters are: where the number of taps in the filter = n+ 1. system, and adjust the two-wire line termination impe- N = Number of CSD coefficients. summation node. The method used in the SLAC is the length of the registers in the ALU.

rightmost part represents decimal fractions, and a deci- x _ is the position of this CSD coefficient within mal point separates them. The first binary 1 is shifted M, the h coefficient. It represents the relative bits to the right of the decimal point, the second binary 1 position of the binary 1 represented by this is shifted M, bits to the right of the decimal point, the third CSD coetticient within the h, coefficient. The binary 1 is shifted M, bits to the right of the decimal point, most significant binary 1 is represented by and 0 on x= 1, The next most significant binary 1 is represented by x = 2, and so on. Note that when M, is 0, the resulting value is abinary1 = Taus i ; . 7 i, , 7 , CyaM,, represents the sign and the relative shift in front of the decimal point, thats, no shift. If Mz iS alS0_Gosition for the first (most significant) binary 1 in the 4th 0, the result is another binary 1 in front of the decimal —_(h,) coetticiont. point, giving a total value of binary 10 in front of the decimal point (i.¢., a decimal value of 2.0). The value of + The number of CSD coefficients, N, is limited to 4 in the N, therefore, determines the range of values the coetfi- GR, GX, R, X, and Zfilter, and 3 for the B fitter. Note also cient h can take; for example, if N=3 the maximum that the GX filter coefficient equation is slightly different and minimum values are +3, and if N = 4 the values are from that of the other filters: between +4. fox= 1 +h 6 Detailed Description of SLAC Coefficients Please refer to the section detailing the commands for The CSD coding scheme in the SLAC uses a value —_ complete details onthe programming of the coefficients. called m,, where m, represents the distance shifted right . of the decimal point for the first binary 1, m, represents TWO-Wire Impedance Matching the distance shifted to the right of the previousbinary 1, A feedback path is provided from the transmit to the and m, represents the number of shifts to the rightofthe receive section via the Z filter. This filter may be pro- second binary 1. Note that the range of values deter- —_ grammed to moditty the effective termination impedance mined by Nis unchanged. Equation2isnow modified (in (Zs) of a SLIC or a transformer hybrid to a desired the case of N = 4) to: value. The desired impedance may be complex. This =B2M 2 M3 “ feature allows the user to terminate each SLIC in a Sub- eB2M' + B2Me + BPM + Bz M 9) scriber Line System with a fixed resistor and digitally h=C.214C,0,24m1 +m2) 4 C,C,C,24mt + m2 +m3) modify their impedance using the Z fitter. + C,C,C,C,21m1 + m2 + m3 +m4) (4) The Xand R filters are the Transmit and Receive attenu- ation distortion correction filters. These filter sections heC2™ [140,22 (14029. (1402-4) (G)_—_are programmed to compensate the attenuation distor- tion caused by the Z filter. where: ‘ M,=m, and B, = C, Transhybrid Balance M,=m,+m, B,=C,-C, In a traditional linecard system, a balance network is M,=m,+m,+m, By =Cy-C,-Cy used with the SLIC to achieve transhybrid balancing. It M.=m,+m,+mame — By Cy Cz Cy Ce the balance network perfectly matches the subscriber's , am _ line, infinite transhybrid balancing is achieved. But in in the SLAC, a coefficient h consists of N CSD coeffi: —_ general, the matching in traditional systems is poor and cients, each being made up of 4 bits and formatted as transhybrid balancing is not very good. Some systems Cam, where C,y is one bit (MSB) and my is 3 bits. —_ have up to 2 or 3 compromise networks per line that Each CSD coefficient is broken down as follows: must be selected semi-automatically or manually to pro- Cy _ is the sign bit (0 = positive, 1 = negative). vide the balance. Mm, _ is the 3-bit shift code. It is encoded as a In the SLAC, a feedback path is provided from the binary number as follows: receive to the transmit section via the B filter. This fitter 000: illegal may be programmed to cancel the received signal from eat : § snes the transmit signal path and achieve a significantly i level of transhybri . ott: 4 shifts improved level of transhybrid balance. 100: 3 shifts Gain Adjustment 101: 2 shifts . ; ; ‘ 410 4 shift Signal levels in the transmit and receive paths may be 111. O shifts modified by programming the GX and GR fitters. The GX y isthe coefficient number (the i inh). filter allows the user to add up to 12 dB of gain (with an accuracy of 0.051 dB up to 10.4 dB and +0.15 dB up to 12 dB) in the transmit path. The GR filter allows the user to add up to 12 dB of loss (with an accuracy of +0.051 dB) in the receive path. 2-56 ‘AM7905A Data Sheet WM 025752e7 0035659 TTL Ml

Test Features information retain their data. The Serial VO Intertace The SLAC simplifies system testing by providing both “@™ins active to receive new commands. digital and analog loop-back paths. Underprogramcon- — Power-On Clear trol, either the DRA or DRB input is looped to the DXA or ; vas Before any other command: nto the SLAC, 1 OX output (digital loop-back) through a path fromthe inactivate commands should be sontiothe sefial otal output ofthe interpolator in the receive path tothe input the SLAC in case the SLAC powers upin he middie ot a of the decimator in the transmit path. The Vw input is reaq sequence. Alternatively, a hardware reset opera- oped to the Vou output (analog loop-back) through tion can be carried out by applying 5 Vto the DCLK pin, the 2 titer To alow testing ofthe subseriberloopcabling A Or CLK should be Weaten lke loos of powcr for leakage, the transmit high pass filter may be disabled : and auto zero operation interrupted. The receive analog + Stand-Alone Mode output may be programmed to open-circuit or cut off the . , , receive path. This receive cut-off command may be Inthe stand! oe nine wee fal imewece baliareen used to stop oscillations in the four-wire side of the tele- device ‘Applying—5 V to the DCLK pin resets the device Bhone network. and the Dy pin can subsequently be used to power-up The SLAC contains an auto-zero circuit inthe A/D con- _ or power-down the SLAC. verter which takes several seconds to settle following a change in the offset voltage at Viv. To facilitate compo- DCLK Dio nent testing of the SLAC, there is atest mode available || to accelerate settling of the auto-zero circuit. This test Fs x Nonmal Megs mode is activated by holding the CS input at -5 V for at -5V ° Reset and Power-Down east 64 ms with the offset voltage applied to Vix (and no 3V 1 Reset and Power-Up signal). The auto-zero will settle inthis time. Inacompo-—§—§ —————_____""" SU NUNNTP nent test environment, this procedure should be fol- Reset State Towed after programming the fiers. The Reset State of the device is: Note: The digital loopback (DLB) path processes an , . internal data word 2-bts shorter than in normal mode, Beth Transmit and Receive, Time and Clock Siots Therefore, DLB signal processing performance is not are set to 0. equivalent to normal mode signal processing and does b. Adawis selected. not meet the specified transmission specifications. DLB ; - is recommended for use with 0 dB programmed gain/at- ©. B, X, R, Z filters are disabled. tenuation and PCM signal levels above —25 dBm0. d. Both Transmit (GX) and Receive (RX) gains are Standby Mode set to unity. The SLAC is forced into the standby mode either by a @. SLIC outputs (C5—C1) are set High. hardware reset applied to the DCLK input or by recep- f. Normal conditions are selected, tion of the Inactivate command. In this mode, power is switched off from all circuitry that can be turned off. No g. DXA/DRA ports are selected. transmission or reception of PCM data takes place. h, Device operates with 2.048-MHz clock only. However, the circuits which contain programmed SSS SLAC Products 2-87 0257527 0035660 718 mm

u-Law: Positive Input Values SO CS SO A Number el Value at | Decoder segment | ofnane |Ymentson| Owain | onan | Shrarsy | deter | “Sapa Number |X interval Output Value ts End Points | Numbern | x, (1) Bit Number Size azs4ase7e| Ye) | Number 10000000] 8031 127 127 | 7008 i i 113 4319 4063 112 4063 - : t 7 16 x 128 97 2143 Hi i i 2016 96 2018 : : : 81 1055 - ° “ 991 80 991 5 ; F 65 511 Tortiiat 495 64 479 6a 19 : 223 48 233 : A 8 108 Parotid 99 22 95 32 95 5 i H 2 " % Titotttt 33 16 3 16 31 t i A 2 8 71111110 2 1 tf | ° o ~~ _° ° Notes: 1. 8159 normalized value units correspond to TMAX = 3.17 dBm0. 2. The character signal corresponding to positive input values between two successive decision values numbered n and n+ 1 (see column 4) is (255 - n) expressed as a binary number. 4, x128is a vial decision value. 2 5. Bit 1 is a 0 for negative input values. NO 2-58 ‘Am7905A Data Sheot 025752? OO35bb1 654 me

$I ADE A-Law: Positive Input Values A ES EE RE SS A mber Character Signal fu Value at Seg-| Decision | Decision | Before inversion | Valueat | Decoder of Intervals ofthe Even Bits | Decoder | Output Xintorval | Tees | N value vane Bit Number Output Value Sze | End Pointe | Number | x (1) Y(9)_| number [ae (2a) G88) Poo 1 11 127 3968 : 4032 128 ns Shane EEEETTY) ‘ \\ 2048 112 2048 . ane 13 1024 96 4024 Z 1056 7 512 80 512 r 528 8 65 2 - : : 256 64 256 264 65 3 49 136 i i 128 48 128 : 182 43 64 32 64 p A {| ° es Notes: 1, 4096 normalized value units correspond to TMAX = 3.14 dBm0. 2. The character signals are obtained by inverting the even bits of the signals of column 6. Before this inversion, the character signal corresponding to positive input values between two successive decision values numbered nandn + 1 (see column 4) is (128 + n) expressed as a binary number. 4. x128 is a virtual decision value. 2 5. Bit 1 is a 0 for negative input values. $$ SSSSSSSSSSSSSSSsSsSSSSSSSsssSsSSSSSSsSS SLAC Products 2-59 mi 0257527 O0a5bb2 590

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES AGND oo... c ec cceeeeeeeeeeeeees DGND £100 mV ‘Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at Operating ranges define those limits between which the ‘or above these limits is not implied. Exposure to Absolute Max- functionality of the device is guaranteed. imum Ratings for extended periods may affect device reliability. ee DC CHARACTERISTICS over operating range (See Note 1) unless otherwise specified [Parameters [Descrpton Tost Conations [win] yp] wax | uns | [2m p20 | | P| fo | [vex foteavngerionesonve [| | | eo fo | [vo Anabg Oupaoneeivorage [+t | |e fav | a a To A OC Vi Tnput Low Voltage (Al Digital Inputs Except DCLK in Stand- Alone Mode and CS in Auto-zero Speedup Mode) 05 v A a Vou ‘Output Low Voltage (All Digital Outputs) low = 2mA v Vou ‘Output High Voltage (All Outputs Except TSC) lou = 400 HA v [Tx [Oatteatage cure SN A VP SS A Vea Supply Curent (Standby) Voo #525 pe Vee Supply Gurren (Acva) Veo =-475V pT a 200 mV p-p @ 1.02 kHz - the iat / cece Cup Capactance Dota | 1s] 1 | Note: Typical values are for T, = 25°C and nominal supply voltages. Min and max specifications are over the temperature and supply voltage ranges shown in the above table entitled "Operating Ranges." Sd 2-60 Am7905A Data Sheet mm 0257527 OO35bb3 427 Ml

$A A TRANSMISSION CHARACTERISTICS voltage of 1.6 V for A-law and 1.588 V for p-law at the All specifications are guaranteed with OdB<GX<+12 analog output. When GX = 0 dB, a 1020-Hz sine wave signal with rms voltage of 1.569 V for A-law and 1.557 V dB,-12 dB < GR < 0dB and A-lawor ji-law companded * PCM, unless otherwise specified, for u-law at the analog input will correspond to a level of h : 0 dBm0 at the digital output. When GR = 04B, a 1020-Hz sine wave signal with level of 0 dBm0 at the digital input will correspond to an rms. a Gain (either path) a. Deviation from ideal value 1020H2z@-10d8mo | -02 +02 | 4B bb. Deviation from initial value 02 +02 | dB Group Delay Distortion (either path) 10 d8mo signal | | (s00 Fig. 14) [| | | Tntermodulation Distortion a. (Note 2) 35 | 8 b. (Note 3) -49 | 6Bmo Crosstalk a. Go-to-Return Path 300 to 8400 Hz, 0 d8mo) -90 -7o | a8 b. Return-to-Go path 300 to 3400 Hz, 0. dB8mo -90 ~70 |B Gain Tracking (either path) (00 Fig. 15 &17) Signal to Total Distortion (either path) (see Fig. 16, 18, & 19) y-Law Companded PCM ‘A-Law Companded PCM Notes: 1. Applied signalis a 0-d8m0 sine wave within 300 to 3400 Hz. The signal measured is any frequency in the range 300 to 3400 He. 2. Two different frequencies, f and, in the range 300 to 3400 Hz and of equal levels in the range —4 to-21 dBm0 are applied. 2h-f products are measured relative to the level of either f; or b. 3. Any intermodulation product due to a signalin the range 300 to 3400 Hz with input leve!-9 dBm0 and a50-Hz signal with input level -23 dBmd. SLAC Products 2-61 wm 0257527 DOSSbbY 3b3

Figure 14. Group Delay Distortion (Elther Path)

08 Input Level

Measured per CCITT Rec. G.714 Paragraph 15. Figure 15. Gain Tracking with Tone (Method 2) Transmit or Receive Path

Measured per CCITT Rec. G.714 Paragraph 14. Figure 16. Signal-to-Total Distortion With Tone (Method 2) Transmit or Receive Path

0.35 Gain

Measured per CCITT Rec. G.714 Paragraph 15. Figure 17. Gain Tracking with Noise (Method 1) Transmit or Receive Path

SWITCHING CHARACTERISTICS over operating range unless otherwise specified Ta=0°C to 70°C, Veo = +5 V #5%, Vex = -5 V 45% (See Notes 1, 5, and 6) [Ne[Parametor | Descrotin Lwin tye ox Yt | [+ [tocu Data Clock High Pulse wiath Note2) ozo TT 20s [2 [ton | Data Clock Low Pulse Wieth (Note) [0.220 TT Ts [3 [toon | ‘Rise Time of Glock Ts sos [a Tice | Falttime otek ids | Cd ds | [& [tess | Chip Select Setup Time Pts Ps [6 Tics, | Chip SelectHoidTime Tso Ps ee Chip Select Off Time after byte written to or belore byte read from B, Z, X, R, GX, or GR in Active mode. MCLK = 2.048 MHz 32 tucy MCLK = 4.096 MHz 64 tucy Otherwise: MCLK = 2.048 MHz 7 wey MCLK = 4.096 MHz 14 tucr [e [x] top Data Seuptine id | CT Cd | Ho [tox] tap Data Hos Time i 0 | id Cid | [i [eas | outtneh Popeoaiondey 875 Pe [12 Tics [| Chip Select Setup Time Tso Te | [73 [tocsa | Chip SelectHoldTime Tso ns [14 [toc | Chip Select Pulse Width (Notes 3&7) | Btcy Pn Chip Select Off Time After Byte written to or before byte read from B, Z, X, R, GX, or GR in Active mode. MCLK = 2.048 MHz 32 tyey MCLK = 4.096 MHz 64 tucy Othemise: MCLK = 2.048 MHz Thue MCLK = 4.096 MHz 14 tuor [Fe [os Outnut Data Tum onDoey {<i + oi | [Yio | OupuDaarontine | do [18 [tooo | Ouput Turn of Daay id id | [78 [cos | Oupabaavais [PCM interface [25 [uss | FraneSosouptime 0 [| tam [ | [26 [tess Frame Syne Hold Time (CompandedMode) [30 (Btucy 50) [ns | [Wiser 3) [ | Winer 1507] —rs_| [ee [so | Detay wo TSC OM (High impedanesy | 30 [| =i» ‘| [2 [oo [Pom Data ouputdomy st Oe [50-[tou | POM Data Ouiputoa tine 90 | | 00 |__| [Stax | POM Data OuputOeayionignz {| | | ms _| [32 [ons | POMDatanput Sep Time ‘| 50 | | ‘|r| 2-66 ‘Am7905A Data Sheet @ 0257527? O035669 145

8,5 SWITCHING CHARACTERISTICS (continued) [Re[rwraneier | Deweipten <i we] we | wx] nie] Master Clock (2.048 MHz) [5* [iwc ___] Master Clock Parod | “a5 | “e808 | [35 [wer | Master Clock Figh Puse Wah a [25 uc. | Waster Gock Low Pulse Wath a a Fise Tim of Cock [Ps ‘Master Clock (4.096 MHz) [55 Jr | Waster Cook Pored cL [22 [we | Waster Gack igh Pogo Wa [90 [21 [nes | stor Seek Tow Pas Wah nr A [Pace | Fa ine of ek A Notes: 1, Min and Max values are valid on all digital outputs except C5—C1 with a 150-pF load. C5—C1 outputs are valid with. a30-pF load. 2. The Data Clock may be stopped in the Low state indefinitely without loss of information. Data will not be clocked in or out while the clock is in the Low state. 3. Chip Select Pulse Width is nominally 8 Data Clock Cycles with a minimum value of 7 Data Clock Cycles + tesy + tess anda maximum value of 9 Data Clock Cycles — tesw — tess- 4. TST is delayed from FS by a typical value of N tucy, where N is the value stored in the Time/Clock Slot register. 5. The Frame Sync pulses repeat at an 8-kHz rate. 6. FS and MCLK must be synchronized and exactly 256 cycles of MCLK must be guaranteed between Frame Syncs. 7. tocy is 1 Data Clock Cycle. SWITCHING WAVEFORMS Input and Output Waveforms Master Clock Timing For AC Tests 20) ‘Test 20 Go) nd osf Points Log et 0.45 Vi 07004B-022 07004B-023 ee SLAC Products 2-67 WM 0257527 OO35670 bb?

Serial Interface (Input Mode) bobo DCLK Los . Pl Lt ® b, 9 tL @ ‘ © YWVVVVVV WY 0: VVV\\ Dat irae) KXXXAXE ais XY) Val XXX eis | ‘ es 0: Data eer val ; Vaid 070048-024 Serial Interface (Output Mode) v DCLK ve @ ®@ a a @ © ® (eu Three-State Vou’ Data Wr Data Data Three-State Nose ve vos AQ ae Xa} a 07004B-025 2-68 ‘AM7905A Data Sheet @ 0257527? O035b71 5ST3

FINAL amo & PCM Highway Timing Time Siot Zero Clock Stot Zero Vu MCLK Mi H iS \\ Fs f e © Vou oor Pee 1D Vo. ° mh ° TESTMNANNANNANAA EDN lars QR000 LINN ANN . 07004B-026 SLAC Products 2-69 @™ 025752? OO35b72 43T

8-Channel Subscriber Linecard To/From Other Equipped Channels Subscriber|— A(TIP) Vix Vw oxa |} Line 1 B(RING) RSN rt Vour TSR oT > a ea, | | suc CEST] Am7oosa on LT | SLAC ope a 2 E0| Do DET os DCLK ' PCM : Highway : A A(TIP) v, DXA coo Ho Subscriber} x Vi lighway Line 4 BIRING) = -RSNKR—$}—} Voy TSCA hn | ee TSCB K CET] Am7e0sa ‘ stac PRAY ry ORB = all Do DET ios CLK i Linecard Controller Link to Higher Level Processor o70048.027

27 AmT@05A Data Sheet

mi o25752? 0035673 37b

Am7905A DATA SHEET REVISION SUMMARY The following list represents the key differences between revision B (August 1990) and revision C (December 1994). WORLOCHIP® was deleted from the title. Ordering Information—Page 2-40 WORLDCHIP was deleted. ‘Am7905A Data Sheet 2-71 mi 0257527 0035674 20c