AM7201 AMD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
- . Micro High Density First-In First-Out (FIFO) Devices 512 x 9-Bit CMOS Memory DISTINCTIVE CHARACTERISTICS RAM based FIFO Status flags—full, half-full, empty @ 512 x 9.organization @ Retransmit capability @ Cycle times of 35/45/65 ns for standard @ Expandable In both width and depth products @ Increased noise Immunity for XK—CMOS ™@ Asynchronous and simultaneous writes threshold and reads @ Pin compatible with industry standard devices ™@ Low power consumption GENERAL DESCRIPTION The Am7201 is a RAM-based CMOS FIFO that is 256 High-density FIFOs such as the Am7201 are useful ina words deep with 9-bit wide words. It is expandable to wide range of applications. The ability to buffer large any width and/or depth to create much larger FIFOs. transfers of data and the rate adaption capabilities make This FIFO can input and output data asynchronously the Am7201 useful in communication, image process- and simultaneously at data rates from 0 to 28.5 MHz for ing, mass storage, DSP, and printing systems. Standard Products. Status flags are provided to signity empty, full and half-full conditions. The capability also exists to retransmit data from the FIFO. BLOCK DIAGRAM Do-De Fo core | | ee | Read [ eee, | 51282 | Po Outputs co ont S xm Ls” XOFF 10175G-1 Figure 1. PRODUCT SELECTOR GUIDE [Part Number] Am720v-25 | Am7201-35 | Am7201-50_| [Access Time | 25ns_[a5ns_ | 50ns | Maximum Power Supply Current 70 mA Operating Frequency 22.2 MHz Operating Rangel Com [com [com | Issue Dave: September 1962 2-19
oo fs 26H Ds ot 5 ° 29 [D. De M4 251] De oe 28 []0;, os 24H by DoL] 7 27 fc Do M6 23 0) FUT xiqjs 26 [)FUAT xq? 22[] RS FF] 9 2s []RS FFs afer Qo] 10 24 DEF Qo 9 201] xonmF QQ 23 []XOMF a; J 10 wa, Ne[] 12 22 fa, aq 18] Os of] 13 . 217] O5 4 1 8 a1 17fas Sees Qe YJ 13 16 [] Q« s5gekad np [14 ispR 10175G-3 10175G-2 Note: Pin 1 is marked for orientation for plastic packages. es LOGIC SYMBOL 7—+| Doe 0-8-7 FURT xi FF w XOWRF = — FF R RS 10175G-4 2-20 Am7201
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is, formed by a combination of: ‘AM7204 25 Pp c L_ OPTIONAL PROCESSING Biank = Standard processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) PACKAGE TYPE P = Plastic DIP (600 mil) (PD 028) J. = Plastic Leaded Chip Carrier (PL 032) R = Plastic DIP (300 mil) (PDW028) SPEED OPTION -25 = 25nsta “35 = 35nsta 50 = SOnsta DEVICE NUMBER/DESCRIPTION Am7201 High Density First-In First-Out (FIFO) 512 x 9-Bit MOS Memory Valid Combinations Valid Combinations "AM7201-25 Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- AM7201-35, PC, RC, JC cal AMD sales office to confirm availability of specific valid combinations, and to check on newly released valid combinations. Am7201 2.21
Data In (Inputs (3) Data Out (Outputs (9), Three State) ‘These nine pins are the data inputs to the FIFO. These nine pins are the data outputs for the | FIFO. a These pins are in a high impedance state whenever EF Read (R) is HIGH. Empty Flag (Output; Active LOW) i The HIGH state of the Empty Flag (EF) indicatesthatthe = —__ . FIFO contains datato be read. The EF goes LOWwhen _—_-Read (Input; Active LOW) the read pointer is equal fo the write pointer, indicating The falling edge of Read (A) initiates a read cycle, ex- that the device is empty. EF LOW inhibits further Read cept when the device is empty, as indicated by the operations. Empty Flag (EF) being LOW. Valid data appears on the The FF goes HIGH attertherisingedge of write (W) cur. UtpUtS (C-8) after the fang edge of R. After F goes goest! HIGH, the Data Outputs (Q0-8) will return to a high im- ing the frst write cycle for an emply FIFO (See Figure 4). begance condition The EF goes LOW after the falling edge of Read(R) dur- PPC’ ing the read cycle which creates the empty condition. RS During a Reset cycle, the EF is driven LOW (active) Reset (Input; Active LOW) FF The falling edge of Reset (RS) is used to reset the FIFO. During Reset, both the read and write pointers are set to Full Flag (Output; Active LOW) the first location in the FIFO. Since the reset cycle initial- The HIGH state of the Full Flag (FF) indicates that the _izesthe roto anemply: Concition, the Empty Fag j=3) FIFO is capable of accepting data. The FF goes LOW is driven LO {active}, and both the Halt-Full Flag (HF) when the write pointer is one locationtessthanthe read and Full Flag (FF) are driven HIGH (inactive). pointer, indicating that the device is full. FF LOW inhibits Vv. further Write operations. co s = Power Supply The FF goes HIGH after the rising edge of Read (R) dur- 7 ing the first read_cycle following a full condition (See This pinis the +5 V power supply for the FIFO. Figure 6). The FF goes LOW after the falling edge of yy Write (W) during the write cycle which creates the full condition. Write (Input; Active LOW) 4 1 The falling edge of Write (W) initiates a write cycle, ex- During a Reset cycle, the FF is driven HIGH (inactive). os nen the device is full, as indicated by the Full Flag FURT (FF) being LOW. Data is latched into the FIFO on the First Load/Retransmilt (Input; Active LOW) rising edge of W. This is a dual purpose input, dependent upon whether Xt the FIFO is in Single Device Mode or Depth-Expansion Expansion in (Input; Active LOW) Mode. _ Expansion in (Xi) is grounded to indicate operation in This pin acts as a FIRST LOAD (FL) pin when in the __ the Single Device or Width-Expansion Modes. In Depth Depth-Expansion Mode. The device receiving datatirst_ _ Expansion Mode, the Xi pin is connected to the Expan- will have the FL input tied LOW, while the remaining de- _sion Out (XO) pin of the previous device, except for the vices will have the FL pin tied HIGH. The statesof the FL__XIpinof the first device which is connected tothe XO pin and Expansion In (Xi) pins are used to determine the _of the last FIFO. FIFO's mode of operation, as shown in Tables 12nd 2. ry. 5in operates at CMOS logic levels, thus providing This pin is used as the Retransmit (RT) input during Sin-_noise immunity between cascaded devices. gle Device Mode. The device can be instructed to >= retransmit the previously written datawhen RTispulsed © XO/HF Low. Expansion Out/Half-FullFlag (Output; Active LOW) GND This is a dual purpose output, dependent upon whether the device is in Single Device Mode or Depth Expansion Power Supply, Ground Mode. This pin is the 0 V power supply for the FIFO This pin operates as an Expansion Out (XO) signal dur- NC ing Depth Expansion Mode. In this mode, the XO pin is No Connect connected to the Expansion Input (Xi) pin of the follow- ing device, except for the XO pin of the last device which These pins are not connected is connected to the XI pin of the first device. 2-22 Am7201
When in Single Device Mode (Expansion In (XI)_pin HIGH afterthe rising edge of Riduring the read operation grounded) this output operates as a Half-Full Flag (HF). which eliminates the half-full condition (See Figure 5). Alter half the FIFO has been filled, the HF will be set . Dk ie arn hat LOW at the falling edge of the next Write (WW) operation, During a Reset cycle, the HF is driven HIGH (inactive). The HF will remain LOW untitthe difference betweenthe This pin operates at CMOS logic levels, thus providing write pointer and read pointer is less than or equal to one noise immunity between cascaded devices. half of the total memory of the FIFO. The HF will go Am7201 2-23
address pointers. The flag logic prevents illogical writes —_ing edge of Wwill be stored sequentially in the FIFO. depth greater than that of the Am7201. The write, read, overflow situations. data-in and data-out lines of the Am7201 areconnected —_A special case of write occurs when a write operation is. and read control circuits of the individual FIFOs are FIFO twer after the rising edge of FF (see Figure 9). valid reset cycle to occur, both the Read (R) and Write sion Mode but is not active. rising edge of Reset (AS). The reset cycle initializes the of Rduring the first read cycle following a full condition. Full Flag (FF) being HIGH, inactive. which eliminates the half-full condition. (See Figure 5). hee ing a data underflow situation. FF til tape after the rising edge of EF (see Figure 8). Figure 2. Reset Timing
Table 1. Reset and Retransmit Truth Table
- Flags will change to show correct state according to write pointer.
2, Pointers will increment only if corresponding flag is HIGH at the beginning of the cycle. Table 2. Reset and First Load Truth Table
- Xlis connected to XO of previous device. See Figure 14.
- Same as during Reset Cycle.
- Pointers will increment only i corresponding flag is HIGH at the beginning of the cycle.
Figure 3. Asynchronous Write and Read Timing
amo &t a ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Ambient Temperature with DC Output Current ... voceeeeeeee es SOMA Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maxi- mum ratings for extended periods may affect device reliability. imum ratings jorexentoreeeeerereeeree ee ee Oe DC CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified ‘Am7201-25 | Am7201-35 Parameter| taz25ns | ta=35ns | ta=50ns Input Leakage Current (any input) (Note | 1 [1 [1 [ + [4 + [va Output Leakage Current (data outputs) 10] 10 BA (Note 2) Vin Input High Voltage (all inputs except XI) 2.0 2.0 Vv (Note 3) Vie Input Low Voltage (all inputs except XI) v (Note 3) Input High Voltage, XI (Note 3) [ss| [ss] [ast Tv] Input Low Voltage, XI (Note 3) [fas| Tis fist v | Ouiput Logiot" Votagelon=-2ma [24] [eat [eat | v | Output Logic" Votagein=ema | foal [oa] [oa] v | lees Average Vcc Power Supply Current 70 mA (Note 4) leca_ | Average Standby Current (R = W= RS = FLIRT = Vin) (Note 4) Ics | Power Down Current 5 mA (all inputs = Voc - 0.2 V) (Note 4) Notes: 1, Measurements with GNO < Vin s Veo, 2. Fi. Viti, GND < Vour s Vee. 3. Vic and Vin are input conditions of output tests and are not themselves directly tested. Va. and Vii are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 4. loc measurements are made with outputs open. a . Am7201 2:31
SWITCHING CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified [Sm earmeteroescnpton gars a a Ha | ne [_twe [Write GyceTime Ts TasT Tas Test [as | [Tw fwite Puse wan [3 [asf s[ [50 [ns | [twa [Write Recovey tine [3 | sof | [8] [rs | [tos [DataSeuptime 3.9 [sf fe] [oof [ns | [ton [Datavoidtime 9 Poof fot [st [ns | [wr |wee tow rurregiow [es | [as] [a] | [ns] [wir [Wwete Low toHar-FulFagtow] 6 || ss[ [| | 65 | ns | [wer [Write HIGH to Empty FlaghiGH [48 [ [25 [| so [| 45 [ns | Pm feeormareeme PTT TET TT | at LOW Z (Note 1) |__twer [Write Pulse WidthatterFFHIGH | 9 | 25] [a5[ 7 [so[ Ins | [tac [Read CycleTime | 3 35 Pas [Tost [ns | | tan [Read Recoverytime | 3 | sof [of fas[ Ins | |_tww [Read Puisewisn | 3 | as[ [asf [sof [ns | i at LOW Z (Note 1 | tov __|DataValidtromReadPulseHiGH| 3 | 5] | s{ [s] [ns | a at HIGH Z (Note 4 [| twe [ReadHiGHtofuiFlaghicH | 69 | | 25[ [30] | 45 [ns | | tee [Read HiGH toHat-FullFlagHicH] 5 [| 35 | [45 | 65 | ns | [_trer [Read LowtoemplyFiaglow | 48 | | 25[ [| 3so[ | 45 [ ns | [twee [Read Puse wietnatereFHiGh |e || [as] [50] [ns] [tas [Reset Cycle Time [2 Tas Tas Tf esT [ns | [tas [Reset Puisewidtn | 2 | as] [as [sof [ns | |_twss_[ResetSewptime | 2 | 25] [a5 [sot [ns | | tsa [Reset Recovery time | 2 | sof [of fs] [ns | [__ter.[Resetto Empty Flagtow [2 [| as [fas [| 65 [ns | [rir [ResettoHatrrutFiagHoh [2 [| as[ | «| [65 [ns | |_ten [ResettoFullFiagHiGH | 2 | [35[ | 4s] [ 65 [ns | [tare [Retransmit Cycle Time | 7 [a5] ast Tes T [ns | |__tar__|RetransmitPulse with | 7 | 25[ [a5 | [sot [ns | |_tars _[Retransmit Setup Time (Note 2) | 7 | as] [as] [so[ [ns | [nen |Reversmtecovey tine | 7 [0] fwo] [ws | [ne Notes: 1, These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. 2. Values are guaranteed by design and are not currently tested 2-32 Am7201
SWITCHING CHARACTERISTICS (continued) Sfmt [paanewoeciton [rus wnt tt Ha] |v [Readwateoxovow fo [fast fas [| 80 [ns | [ReagwrtetoxoHGH | 10 [| as | [a5 | 50 | ns | Lm |xPusewian oe) |_| as[ [as{ [sof [ns | Prof fof ns | [es [xtseuptine Po Po fe [Tre | Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. 2. Values are guaranteed by design and are not currently tested EE Am7201 2-33
- Includes jig and scope capacitances.
Figure 17. AC Test Load Symbol | Parameter Description (Note 1) | Test Conditions Typ. modified where capacitance may be affected.