AM7200 AMD | Alldatasheet
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High Density First-In First-Out (FIFO) paicre 256 x 9-Bit CMOS Memory DISTINCTIVE CHARACTERISTICS @ RAM based FIFO ® Status flags—tull, half-full, empty M256 x 9 organization ™ Retransmit capability @ Cycle times of 35/45/65 ns for standard ™@ ~=Expandable in both width and depth products ™ Increased noise immunity for X}-CMOS, ™ Asynchronous and simultaneous writes threshold and reads Pin compatible with industry standard devices Low power consumption GENERAL DESCRIPTION The Am7200 is a RAM-based CMOS FIFO that is 256 High-density FIFOs such as the Am7200 are useful ina words deep with 9-bit wide words. It is expandable to _—_ wide range of applications. The ability to buffer large any width and/or depth to create much larger FIFOs. transfers of data and the rate adaption capabilities make This FIFO can input and output data asynchronously _—‘the Am7200 useful in communication, image process- and simultaneously at data rates from 0 to 28.5MHz for —_ing, mass storage, DSP, and printing systems. ‘Standard Products. Status flags are provided to signity empty, full and hatf-full conditions. The capability also exists to retransmit data from the FIFO. BLOCK DIAGRAM Do-Ds WwW Wr . oe [ raner | 256%° | Pointer p 5 Outputs: Control = ed Bie Logic Figure 1. PRODUCT SELECTOR GUIDE [Part Number | Am7200-25 | _Am7200-35 | _Am7200-50 Maximum Power Supply Current 70 mA 60 mA Operating Frequency 28.5 MHz 15.3 MHz Issue Date: September 1992, 23
Ds : 2 p De STs t Te dss 261] Ds D5 ° 29 [1D, de Ys 251) de Dj 6 2a []o, os 26 or Dol 7 27 [NC Do 6 23] FURT xg s 26 DFURT xiQ7 221) RS FF) 9 25 RS woe 20eF Qo] 10 24 DEF ao 9 200) xonF ad 23 DXOmF ato tsa, Ne[] 12 22a, a1 18 fas Off 13 211106 14.15 16 17 18 19 20 Qs J 12 17) Os Seer asf}is 16 fa seek ad cnp [14 ispR 10804F-3 10804F-2 Note: Pin 1 is marked for orientation for plastic packages. —_— LOGIC SYMBOL %— do-e os > FURT xi FF Ww XOnF Ros OF 10804F-4
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ORDERING INFORMATION
‘AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is, formed by a combination of: AM7200 25 P c L_ OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE © = Commercial (0°C to +70°C) PACKAGE TYPE P = Plastic DIP (600 mil) (PD 028) J. = Plastic Leaded Chip Carrior (PL 032) R = Plastic DIP (300 mil) (PDWo28) SPEED OPTION -25 = 25nsta -35 = 35nsta 50 = 50nsta DEVICE NUMBER/DESCRIPTION Am7200 High Density First-In First-Out (FIFO) 256 x 9-Bit CMOS Memory Valid Combinations Valid Combinations ‘AM7200-25 Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- ‘AM7200-35 PC, RC, JC cal AMD sales office to confirm availability of specific "AM7200-50 valid combinations, and to check on newly released valid combinations. ‘Am7200 25
Data In (Inputs (9)) Data Out (Outputs (9), Three State) These nine pins are the data inputs to the FIFO. These nine pins are the data outputs for the FIFO. = These pins are in a high impedance state whenever EF Read (R) is HIGH. ‘Empty Flag (Output; Active LOW) Fr The HIGH state of the Empty Flag (EF indicates that the . FIFO contains datato be read. The EFgoes LOWwhen ‘Read (Input; Active LOW) the read pointer is equal to the write pointer, indicating The falling edge of Read (F) initiates a read cycle, ex- that the device is empty. EF LOW inhibits further Read cept when the device is empty, as indicated by the operations. Empty Flag (EF) being LOW. Valid data appears on the TheEF goes HiGHatterthe rising edge ot Write (W) dur- PAH tne Data Gutpus (O08) wil etn toa high ing the first write cycle for an emply FIFO (See Figure 4). Seance condition ‘The EF goes LOW after the falling edge of Read (9) dur- " ing the read cycle which creates the empty condition. RS During a Reset cycle, the EF is driven LOW (active). ‘Fraset (Input; Active LOW) tE The falling edge of Reset (RS) is used to reset the FIFO. During Reset, both the read and write pointers are set to Full Flag (Output; Active LOW) the first location inthe FIFO. Since the reset cycle initial- The HIGH state of the Full Flag (FF) indicates that the _izesthe FIFOto an empty condition, the Empty Flag fe FIFO is capable of accepting data. The FF goes LOW _s driven LOW (active), and both the Half-Full Flag (H when the write pointer is one location less than the read and Full Flag (FF) are driven HIGH (inactive). pointer, indicating that the device isfull. FFLOWinhibits —y, further Write operations. ce The FF goes HIGH atterthe rising edge of Read (Fi) dur POWEr SUPPIY ing the first read cycle following a full condition (See ‘This pin'is the +5 V power supply for the FIFO. Figure 6). The FF goes LOW afer the falling edge of yy Write (W) during the write cycle which creates the full condition. ‘Write (Input; Active LOW) i FFi inacti The falling edge of Write (W) initiates a write cycle, ex- During a Reset cycle, the FF is driven HIGH (inactive). cept when the device is ful, as indicated by the Full Fiag FURT (FF) being LOW. Data is latched into the FIFO on the Firat Load/Retranamil (Input; Active LOW) fising edge of W. This is a dual purpose input, dependent upon whether XT the FIFO is in Single Device Mode or Depth-Expansion Expansion n (Input; Active LOW) Mode Expansion In (Xi) is grounded to indicate operation in This pin acts as a FIRST LOAD (FI) pin when in the __the Single Device or Width-Expansion Modes. In Depth Depth-Expansion Mode. The device receiving data first Expansion Mode, the XIpin is connected to the Expan- will have the FL input tied LOW, while the remaining de-__sion Out (XO) pin of the previous device, except for the vices will have the FLpintied HIGH. The states ofthe FL —_XIpinof the first device which is connected tothe XOpin and Expansion In oo pins are used to determine the _of the last FIFO. FIFO's mode of operation, as shown in Tables 1 and 2. This pin operates at CMOS logic levels, thus providing This pin is used as the Retransmit (RT) input during Sin- noise immunity between cascaded devices. gle Device Mode. The device can be instructed to retransmit the previously written data when RTis pulsed © XO/HF Low. ‘Expansion Out/Halt-Full Flag (Output; Active LOW) GND This is a dual purpose output, dependent upon whether oe Port M 5 n Power Supply, Ground Hie e device is in Single Device Mode or Depth Expansion This pin is the 0 V power supply for the FIFO. This pin operates as an Expansion Out (XO) signal dur- NC ing Depth Expansion Mode. In this mode, the XO pin is. No Connect connected to the Expansion Input (XI) pin of the follow- r ing device, except for the XO pin of the last device which These pins are not connected. is connected to the XI pin of the first device.
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When in Single Device Mode (Expansion In (XI) pin _ HIGHatter the rising edge of Fi during the read operation grounded) this output operates as a Half-Full Flag (HF). which eliminates the half-full condition (See Figure 5). Atter half the FIFO has been filled, the HF will be set . ne inacti LOW at the falling edge of the next Write (W) operation. uring a Reset cycle, the HF is driven HIGH (inactive). The HF will remain LOW untilthe difference betweenthe This pin operates at CMOS logic levels, thus providing write pointer and read pointeristessthanorequaltoone noise immunity between cascaded devices. half of the total memory of the FIFO. The HF will go Am7200 27
address pointers. The flag logic prevents illogical writes ing edge of Wwill be stored sequentially in the FIFO. data-in and data-out lines of the Am7200 are connected Vertlow situations. automaticaly enabled and disabled through the hand FEO twer after the rising edge of FF (see Figure 9). (W) signals must be HIGH trss prior to andtrsrafterthe sion Mode but is not active. Ss. which eliminates the half-full condition. (See Figure 5). tess ates an emety condition. (See Figure 4.) An empty con. ing a data underflow situation. ome LITT TTT TTT TTL TTT A special case of read occurs when a read operation is. tosoar-s __ til tape after the rising edge of EF (see Figure 8). Figure 2. Reset Timing
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Table 1. Reset and Retransmit Truth Table 1, Flags will change to show correct state according to write pointer.
- Pointers will increment only it corresponding flag is HIGH at the beginning of the cycle.
Table 2. Reset and First Load Truth Table
- Xlis connected to XO of previous device. See Figure 14.
- Same as during Reset Cycle.
- Pointers will increment only if corresponding flag is HIGH at the beginning of the cycle.
Figure 8. Read Data Flow-Through Mode
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Figure 12. Single FIFO Configuration Figure 13. Width-Expansion to Form a 256 x 18 FIFO Figure 14. Depth-Expansion to Form 768 x 9 FIFO Figure 15. FIFO Array Using Both Width-Expansion and
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ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Ambient Temperature with upply Voltage, (Veo) * Storage Temperature 55°C to +150°C _tionalliy of the device is guaranteed. DC Output Current voeeeeeee reese, SOMA Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maxi- mum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified ‘Am7200-25 | Am7200-35 | Am7200-50 Parameter| ta=25ns | ta=35ns | ta=50ns Symbol’ | Parameter Description [nt | wn] wa in Input Leakage Current (any inpui) (Note) —1 [4 [1 [a [a 4 [ua] Output Leakage Current (data outputs) -10] 10 | pA (Note 2) Vig Input High Voltage (all inputs except Xl) Vv (Note 3) Vie Input Low Voltage (all inputs except XI) Vv (Note 3) Input High Voltage, XI (Note 3) [ss] [as{ [ast |v Input Low Voltage, XI (Note 3) | [ss] [rst [ist v | Output Logic“1"Vortage lon=-2ma__[24[ [aa feat | v | CuiputLogic“O"Vottagela=ema | fost [os] fo] v | lec: | Average Vec Power Supply Current 70 (Note 4) lece | Average Standby Current mA (R= W= RS = FLIRT = Vin) (Note 4) lees Power Down Current mA (all inputs = Voc ~ 0.2 V) (Note 4) Notes: 1. Measurements with GND Vin s Voc 2. R2 Vin, GND < Vout < Vcc. 3. Vic and Vix are input conditions of output tests and are not themselves directly tested. Vit and Vin are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 4, loc measurements are made with outputs open. Am7200 215
SWITCHING CHARACTERISTICS over COMMERCIAL operating range unless otherwise specifie rene [ars anrasoasT anvaoeso] [mt eaametoescpion [res nM [i [two —|wite cyceTime | 3 |] [*{ [@] [rel [cwrw [wine Puce wan | spas] [asf [so[ | ns | [twa Wate Recovey Tme | 3 [off op [sf [as [tos JoataSewptime | sa [as[ | [ [oo] [rs | [tr oatarogtime | ss [of [ol |[s| [ns] [wr |wite Lowtoruiragiow [ea | [asl [el [| ns | [ter Jwete LOW ioHarrulFlgtow| sf [38 [4s [ [65 [ns | [incr |wite HIGH Empty FagHiGh | a8 | [es | 90 {| 45 | ns | a a at LOW Z (Note 1) [wer [Write Pulse WisthanerFFHiGH | 9 | 2s[ | as{ [so[ | ns | [tro [Read Gycetime «| 3 | sf [ast Test [ns | [un [acsoss Tine saws Las] [ost [50 [ns] [ime [ReadRecovey tine | 9 [wl [ol [asl [ns] [wow |Reaarutewan | s_|as[ fos[ [so[ [ns Perera TTL at LOW Z (Note 4 [tor [ata vatatromneadPusenicn| a fs] | s{ | s{ [ns] [w= lewimnucyeowes [oT Tet fet [ele at HIGH Z (Note 4 [tw [Read HiGHioFulrlagwich | 69 | | 25] [sof | 45 [ns | [Cine [reas HIGH Hat-FulfFiag Gels | [os | 5] | 65 | ns | [tm [Read LOW to Empiy Flag iow [a8 | [25 | | 30 { | 45 [ns] | wwe [Read Puse Wan atereFHiGA |e | =s[ Lest [eel [ns] [tnso [Reset yee Time | 2 |] [| [es] [rs] [tas [Reset Puisewietn | 2 | 25 [as { [sof | ns | [tase [Reset SeupTime | 2 | 25{ [as { sof [ns | [insn [Reset Recover Time | 2 | 10{ [wl [5 { | ns] [ten [ResettoEmpyfiagtow | 2 [| [as [as [I 6s | ns | [ew [Resettorat-rut Fagrign [2 [| as[ [| | 65 | ns | [ten [ResettoFullFlagHigH [2 [ [3s[ [as [ [65 [ns | [tare [RetransmitCycieTime 7 [as] Tas[ [est [ns | [ter [Retransmit Pulse with | 7 [a5 fas [ [sof | ns | [irs [Retransmit Setup Time Note2) [| 7 [25 as[ [so] [ns | [ine |Retransmtrecoven tine [7 | o[ [wf fis [ [ne Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected 2. Values are guaranteed by design and are not currently tested.
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AMD Ps] SWITCHING CHARACTERISTICS (continued) sym [eerameterDeserition __|rgues mn max nn Math Mas unt [vo [Reacts xOiow [0] ST [S> [sp [or [Reeawitei XOHIGH | 10 | Pas | [os | | s0 [ns | [ta [xiPuise wien ote) | as fase S | [ne Pa ecoveny Tine wWoiea) [ar -ao f —P10][10 | Pr J [cus aseuptine ist fof fof [wo] [re | Notes: 1, These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. 2. Values are guaranteed by design and are not currently tested. . Am7200 217
- Includes jig and scope capacitances.
Figure 17. AC Test Load Symbol | Parameter Description (Note 1)_| Test Conditions Typ.
- These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is