AM70PDL129CDH66IT

AM70PDL127CDH AMD | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am70PDL127CDH/ Am70PDL129CDH Data Sheet Publication Number 30651 Revision A Amendment +2 Issue Date November 24, 2003

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 30651 Rev: A Amendment +2 Issue Date: November 24, 2003 Refer to AMD’s Website (www.amd.com) for the latest information. Am70PDL127CDH/Am70PDL129CDH Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP) 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and

64 Mbit (4 M x 16-Bit) CMOS Pseudo Static RAM

DISTINCTIVE CHARACTERISTICS MCP Features ■ Consists of Am29PDL127H/Am29PDL129H, 64 Mb pSRAM and two Am29LV640M. ■ Power supply voltage of 2.7 to 3.1 volt ■ High performance (XIP) — Access time as fast as 65 ns initial / 25 ns page ■ High performance (Data Storage) — Access time as fast as 110 ns initial / 30 ns page ■ Package — 93-Ball FBGA ■ Operating Temperature — –40°C to +85°C Flash Memory Features (XIP) AM29PDL127H/AM29PDL129H ARCHITECTURAL ADVANTAGES ■ 128 Mbit Page Mode device — Page size of 8 words: Fast page read access from random locations within the page ■ Dual Chip Enable inputs (PDL129 only) — Two CE# inputs control selection of each half of the memory space ■ Single power supply operation — Full Voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications ■ Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations ■ FlexBank Architecture — 4 separate banks, with up to two simultaneous operations per device PDL127: — Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) — Bank B: 48 Mbit (32 Kw x 96) — Bank C: 48 Mbit (32 Kw x 96) — Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31) PDL129: — Bank 1A: 48 Mbit (32 Kw x 96) — Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31) — Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) — Bank 2B: 48 Mbit (32 Kw x 96) ■ SecSi TM (Secured Silicon) Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words ■ Both top and bottom boot blocks in one device ■ Manufactured on 0.13 µm process technology ■ 20-year data retention at 125°C ■ Minimum 1 million erase cycle guarantee per sector PERFORMANCE CHARACTERISTICS ■ High Performance — Page access times as fast as 25 ns — Random access times as fast as 65 ns ■ Power consumption (typical values at 10 MHz) — 45 mA active read current — 25 mA program/erase current — 1 µA typical standby mode current SOFTWARE FEATURES ■ Software command-set compatible with JEDEC 42.4 standard — Backward compatible with Am29F and Am29LV families ■ CFI (Common Flash Interface) complaint — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Erase Suspend / Erase Resume — Suspends an erase operation to allow read or program operations in other sectors of same bank ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data

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■ WP#/ACC (Write Protect/Acceleration) input —A t V IL, hardware level protection for the first and last two 4K word sectors. —A t V IH, allows removal of sector protection —A t V HH, provides accelerated programming in a factory setting FLASH MEMORY FEATURES (DATA STORAGE) AM29LV640M ARCHITECTURAL ADVANTAGES ■ Single power supply operation — 3 V for read, erase, and program operations ■ Manufactured on 0.23 µm MirrorBit process technology ■ SecSi™ (Secured Silicon) Sector region — 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer ■ Flexible sector architecture — One hundred twenty-eight 32 Kword sectors ■ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection ■ Minimum 100,000 erase cycle guarantee per sector ■ 20-year data retention at 125 PERFORMANCE CHARACTERISTICS ■ High performance — 110 ns access time — 30 ns page read times — 0.5 s typical sector erase time — 22 µs typical effective write buffer word programming time: 16-word write buffer reduces overall programming time for multiple-word updates — 4-word page read buffer — 16-word write buffer ■ Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current SOFTWARE & HARDWARE FEATURES ■ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices ■ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: V ID-level method of changing code in locked sectors — WP#/ACC input: Write Protect input (WP#) protects first or last sector regardless of sector protection settings ACC (high voltage) accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 3 ADVANCE INFORMATION pSRAM Features ■ Power dissipation — Operating: 35 mA maximum — Standby: 80 µA maximum — Deep power-down standby: 20 µA ■ Data retention supply voltage: 2.7 to 3.1 V ■ Power down features using CE#1s and CE2s ■ CE1s# and CE2s Chip Select ■ Byte data control: LB#s (DQ7-DQ0), UB#s (DQ15-DQ8)

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GENERAL DESCRIPTION (PDL129) The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V V PP is not required for write or erase operations. The device offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to oper- ate without wait states. To eliminate bus contention the de- vice has separate chip enable (CE#f1, CE#f2), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit mem- ory space. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Page Mode Features The page size is 8 words. After initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.1 V) for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard . Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. Device programming occurs by executing the program com- mand sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. Device erasure occurs by execut- ing the erase command sequence. The host system can detect whether a program or erase op- eration is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power con- sumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Chip Enable Configuration CE#f1 Control CE#f2 Control Bank 1A

48 Mbit (32 Kw x 96)

16 Mbit (4 Kw x 8 and 32 Kw x 31)

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 5 ADVANCE INFORMATION GENERAL DESCRIPTION (PDL127) The Am29PDL127H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V V PP is not required for write or erase operations. The device offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to oper- ate without wait states. To eliminate bus contention the de- vice has separate chip enable (CE#f1), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Page Mode Features The page size is 8 words. After initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.1 V) for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard . Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. Device programming occurs by executing the program com- mand sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. Device erasure occurs by execut- ing the erase command sequence. The host system can detect whether a program or erase op- eration is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power con- sumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Bank Sectors A 16 Mbit (4 Kw x 8 and 32 Kw x 31) B 48 Mbit (32 Kw x 96) C 48 Mbit (32 Kw x 96) D 16 Mbit (4 Kw x 8 and 32 Kw x 31)

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Table 5. SecSi Table 8. Am29PDL127H Boot Sector/Sector Block Addresses for Pro- Table 9. Am29PDL129H Boot Sector/Sector Block Addresses for Pro- Table 10. Am29PDL129H Boot Sector/Sector Block Addresses for Figure 1. In-System Sector Protection/

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Figure 24. Sector Group Protect and Unprotect Timing Diagram . 119 Figure 25. Alternate CE# Controlled Write (Erase/Program)

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 9 ADVANCE INFORMATION PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am70PDL127CDH/Am70PDL129CDH Speed Option Standard Voltage Range: VCC = 2.7–3.1 V Flash Memory (XIP) Pseudo SRAM Flash Memory (Data Storage) 66 85 66 85 66 85 Max Access Time, ns 65 85 70 70 110 110 Page Access Time, ns 25 30 N/A N/A 30 30 CE#f1 Access, ns 65 85 70 70 110 110 OE# Access, ns 25 30 35 35 30 30 VSSVCCps RESET# WE# OE# CE1#ps LB#s UB#s WP#/ACC CE2ps

64 MBit

128 MBit

(XIP) Am29PDL127H/ Am29PDL129H DQ15 to DQ0 DQ15 to DQ0 A21 to A0 (A22) A21 to A0 CE#f1 RY/BY#A21 to A0 (A22 PDL127 only) DQ15 to DQ0CE#f2 (PDL129 only) VSSVCCf RESET#ds WP#/ACCds CE#1ds (Data Storage) Am29LV640MH (Data Storage) Am29LV640MH CE#2ds VSSVCCQds VSSVCCQds RY/BY#ds RY/BY#ds DQ15 to DQ0 DQ15 to DQ0 A21 to A0 A21 to A0

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CONNECTION DIAGRAM–PDL129H Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC CE#2dsV CCQf NC CE#f1 CE#1ps V SS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 CE#f2 WP#/ACC RESET# RY/BY# DQ3 V CCf DQ11 VCCds WE# CE2ps A20 DQ4 VCCps VCCQds A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 NC DQ15 DQ7 DQ14 A15 A21 NC A16 V CCf VSS NC NC NC NC NC NC Flash 1 Only NC NC RY/BY#ds CE#1ds B3 B4 B7 B8 VSSds NC RESET#ds NC NC NC NC NC L2 L3 L4 NC NC NC V SSds L7 L8 NC NC WP#/ACCds NC MirrorBit Only RAM Only Flash Shared Only 93-Ball FBGA Top View

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 11 ADVANCE INFORMATION CONNECTION DIAGRAM–PDL127H Special Package Handling Instructions Special handling is required for Flash Memory prod- ucts in molded packages (BGA). The pack age and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC CE#2dsV CCQf NC CE#f1 CE#1ps V SS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 NC WP#/ACC RESET# RY/BY# DQ3 V CCf DQ11 VCCds WE# CE2ps A20 DQ4 VCCps VCCQds A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 NC DQ15 DQ7 DQ14 A15 A21 A22 A16 V CCf VSS NC NC NC NC NC NC Flash 1 Only NC NC RY/BY#ds CE#1ds B3 B4 B7 B8 VSSds NC RESET#ds NC NC NC NC NC L2 L3 L4 NC NC NC V SSds L7 L8 NC NC WP#/ACCds NC MirrorBit Only RAM Only 93-Ball FBGA Top View

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A21–A0 = 22 Address Inputs (Common) A22 = Address Input (PDL127 only) (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash) CE#f2 = Chip Enable 2 (Flash) (PDL129 Only) CE#1ps = Chip Enable 1 (pSRAM) CE2ps = Chip Enable 2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output and open drain. When RY/BY# = VIH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an em- bedded algorithm or the device is executing a hardware reset opera- tion. UB#s = Upper Byte Control (pSRAM) LB#s = Lower Byte Control (pSRAM) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Write Protect/Acceleration Input. When WP/ACC#= V IL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= V IH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ACC#= 12V , program and erase operations are accelerated. V CCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) V CCs = pSRAM Power Supply VSS = Device Ground (Common) ds = Data Storage NC = Pin Not Connected Internally CE#1ds = Chip Enable 1 (Am29LV640MH Flash- Data Storage) CE#2ds = Chip Enable 2 (Am29LV640MH Flash- Data Storage) RY/BY# = READY/BUSY Output (Data Stor- age) RESET#ds = Hardware Reset Pin, Active Low (Data Storage) WP#/ACCds = Write Protect/Acceleration Input (Data Storage) LOGIC SYMBOL DQ15–DQ0 A21–A0 CE#f1 OE# WE# RESET# UB#s RY/BY# WP#/ACC LB#s CE#1ps CE2ps CE#f2 (PDL129 Only) A22 (PDL127 Only) CE#2ds RESET#ds CE#1ds WP#/ACCds RY/BY#ds

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 13 ADVANCE INFORMATION

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. A m 7 0 P D L 1 2 7C DH6 6I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) SPEED OPTION See “Product Selector Guide” on page 9. PROCESS TECHNOLOGY H = 0.13 µm (Am29PDL127H and Am29PDL129H)

128 Mb DATA STORAGE

(2 x Am29LV640M) PSEUDO SRAM DEVICE DENSITY C = 64 Mbits CONTROL PINS 7 = 1 CE Flash 9 = 2 CE Flash AMD DEVICE NUMBER/DESCRIPTION Am70PDL127CDH/Am70PDL129CDH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM, and 128 Mbit data storage. Valid Combinations Order Number Package Marking Am70PDL127CDH66I T, S M700000004 Am70PDL127CDH85I T, S M700000005 Am70PDL129CDH66I T, S M700000006 Am70PDL129CDH85I T, S M700000007

14 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Device Bus Operations

1. Other operations except for those indicated in this column are
2. Do not apply CE#f1 or 2 = V IL, CE#1ps = VIL and CE2ps = VIH at
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V IL, the boot sectors will be protected. If WP#/ACC

= VIH the boot sectors protection will be removed.

1. The sector protect and sector unprotect functions may also be

Block Protection and Unprotection” section.

1. If WP#/ACC = V IL, the two outermost boot sectors remain
2. Data will be retained in pSRAM.
3. Data will be lost in pSRAM.
4. Both CE#f1 inputs may be held low for this operation.

0.3 V H High-Z High-Z

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mand is necessary in this mode to obtain array data. specifications and to Figure 12 for the timing diagram. tive current specification for reading array data. microprocessor supplying the specific word location. A2 to A0 to select the specific word within that page. Table 2. Page Select Table 3. Bank Select (PDL129H) Table 4. Bank Select (PDL127H)

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 17 ADVANCE INFORMATION Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f1 or CE#f2 (PDL 129 only) to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Pro- gram Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 4 indicates the address space that each sector occupies. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase op- eration. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The Flash AC Characteristics section contains timing specifica- tion tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin should be raised to V CC when not in use. That is, the WP#/ACC pin should not be left float- ing or unconnected; inconsistent behavior of the de- vice may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Command Se- quence sections for more information. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f1, CE#f2 (PDL129 only) and RESET# pins are all held at V IO ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE#f1, CE#f2 (PDL129 only), and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 150 ns. The automatic sleep mode is independent of the CE#f1/CE#f2 (PDL129 only), WE#, and OE# con- trol signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always avail- able to the system. Note that during automatic sleep mode, OE# must be at V IH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification.

18 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 6. Am29PDL127H Sector Architecture

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Table 6. Am29PDL127H Sector Architecture (Continued)

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Table 7. Am29PDL129H Sector Architecture

Table 7. Am29PDL129H Sector Architecture (Continued)

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Table 8. Am29PDL127H Boot Sector/Sector Block

Table 9. Am29PDL129H Boot Sector/Sector Block Table 10. Am29PDL129H Boot Sector/Sector

36 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

The Am29PDL127H/Am29PDL129H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sec- tor groups are permitted. WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129. The WP# Hardware Protection feature is always available, regardless of which of the other two methods are cho- sen. Selecting a Sector Protection Mode The device defaults to the Persistent Sector Protection mode. However, to prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Per- sistent Sector Protection Mode into the Password Pro- tection Mode, it is recommended that either of two one-time programmable non-volatile bits that perma- nently define which sector protection method be set before the device is first programmed . The Persis- tent Sector Protection Mode Locking Bit perma- nently sets the device to the Persistent Sector Protection mode. The Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is pro- tected or unprotected. See Autoselect Command Se- quence for details. Persistent Sector Protection The Persistent Sector Protection method replaces the

12 V controlled protection method in previous AMD

flash devices. This new method provides three differ- ent sector protection states: ■ Persistently Locked—The sector is protected and cannot be changed. ■ Dynamically Locked—The sector is protected and can be changed by a simple command. ■ Unlocked—The sector is unprotected and can be changed by a simple command. To achieve these states, three types of “bits” are used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is as- signed to a maximum four sectors (see the sector ad- dress tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits ( PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB re- quires erasure, the device must be instructed to pre- program all of the sector PPBs prior to PPB erasure. Otherwise, a previously er ased sector PPBs can po- tentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a glo- bal volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are change- able. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is de- faulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and un- protected conditions. This allows software to easily protect sectors against inadvertent changes yet does

limited to 100 erase cycles. clear the PPB Lock is to go through a power cycle. tection during system initialization. vice operates normally again. Table 11. Sector Protection Schemes whether or not the sector is protected or unprotected. DYB/PPB/PPB lock verify command to the device. place the device in password protection mode.

000 Unprotected—PPB and DYB are

001 Unprotected—PPB not

38 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

ences between the Persistent Sector Protection and the Password Sector Protection Mode: ■ When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. ■ The only means to clear the PPB Lock bit is by writ- ing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the pass- word is permanently set with no means to read, pro- gram, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the pass- word. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password re- gion, the customer may perform Password Verify oper- ations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to re- verse this function. 2. Disables all further commands to the password re- gion. All program, and read operations are ignored. Both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Lock- ing Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Pass- word Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify com- mand from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129 with- out using V ID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts V IL on the WP#/ACC pin, the de- vice disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously pro- tected or unprotected. If the system asserts V IH on the WP#/ACC pin, the de- vice reverts to whether sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129 were last set to be protected or unprotected. That is, sector protection or unprotection for these sec- tors depends on whether they were last protected or unprotected using the method described in High Volt- age Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Lock- ing Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONL Y means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Suc- cessful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set.

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 39 ADVANCE INFORMATION If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set com- mand. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persis- tent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be imple- mented using programming equipment. The proce- dure requires high voltage (V ID) to be placed on the RESET# pin. Refer to Figure 1 for details on this pro- cedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.

40 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

42 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Figure 3. PDL127/9H SecSi Sector Protection Algorithm

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 43 ADVANCE INFORMATION Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low V CC Write Inhibit When V CC is less than V LKO, the device does not ac- cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE#, CE#f1, CE#f2 or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f1 =CE#f2 = V IH or WE# = V IH. To initiate a write cycle, CE#f1/CE#f2 and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f1 = V IL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12–15. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is exe- cuting an Embedded Program or embedded Erase al- gorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 12–15. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alterna- tively, contact an AMD representative for copies of these documents.

44 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 12. CFI Query Identification String Table 13. System Interface String

Table 14. Device Geometry Definition

46 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 15. Primary Vendor-Specific Extended Query

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 47 ADVANCE INFORMATION COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 16 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. A reset com- mand is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f1/CE#f2 (PDL129H only), whichever happens later. All data is latched on the rising edge of WE# or CE#f1/CE#f2 (PDL129H only), whichever happens first. Refer to the Flash AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the MCP Device Bus Operations section for more informa- tion. The Read-Only Operations – Am29PDL127H and Read-Only Operations – Am29PDL127H tables pro- vide the read parameters, and Figure 12 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Table 16 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 4 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).

48 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. The SecSi Sector is not ac- cessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 16 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Sili- con) Sector Flash Memory Region” for further informa- tion. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is en- abled. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 16 shows the address and data requirements for the program command se- quence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. Note that the SecSi sector, autoselect, and CFI functions are unavailable when the SecSi Sector is enabled. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 16 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figures 12 and 13 for timing diagrams.

50 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

reading array data, to ensure data integrity. and Figure 14 section for timing diagrams. Figure 5. Erase Operation period during the sector erase command sequence. writing the Erase suspend command. if a sector is actively erasing or is erase-suspended. mation on these status bits. just as in the standard Word Program operation. pend mode, and is ready for another valid operation. pended bank is required when writing this command. Further writes of the Resume command are ignored. the chip has resumed erasing.

1. See Table 16 for erase command sequence.
2. See the section on DQ3 for information on the sector

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 51 ADVANCE INFORMATION of the password when programming. There are no pro- visions for entering the 2-cycle unlock cycle, the pass- word program command, and all the password data. There is no special addressing order required for pro- gramming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset com- mand to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verifi- cation. The Password Program Command is only ca- pable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remain- ing as a “0”. The password is all ones when shipped from the factory. All 64-bit password combinations are valid as a password. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will al- ways drive all F’s onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device will not oper- ate in Simultaneous Operation when the Password Verify command is executed. Only the password is re- turned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Per- sistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Pass- word Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Com- mand should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. SecSi Sector Protection Bit Program Command The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which pre- vents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as pro- grammed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the V CC-level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully exe- cuted. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the Password Unlock command is executed. Upon set- ting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command (only in the Persistent Protection Mode). DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits A22-A12 for PDL127 and (A21–A12) for PDL129H are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored dur- ing the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hard- ware reset. Exiting the DYB Write command is accom- plished by writing the Read/Reset command.

52 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. Once the Password Unlock command is entered, the RY/BY# indicates that the device is busy. Approxi- mately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock com- pletes (RY/BY# is not low or DQ6 does not toggle when read), the next part of the password is written. The system must thus monitor RY/BY# or the status bits to confirm when to write the next portion of the password. Seven cycles are required to successfully clear the PPB Lock Bit. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually pro- grammed (but is bulk erased with the other PPBs). The specific sector address (A21–A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been pro- grammed with margin. If the PPB has been pro- grammed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs be- yond 100 cycles is not guaranteed. The PPB Program command does not follow the Em- bedded Program algorithm. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually eras- ing a specific PPB. Unlike the PPB program, no spe- cific sector address is required. However, when the PPB erase command is written all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the com- mand will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-era- sure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is pro- tected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, remov- ing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. PPB Lock Bit Set Command The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sec- tor is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the com- mand is written. PPB Status Command The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. PPB Lock Bit Status Command The programming of the PPB Lock Bit for a given sec- tor can be verified by writing a PPB Lock Bit status ver- ify command to the device. Sector Protection Status Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sec- tor Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group.

Tables 4 and 5 for more detail. RA = Read Address (A22:A0) (A21:A0 for PDL129). RD = Read Data (DQ15:DQ0) from location RA. autoselect mode) or erasing. write data. Data latched on rising edge of WE#.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. No unlock or command cycles required when bank is reading
6. The Reset command is required to return to reading array (or to

providing status information).

1. Fourth cycle of autoselect command sequence is a read cycle.

section for more information.

1. The data is C0h for factory or customer locked and 80h for factory
2. The data is 00h for an unprotected sector group and 01h for a
3. Device ID must be read across cycles 4, 5, and 6. 20 for

Am29PDL127H and 21 for Am29PDL129H.

1. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode. erase operation, and requires bank address.

1. Program/Erase Resume command is valid only during Erase

Suspend mode, and requires bank address.

1. Command is valid when device is ready to read array data or

when device is in autoselect mode.

1. WP#/ACC must be at VID during the entire operation of command.
2. Unlock Bypass Entry command is required prior to any Unlock

return to the reading array. Table 16. Memory Array Command Definitions

54 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. A21:A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6

in cycle 6, program command must be issued and verified again.

1. Data is latched on the rising edge of WE#.
2. Entire command sequence must be entered for each portion of
3. Command sequence returns FFh if PPMLB is set.
4. The password is written over four consecutive cycles, at
5. A 2 µs timeout is required between any two portions of password.
6. A 100 µs timeout is required between cycles 4 and 5.
7. A 1.2 ms timeout is required between cycles 4 and 5.
8. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
9. DQ1 = 1 if PPB locked, 0 if unlocked.
10. For PDL128G and PDL640G, the WP address is 0111010. The

EP address (PPB Erase Address) is 1111010.

1. Following the final cycle of the command sequence, the user must
2. If checking the DYB status of sectors in multiple banks, the user

must follow Note 17 before crossing a bank boundary. Table 17. Sector Protection Command Definitions

56 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 18 shows the outputs for RY/BY#. is complete, DQ6 stops toggling. Table 18 shows the outputs for Toggle Bit I on DQ6. also the subsection on DQ2: Toggle Bit II. Figure 7. Toggle Bit Algorithm

58 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 18. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

60 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Notes: 1. Valid CE#f1/CE#f2 conditions (PDL129 only): (CE#f1= V IL, CE#f2= VIH) or (CE#f1= VIH, CE#f2= VIL) 2. The I CC current listed is typically less than 5 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 150 ns. Typical sleep mode current is 1 µA. 6. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, OE#, RESET# Input Load Current V CC = VCC max; VID= 12.5 V 35 µA ILR Reset Leakage Current V CC = VCC max; VID= 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2, 3) OE# = VIH, VCC = VCC max (Note 1)

5 MHz 20 30

10 MHz 45 55

ICC2 VCC Active Write Current (Notes 1, 3, 4) OE# = V IH, WE# = VIL 15 25 mA ICC3 VCC Standby Current (Note 3) CE#f1, CE#f2 (PDL129 only), RESET#, WP/ACC# = VIO ± 0.3 V 15 µ A ICC4 VCC Reset Current (Note 3) RESET# = V SS ± 0.3 V, CE# = VSS 15 µ A ICC5 Automatic Sleep Mode (Notes 3, 5) VIH = VIO ± 0.3 V; VIL = VSS ± 0.3 V, CE# = VSS 15 µ A ICC6 VCC Active Read-While-Program Current (Notes 1, 2, 3) OE# = VIH Word 21 45 mA ICC7 VCC Active Read-While-Erase Current (Notes 1, 2, 3) OE# = VIH Word 21 45 mA ICC8 VCC Active Program-While-Erase- Suspended Current (Notes 1, 3, 6) OE# = VIH 17 25 mA VIL Input Low Voltage V IO = 2.7–3.6 V –0.5 0.8 V VIH Input High Voltage V IO = 2.7–3.6 V 2.0 VCC+0.3 V VHH Voltage for ACC Program Acceleration V CC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V VOL Output Low Voltage I OL = 2.0 mA, VCC = VCC min 0.4 V VOH Output High Voltage I OH = –2.0 mA, VCC = VCC min 2.4 V VLKO Low VCC Lock-Out Voltage (Note 6) 2.3 2.5 V

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 61 ADVANCE INFORMATION PSRAM DC CHARACTERISTICS Recommended DC Operating Conditions (Note 1) Notes: 1. T A = -40 to 85°C, otherwise specified. 2. Overshoot: V CC + 1.0 V in case of pulse width ≤ 20 ns. 3. Undershoot: -1.0 V in case of pulse width ≤ 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested. Capacitance (f= 1MHz, TA = 25°C) Note: Capacitance is sampled, not 100% tested. DC and Operating Characteristics Note: Typical values are tested at VCC= 2.9 V, TA= 25°C and not guaranteed. Item Symbol Min Typ Max Unit Supply Voltage V CC 2.7 2.9 3.1 V Ground V SS 000V Input High Voltage V IH 2.2 - VCC + 0.3 (Note 2) V Input Low Voltage V IL -0.3 (Note 3) - 0.6 V Item Symbol Test Condition Min Max Unit Input Capacitance C IN VIN= 0 V - 8 pF Input/Output Capacitance C IO VIO= 0 V - 10 pF Item Symbol Test Conditions Min Typ Max Unit Input Leakage Current I LI VIN= VSS to VCC -1 - 1 µs Output Leakage Current I LO CS#1s= VIH, CS2s= VIH or WE#= VIL, VIO= VSS to VCC -1 - 1 µs Average Operating Current ICC1 Cycle time = 1ms, 100% duty, IIO= 0 mA, CS#1s ≤ 0.2 V, CS2s ≥ VCC ≤ 0.2 V or VIN ≥ VCC-0.2 V -3 07 m A ICC2 Cycle Time = Min, IIO = 0 mA, 100% duty, IIO = 0 mA, CS#1s = VIL, CS2s = VIH, VIN=VIL or VIH -- 3 5 m A Output Low Voltage V OL IOL= 2.1 mA - - 0.4 V Output High Voltage V OH IOH= -1.0 mA 2.4 - - V Standby Current (CMOS) I SB1 CS#1s ≥ VCC-0.2 V, CS2s ≥ VCC-0.2 V, Other inputs= VSS to VCC -- 8 0 µs Deep Power Down I SBD CS2s ≤ 0.2V, Other inputs= VSS to VCC -- 2 0 µs

62 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 19. Test Specifications Figure 10. Test Setup, V IO = 2.7 – 3.1 V Figure 11. Input Waveforms and Measurement Levels

Figure 12. Reset Timings

64 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed JEDEC Std Description 66 85 Unit tAVAV tWC Write Cycle Time (Note 1) Min 65 85 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 35 ns tAHT Address Hold Time From CE#1f or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 30 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 10 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time (CE#f1 to WE#) Min 0 ns tELWL tCS CE#f1 Setup Time Min 0 ns tEHWH tWH WE# Hold Time (CE#f1 to WE#) Min 0 ns tWHEH tCH CE#f1 Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 40 ns tWHDL tWPH Write Pulse Width High Min 25 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 6 µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

66 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”.
2. For PDL129 during CE# transitions the other CE# pin = VIH.

Figure 15. Chip/Sector Erase Operation Timings

68 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

cycle, and array data read cycle. Figure 18. Toggle Bit Timings (During Embedded Algorithms) Figure 19. DQ2 vs. DQ6

Figure 20. Temporary Sector Unprotect Timing Diagram

70 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.
2. For PDL129 during CE#f1 transitions the other CE#f1 pin = V IH.

Figure 21. Sector/Sector Block Protect and

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 71 ADVANCE INFORMATION FLASH AC CHARACTERISTICS Alternate CE#f1 Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed JEDEC Std Description 66 85 Unit tAVAV tWC Write Cycle Time (Note 1) Min 66 85 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 35 ns tDVEH tDS Data Setup Time Min 30 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE#f1 Pulse Width Min 40 ns tEHEL tCPH CE#f1 Pulse Width High Min 25 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 6 µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

72 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SADD = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.

Figure 22. Flash Alternate CE#f1 Controlled Write (Erase/Program) Operation Timings

74 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Note: “X” means don’t care. (Must be low or high state). Absolute Maximum Ratings Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability. CS#1s CS2s OE# WE# LB# UB# I/O 1-8 I/O9-16 Mode Power H H X X X X High-Z High-Z Deselected Standby X L X X X X High-Z High-Z Deselected Deep Power Down L H X X H H High-Z High-Z Deselected Standby L H H H L X High-Z High-Z Output Disabled Active L H H H X L High-Z High-Z Output Disabled Active LH L H L H D OUT High-Z Lower Byte Read Active LH L H H L H i g h - Z D OUT Upper Byte Read Active LH L H L L D OUT DOUT Word Read Active LH X L L H D IN High-Z Lower Byte Write Active L HX LLL D IN DIN Word Write Active Item Symbol Ratings Unit Voltage on any pin relative to VSS VIN, VOUT -0.2 to VCC + 0.3V V Voltage on VCC supply relative to VSS VCC -0.2 to 3.6 V V Power Dissipation P D 1.0 W Storage T emperature T STG -65 to 150 °C Operating Temperature T A -40 to 85 °C

Figure 25. Standby Mode State Machines tWP (min)= 70 ns for continuous write operation over 50 times.

76 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Figure 26. Timing Waveform of Read Cycle 1 Figure 27. Timing Waveform of Read Cycle 2

1. t HZ and tOZ are defined as the time at which the outputs

referenced to output voltage levels.

1. At any given temperature and voltage condition, tHZ (Max) is
2. t OE (Max) is met only when OE# becomes enabled after tAA
3. If invalid address signals shorter than min. tRC are

for min. tRC at least once in every 4 us.

78 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

1. A write occurs during the overlap (t WP) of low CS#1s and low WE#. A write begins when CS#1s goes low and WE# goes low
2. t CW is measured from the CS#1s going low to the end of write.
3. t AS is measured from the address valid to the beginning of write.
4. t WR is measured from the end of write to the address change. tWR is applied in case a write ends with CS#1s or WE# going high.
5. When you toggle CS2s pin low, the device gets into the Deep Power Down mode after 0.5 ms suspend period.
6. To return to normal operation, the device needs Wake-up period.
7. Wake Up sequence is just the same as Power Up sequence.

Figure 30. Timing Waveform of Write Cycle 3

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 79 ADVANCE INFORMATION ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables Table 16 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. T est conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 108 sec Word Program Time 6 210 µs Excludes system level overhead (Note 5) Accelerated Word Program Time 4 120 µs Chip Program Time (Note 3) 50 200 sec Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 11 14 pF COUT Output Capacitance V OUT = 0 12 16 pF CIN2 Control Pin Capacitance V IN = 0 14 16 pF CIN3 WP#/ACC Pin Capacitance V IN = 0 17 20 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

80 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

GENERAL DESCRIPTION (LV640M) The Am29LV640MH is a 64 Mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words. The device has an 8-bit/16-bit bus and can be programmed either in the host system or in standard EPROM programmers. An access time of 110 ns is available. Each device re- quires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) feature pro- vides shorter programming times through increased current on the WP#/ACC input. This feature is in- tended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the device using standard microprocessor write timing. Write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase oper- ation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to deter- mine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin. The protected sector will still be protected even during accelerated programming. The SecSi ™ (Secured Silicon) Sector provides a 128-word area for code or data that can be perma- nently protected. Once this sector is protected, no fur- ther changes within the sector can occur. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

register serve as inputs to the internal state machine. these operations in further detail.

1. Addresses are A21:A0 in word mode.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

1. If WP# = V IL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as
2. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

mand is necessary in this mode to obtain array data. specification on reading array data.

0.3 V XX VCC ±

0.3 V XH X High-Z High-Z

82 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Ad- dress bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to t ACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode ac- cesses are obtained by keeping the “read-page ad- dresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Char- acteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, no ex- ternal pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V IO ± 0.3 V . (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system.

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 83 ADVANCE INFORMATION Refer to the DC Characteristics table for the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V , the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

84 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 2. Sector Address Table

Table 2. Sector Address Table (Continued)

86 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

implemented via two methods. the first sector group unprotect write cycle. tact an AMD representative for details. Table 3. Sector Group Protection/Unprotection

88 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

scribed in “Sector Group Protection and Unprotection”. increased. See the table in “DC Characteristics”. since the WP#/ACC pin has internal pullup to V CC. Figure 1. Temporary Sector Group

1. All protected sector groups unprotected (If WP# = V IL,

the first or last sector will remain protected).

1. All previously protected sector groups are protected

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

90 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

rity of the ESN once the product is shipped to the field. being used to replace devices that are factory locked. dresses normally occupied by the first sector (SA0). sending commands to sector SA0. Table 5 for SecSi Sector addressing. mand sequence. See Command Definitions. space can be modified in any way. without raising any device pin to a high voltage. Sector, follow the algorithm shown in Figure 3. writing within the remainder of the array. Figure 3. SecSi Sector Protect Verify Table 4. SecSi Sector Contents

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 91 ADVANCE INFORMATION for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low V CC Write Inhibit When V CC is less than V LKO, the device does not ac- cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = V IL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 6–9. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 6–9. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alterna- tively, contact an AMD representative for copies of these documents.

92 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 5. CFI Query Identification String

Table 6. System Interface String Table 7. Device Geometry Definition

94 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 8. Primary Vendor-S pecific Extended Query

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 95 ADVANCE INFORMATION non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. See the next section, Reset Command , for more informa- tion. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Pro- gramming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: Note: The device ID is read over three cycles. SA = Sector Address Tables 10 and 11 show the address requirements and codes. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 10 and 11 show the address and data requirements for both command sequences. See also “SecSi (Secured Sili- con) Sector Flash Memory Region” for further informa- tion. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is en- abled. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further Identifier Code A7:A0 (x16) Manufacturer ID 00h Device ID, Cycle 1 01h Device ID, Cycle 2 0Eh Device ID, Cycle 3 0Fh SecSi Sector Factory Protect 03h Sector Protect Verify (SA)02h

96 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 10 and 11 show the address and data requirements for the word/byte pro- gram command sequence, respectively. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status sec- tion for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Tables 10 and 11 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi- ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which pro- gramming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is se- lected by address bits A MAX–A 4. All subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be per- formed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be per- formed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Pro- gram Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming.

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 97 ADVANCE INFORMATION The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data load- ing stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the de- vice for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is re- quired when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device dam- age may result. In addition, no external pullup is nec- essary since the WP#/ACC pin has internal pullup to VCC. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.

98 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Figure 4. Write Buffer Programming Operation

1. When Sector Address is specified, any address in
2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

1. If this flowchart location was reached because

command. if DQ5=1, write the Reset command.

1. See Table 11 for command sequences required for

Figure 5. Program Operation µs maximum (5 µs typical) and updates the status bits. program operation is in progress. Autoselect Command Sequence for more information. written after the device has resume programming. Note: See Table 11 for program command sequence.

100 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Figure 6. Program Suspend/Program Resume chip erase command sequence. of the erase operation by using DQ7, DQ6, or DQ2. mation on these status bits. array data, to ensure data integrity. available when an erase operation is in progress. and Figure 19 section for timing diagrams. ings during these operations. erase operation is in progress.

102 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Table 9. Command Definitions (x16 Mode) RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. pulse, whichever happens later. or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are

bits above DQ7 are don’t care.

1. No unlock or command cycles required when device is in read
2. Reset command is required to return to read mode (or to

providing status information.

1. Fourth cycle of the autoselect command sequence is a read
2. Device ID must be read in three cycles.
3. WP# protects highest address sector, data is 98h for factory

unprotected sector group and 01h for a protected sector group.

1. Total number of cycles in command sequence is determined by

cycles in command sequence is 21.

1. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. Unlock Bypass command is required prior to Unlock Bypass
2. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

1. System may read and program in non-erasing sectors, or enter

command is valid only during a sector erase operation.

1. Erase Resume command is valid only during Erase Suspend
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

104 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev- eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively eras- ing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com- plete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any ad- dress, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approxi- mately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the de- vice enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alterna- tively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.

106 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

termine the status of the operation (top of Figure 9). in the erase-suspend-program mode). device will accept additional sector erase commands. last command might not have been accepted. Table 10. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
3. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

108 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = V IL is ± 5.0 µA. 2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. for these connections is VIO + 0.3 V. 7. V CC voltage requirements. 8. V IO voltage requirements. 9. Includes RY/BY# 10. Not 100% tested. Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT ACC Input Load Current V CC = VCC max 35 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH,

5 MHz 15 20

1 MHz 15 20

ICC2 VCC Initial Page Read Current (2, 3) CE# = V IL, OE# = VIH 30 50 mA ICC3 VCC Intra-Page Read Current (2, 3) CE# = V IL, OE# = VIH 10 20 mA ICC4 VCC Active Write Current (3, 4) CE# = V IL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 15 µ A ICC6 VCC Reset Current (3) RESET# = V SS ± 0.3 V, WP# = VIH 15 µ A ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 15 µ A VIL1 Input Low Voltage 1(6, 7) –0.5 0.8 V VIH1 Input High Voltage 1 (6, 7) 1.9 V CC + 0.5 V VIL2 Input Low Voltage 2 (6, 8) –0.5 0.3 x V IO V VIH2 Input High Voltage 2 (6, 8) 1.9 V IO + 0.5 V VHH Voltage for ACC Program Acceleration VCC = 2.7 –3.3 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.3 V 11.5 12.5 V VOL Output Low Voltage (9) I OL = 2.0 mA, VCC = VCC min = VIO 0.15 x VIO V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V VOH2 IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V VLKO Low VCC Lock-Out Voltage (10) 2.3 2.5 V

110 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

1. See Figure 12 and Table 13 for test specifications.
2. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

0 VRY/BY#

Figure 14. Read Operation Timings

• Figure shows device in word mode. Addresses are A1–A-1 for byte mode.

Figure 15. Page Read Timings

112 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

1. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Description All Speed Options UnitJEDEC Std. Figure 16. Reset Timings

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 113 ADVANCE INFORMATION AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. Parameter All Speed OptionsJEDEC Std. Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 110 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 11 µs Per Word Typ 22 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 8.8 µs Per Word Typ 17.6 µs Single Word/Byte Program Operation (Note 2, 5) Byte Typ 100 µs Word 100 Single Word/Byte Accelerated Programming Operation (Note 2, 5) Byte Typ Word 90 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tBUSY WE# High to RY/BY# Low Min 110 ns

114 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings Figure 18. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. Illustration shows device in word mode.

Figure 19. Chip/Sector Erase Operation Timings

116 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Figure 20. Data# Polling Timings (During Embedded Algorithms)

118 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

1. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Figure 23. Temporary Sector Group Unprotect Timing Diagram

• For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.

Figure 24. Sector Group Protect and Unprotect Timing Diagram

120 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. Parameter Speed OptionsJEDEC Std. Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 110 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 22 µs µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 17.6 µs µs Single Word/Byte Program Operation (Note 2, 5) Word Typ 100 µs Single Word/Byte Accelerated Programming Operation (Note 2, Word Typ 90 µs t WHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tRH RESET# High Time Before Write Min 50 ns

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Illustration shows device in word mode.

122 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 4. For 1-16 words programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 12 and 11 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 15 sec Chip Erase Time 32 128 sec Single Word Program Time (Note 3) Word 100 TBD µs Accelerated Single Word Program Time (Note 3) Word 90 TBD µs Total Write Buffer Program Time (Note 4) 352 TBD µs Effective Write Buffer Program Time (Note 3) Per Word 22 TBD µs Total Accelerated Effective Write Buffer Program Time (Note 4) 282 TBD µs Effective Accelerated Write Buffer PRogram Time (Note 4) Word 17.6 TBD µs Chip Program Time 92 TBD sec Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 123 ADVANCE INFORMATION PACKAGE PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 11 26 pF COUT Output Capacitance V OUT = 0 12 28 pF CIN2 Control Pin Capacitance V IN = 0 14 28 pF CIN3 WP#/ACC Pin Capacitance V IN = 0 17 20 pF

124 Am70PDL127CDH/Am70PDL129CDH November 24, 2003

FUA093—93-Ball Fine-Pitch Grid Array 13 x 9 mm package 3300 \\ 16-038.21a PACKAGE FUA 093 JEDEC N/A 13.00 mm x 9.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.40 PROFILE A1 0.16 --- --- BALL HEIGHT A2 1.06 --- 1.21 BODY THICKNESS D 13.00 BSC. BODY SIZE E 9.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 93 BALL COUNT φb 0.31 --- 0.41 BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A2,A3,A4,A5,A6,A7,A8,A9,C10,D1,D10, DEPOPULATED SOLDER BALLS E1,E10,H1,H10,J1,J10,K1,K10 M2,M3,M4,M5,M6,M7,M8,M9 NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. INDEX MARK 93X C0.15 (2X) (2X) C0.15 B A b 0.20 C C D E PIN A1 C TOP VIEW SIDE VIEW CORNER A 0.08

0.15 M C

0.08 ADCEFGHJKLM B eD CORNER 7SE eE SD BOTTOM VIEW PIN A1

November 24, 2003 Am70PDL127CDH/Am70PDL129CDH 125 ADVANCE INFORMATION REVISION SUMMARY Revision A (August 16, 2003) Initial release. Revision A+1 (September 3, 2003) Connection Diagrams Corrected ball grid labels for balls K9 and L7–L9 on both Am70PDL127CDH and Am70PDL129CDH con- nection diagrams. Revision A+2 (November 24, 2003) Device Information Removed Reference to Page Mode for pSRAM. Distinctive Characteristics, Flash Memory Features (Data Storage) Removed Reference to VIO. Product Selector Guide Corrected pSRAM access times. Operating Ranges Corrected V ccf/Vccs standard voltage range max from 3.3 V to 3.1 V. DC Characteristics Test Condition I OL of VOL updated from 4.0 mA to 2.0 mA. Test Conditions Corrected max voltage from 3.3 V to 3.1 V. SecSi TM (Secured Silicon) Sector Flash Memory Region Customer Lockable Area (64 words): Clarified text under first bullet and added SecSi Sector Protection Algorithm figure. Table 17, Sector Protection Command Definitions Corrected number of cycles for SecSi Protection Bit Status, PPMLB Status, and SPMLB Status to 5 cycles. For these command sequences, inserted a cycle be- fore the final read cycle (RD0). pSRAM AC Characteristics Corrected Speed Bins to 66/85 ns. Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.