AM50DL128CH

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Continuity of Specifications Continuity of Ordering Part Numbers For More Information Am50DL128CH Data Sheet Publication Number 30776 Revision A Amendment 0 Issue Date October 6, 2003

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 30776 Rev: A Amendment/0 Issue Date: October 6, 2003 Refer to AMD’s Website (www.amd.com) for the latest information. Am50DL128CH Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance Access time as fast as 55 ns Package 88-Ball FBGA Operating Temperature –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations Data can be continuously read from one bank while executing erase/program functions in another bank. Zero latency between read and write operations Flexible Bank™ architecture Read may occur in any of the three banks not being written or erased. Four banks may be grouped by customer to achieve desired bank divisions. Manufactured on 0.13 µm process technology SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data Customer lockable: Sector is one-time programmable. Once sector is locked, data cannot be changed. Zero Power Operation Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. Boot sectors Top and bottom boot sectors in the same device Compatible with JEDEC standards Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance Access time as fast as 55 ns Program time: 4 µs/word typical utilizing Accelerate function Ultra low power consumption (typical values) 2 mA active read current at 1 MHz 10 mA active read current at 5 MHz 200 nA in standby or automatic sleep mode Minimum 1 million write cycles guaranteed per sector 20 year data retention at 125°C Reliable operation for the life of the system SOFTWARE FEATURES Data Management Software (DMS) AMD-supplied software manages data programming, enabling EEPROM emulation Eases historical sector erase flash limitations Supports Common Flash Memory Interface (CFI) Program/Erase Suspend/Erase Resume Suspends program/erase operations to allow programming/erasing in same bank Data# Polling and Toggle Bits Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) Hardware method of resetting the internal state machine to the read mode WP#/ACC input pin Write protect (WP#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status Acceleration (ACC) function accelerates program timing Sector protection Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector Temporary Sector Unprotect allows changing data in protected sectors in-system pSRAM Features Power dissipation Operating: 50 mA maximum Standby: 100 µA maximum Deep power-down standby: 5 µA CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 2.7 to 3.3 volt Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) 8-word page mode access

October 6, 2003 A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION Am29DL640H Features The Am29DL640H is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each. Word mode data appears on DQ15–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 55, 70 or 85 ns and is offered in a 88-ball FBGA package. Standard control pins—chip enable (CE#f), write en- able (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors only. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can im- prove overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL640H can be organized as both a top and bottom boot sector configuration. The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, cus- tomer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and soft- ware integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Bank Megabits Sector Sizes Bank 1 8 Mb Eight 4 Kword, Fifteen 32 Kword Bank 2 24 Mb Forty-eight 32 Kword Bank 3 24 Mb Forty-eight 32 Kword Bank 4 8 Mb Eight 4 Kword, Fifteen 32 Kword

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am50DL128CH Speed Options Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory Pseudo SRAM Max Access Time, ns Page Access Time (pSRAM), ns N/A N/A N/A CE#f Access, ns OE# Access, ns VSS VCCs RESET#2 WE# OE# CE1#ps LB# UB# CE#f1 WP#/ACC CE2ps

64 MBit

RY/BY#1 VSS VCCf CE#f2 DQ15 to DQ0 VSSf VCCf RY/BY#2 RESET#1

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH MEMORY BLOCK DIAGRAM VCC VSS Bank 1 Address Bank 2 Address A21–A0 RESET# WE# CE# BYTE# DQ15–DQ0 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Bank 1 X-Decoder OE# BYTE# DQ15–DQ0 Status Control A21–A0 A21–A0 A21–A0 A0–A21 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank 2 X-Decoder Y-gate Bank 3 X-Decoder Bank 4 X-Decoder Y-gate Bank 3 Address Bank 4 Address

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAM Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PLCC, PDIP, SSOP). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. NC NC NC CE#f2 RY/BY#2 VSS NC A11 WE# WP#/ACC LB# NC A19 A12 CE2ps RESET#1 UB# A13 A20 RY/BY#1 A18 A10 A14 NC NC A17 DQ6 NC NC NC A15 A21 NC A16 NC NC DQ1 VSS NC NC NC NC M10 NC A10 NC NC NC DQ13 DQ15 VCCf DQ4 DQ3 DQ9 OE# CE#f1 DQ12 DQ7 VSS VCCps VCCf DQ10 DQ0 CE#1fps DQ5 DQ14 NC NC DQ11 DQ2 DQ8 NC NC NC NC NC VCCf VSS RESET#2 NC Shared Flash 1 only Flash 2 only Flash 1 and 2 shared SRAM only 88-Ball FBGA Top View

October 6, 2003 A D V A N C E I N F O R M A T I O N PIN DESCRIPTION A21–A0 = 22 Address Inputs (Common) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash 1) CE#f2 = Chip Enable 2 (Flash 2) CE1#ps = Chip Enable 1 (pSRAM) CE2ps = Chip Enable 2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY#1 = Ready/Busy Output (Flash 1) RY/BY#2 = Ready/Busy Output (Flash 2) UB# = Upper Byte Control (pSRAM) LB# = Lower Byte Control (pSRAM) RESET#1 = Hardware Reset Pin, Active Low (Flash 1) RESET#2 = Hardware Reset Pin, Active Low (Flash 2) WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) VCCps = pSRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL DQ15–DQ0 A21–A0 CE#f1 OE# WE# RESET#1 UB# RY/BY#1 WP#/ACC LB# CE1#ps CE2ps CE#f2 RESET#2 RY/BY#2

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD or Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am50DL128 C H I T TAPE AND REEL T 7 inches S 13 inches TEMPERATURE RANGE I Industrial (–40°C to +85°C) SPEED OPTION See “Product Selector Guide” on page 5 FLASH PROCESS TECHNOLOGY H 0.13 µm PSEUDO SRAM DEVICE DENSITY C

64 Mbits

AMD DEVICE NUMBER/DESCRIPTION Am50DL128CH Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640H 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode 88-Ball Fine Pitch Ball Grid Array, 11.6 x 8, 0.80 mm pitch package (FTA088) Valid Combinations Order Number Package Marking Am50DL128CH56I T,S M50000004M Am50DL128CH70I M50000004N Am50DL128CH85I M50000004P

October 6, 2003 A D V A N C E I N F O R M A T I O N MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N Table 1. Device Bus Operations—Flash Word Mode Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: Other operations except for those indicated in this column are inhibited. Do not apply CE#f1 or 2 = VIL, CE1#s = VIL and CE2s = VIH at the same time. Active flash is device being addressed. Don’t care or open LB#s or UB#s. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Data will be retained in pSRAM. Data will be lost in pSRAM. 10. CE# inputs on both flash devices may be held low for this operation. Operation (Notes 1, 2) CE#f Active CE#f Inactive CE1#ps CE2ps OE# WE# Addr. LB#s UB#s RESET# WP#/ ACC (Note 5) DQ7– DQ0 DQ15– DQ8 (Note 3) Read from Active Flash (Note 8) L H H H L H AIN X X H L/H DOUT DOUT (Note 9) H L Write to Active Flash (Note 8) L H H H H L AIN X X H (Note 5) DIN DIN (Note 9) H L Standby VCC ± 0.3 V H H X X X X X VCC ± 0.3 V H High-Z High-Z Deep Power-down Standby VCC ± 0.3 V H L X X X X X VCC ± 0.3 V H High-Z High-Z Output Disable (Note 10) L H L H H H X X X H L/H High-Z High-Z H H X X X Flash Hardware Reset (Note 8) X H H X X X X X L L/H High-Z High-Z (Note 9) H L Sector Protect (Notes 6, 10) (Note 8) L H H H H L SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X (Note 9) H L Sector Unprotect (Notes 6, 10) (Note 8) L H H H H L SADD, A6 = H, A1 = H, A0 = L X X VID (Note 7) DIN X (Note 9) H L Temporary Sector Unprotect (Note 8) X H H X X X X X VID (Note 7) DIN High-Z (Note 9) H L Read from pSRAM H H L H L H AIN L L H X DOUT DOUT H L High-Z DOUT L H DOUT High-Z Write to pSRAM H H L H X L AIN L L H X DIN DIN H L High-Z DIN L H DIN High-Z

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH DEVICE BUS OPERATIONS Word Configuration The device is in word configuration, DQ15–DQ0 are active and controlled by CE#f and OE#. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to VIL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the Flash Read-Only Operations table for tim- ing specifications and to Figure 15 for the timing dia- gram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to VIL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Flash Device Bus Operations” for more information. The device features an Unlock Bypass mode to facil- itate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. The “Flash Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The Flash AC Characteristics section contains timing specifica- tion tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to nor- mal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. See “Write Protect (WP#)” on page 18 for related in- formation. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Se- quence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6f and ICC7f in the Zero-Power Flash table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at VCC ± 0.3 V.

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N (Note that this is a more restricted voltage range than VIH.) If CE#f and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de- vice requires standard access time (tCE) for read ac- cess when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3f in the Zero-Power Flash table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5f in the Zero-Power Flash table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4f). If RESET# is held at VIL but not within VSS±0.3 V, the standby cur- rent will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not ex- ecuting (RY/BY# pin is “1”), the reset operation is com- pleted within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the pSRAM AC Characteristics tables for RE- SET# parameters and to Figure 16 for the timing dia- gram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

October 6, 2003 A D V A N C E I N F O R M A T I O N Table 2. Am29DL640H Sector Architecture Bank Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x16) Address Range Bank 1 SA0 0000000000 00000h–00FFFh SA1 0000000001 01000h–01FFFh SA2 0000000010 02000h–02FFFh SA3 0000000011 03000h–03FFFh SA4 0000000100 04000h–04FFFh SA5 0000000101 05000h–05FFFh SA6 0000000110 06000h–06FFFh SA7 0000000111 07000h–07FFFh SA8 0000001xxx 08000h–0FFFFh SA9 0000010xxx 10000h–17FFFh SA10 0000011xxx 18000h–1FFFFh SA11 0000100xxx 20000h–27FFFh SA12 0000101xxx 28000h–2FFFFh SA13 0000110xxx 30000h–37FFFh SA14 0000111xxx 38000h–3FFFFh SA15 0001000xxx 40000h–47FFFh SA16 0001001xxx 48000h–4FFFFh SA17 0001010xxx 50000h–57FFFh SA18 0001011xxx 58000h–5FFFFh SA19 0001100xxx 60000h–67FFFh SA20 0001101xxx 68000h–6FFFFh SA21 0001101xxx 70000h–77FFFh SA22 0001111xxx 78000h–7FFFFh

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N Bank 2 SA23 0010000xxx 80000h–87FFFh SA24 0010001xxx 88000h–8FFFFh SA25 0010010xxx 90000h–97FFFh SA26 0010011xxx 98000h–9FFFFh SA27 0010100xxx A0000h–A7FFFh SA28 0010101xxx A8000h–AFFFFh SA29 0010110xxx B0000h–B7FFFh SA30 0010111xxx B8000h–BFFFFh SA31 0011000xxx C0000h–C7FFFh SA32 0011001xxx C8000h–CFFFFh SA33 0011010xxx D0000h–D7FFFh SA34 0011011xxx D8000h–DFFFFh SA35 0011000xxx E0000h–E7FFFh SA36 0011101xxx E8000h–EFFFFh SA37 0011110xxx F0000h–F7FFFh SA38 0011111xxx F8000h–FFFFFh SA39 0100000xxx F9000h–107FFFh SA40 0100001xxx 108000h–10FFFFh SA41 0100010xxx 110000h–117FFFh SA42 0101011xxx 118000h–11FFFFh SA43 0100100xxx 120000h–127FFFh SA44 0100101xxx 128000h–12FFFFh SA45 0100110xxx 130000h–137FFFh SA46 0100111xxx 138000h–13FFFFh SA47 0101000xxx 140000h–147FFFh SA48 0101001xxx 148000h–14FFFFh SA49 0101010xxx 150000h–157FFFh SA50 0101011xxx 158000h–15FFFFh SA51 0101100xxx 160000h–167FFFh SA52 0101101xxx 168000h–16FFFFh SA53 0101110xxx 170000h–177FFFh SA54 0101111xxx 178000h–17FFFFh SA55 0110000xxx 180000h–187FFFh SA56 0110001xxx 188000h–18FFFFh SA57 0110010xxx 190000h–197FFFh SA58 0110011xxx 198000h–19FFFFh SA59 0100100xxx 1A0000h–1A7FFFh SA60 0110101xxx 1A8000h–1AFFFFh SA61 0110110xxx 1B0000h–1B7FFFh SA62 0110111xxx 1B8000h–1BFFFFh SA63 0111000xxx 1C0000h–1C7FFFh SA64 0111001xxx 1C8000h–1CFFFFh SA65 0111010xxx 1D0000h–1D7FFFh SA66 0111011xxx 1D8000h–1DFFFFh SA67 0111100xxx 1E0000h–1E7FFFh SA68 0111101xxx 1E8000h–1EFFFFh SA69 0111110xxx 1F0000h–1F7FFFh SA70 0111111xxx 1F8000h–1FFFFFh Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x16) Address Range

October 6, 2003 A D V A N C E I N F O R M A T I O N Bank 3 SA71 1000000xxx 200000h–207FFFh SA72 1000001xxx 208000h–20FFFFh SA73 1000010xxx 210000h–217FFFh SA74 1000011xxx 218000h–21FFFFh SA75 1000100xxx 220000h–227FFFh SA76 1000101xxx 228000h–22FFFFh SA77 1000110xxx 230000h–237FFFh SA78 1000111xxx 238000h–23FFFFh SA79 1001000xxx 240000h–247FFFh SA80 1001001xxx 248000h–24FFFFh SA81 1001010xxx 250000h–257FFFh SA82 1001011xxx 258000h–25FFFFh SA83 1001100xxx 260000h–267FFFh SA84 1001101xxx 268000h–26FFFFh SA85 1001110xxx 270000h–277FFFh SA86 1001111xxx 278000h–27FFFFh SA87 1010000xxx 280000h–28FFFFh SA88 1010001xxx 288000h–28FFFFh SA89 1010010xxx 290000h–297FFFh SA90 1010011xxx 298000h–29FFFFh SA91 1010100xxx 2A0000h–2A7FFFh SA92 1010101xxx 2A8000h–2AFFFFh SA93 1010110xxx 2B0000h–2B7FFFh SA94 1010111xxx 2B8000h–2BFFFFh SA95 1011000xxx 2C0000h–2C7FFFh SA96 1011001xxx 2C8000h–2CFFFFh SA97 1011010xxx 2D0000h–2D7FFFh SA98 1011011xxx 2D8000h–2DFFFFh SA99 1011100xxx 2E0000h–2E7FFFh SA100 1011101xxx 2E8000h–2EFFFFh SA101 1011110xxx 2F0000h–2FFFFFh SA102 1011111xxx 2F8000h–2FFFFFh SA103 1100000xxx 300000h–307FFFh SA104 1100001xxx 308000h–30FFFFh SA105 1100010xxx 310000h–317FFFh SA106 1100011xxx 318000h–31FFFFh SA107 1100100xxx 320000h–327FFFh SA108 1100101xxx 328000h–32FFFFh SA109 1100110xxx 330000h–337FFFh SA110 1100111xxx 338000h–33FFFFh SA111 1101000xxx 340000h–347FFFh SA112 1101001xxx 348000h–34FFFFh SA113 1101010xxx 350000h–357FFFh SA114 1101011xxx 358000h–35FFFFh SA115 1101100xxx 360000h–367FFFh SA116 1101101xxx 368000h–36FFFFh SA117 1101110xxx 370000h–377FFFh SA118 1101111xxx 378000h–37FFFFh Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x16) Address Range

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N Note: The address range is A21:A0. Table 3. Bank Address Table 4. SecSi™ Sector Addresses Bank 4 SA119 1110000xxx 380000h–387FFFh SA120 1110001xxx 388000h–38FFFFh SA121 1110010xxx 390000h–397FFFh SA122 1110011xxx 398000h–39FFFFh SA123 1110100xxx 3A0000h–3A7FFFh SA124 1110101xxx 3A8000h–3AFFFFh SA125 1110110xxx 3B0000h–3B7FFFh SA126 1110111xxx 3B8000h–3BFFFFh SA127 1111000xxx 3C0000h–3C7FFFh SA128 1111001xxx 3C8000h–3CFFFFh SA129 1111010xxx 3D0000h–3D7FFFh SA130 1111011xxx 3D8000h–3DFFFFh SA131 1111100xxx 3E0000h–3E7FFFh SA132 1111101xxx 3E8000h–3EFFFFh SA133 1111110xxx 3F0000h–3F7FFFh SA134 1111111000 3F8000h–3F8FFFh SA135 1111111001 3F9000h–3F9FFFh SA136 1111111010 3FA000h–3FAFFFh SA137 1111111011 3FB000h–3FBFFFh SA138 1111111100 3FC000h–3FCFFFh SA139 1111111101 3FD000h–3FDFFFh SA140 1111111110 3FE000h–3FEFFFh SA141 1111111111 3FF000h–3FFFFFh Bank A21–A19 000 001, 010, 011 100, 101, 110 111 Device Sector Size (x8) Address Range (x16) Address Range Am29DL640H 256 bytes 000000h–0000FFh 00000h–0007Fh Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x16) Address Range

October 6, 2003 A D V A N C E I N F O R M A T I O N Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 5). The hardware sector protection feature disables both program and erase operations in any sector. The hard- ware sector unprotection feature re-enables both pro- gram and erase operations in previously protected sectors. Sector protection/unprotection can be imple- mented via two methods. Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector protection/ unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 25 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unpro- tect write cycle. Note that the sector unprotect algo- rithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the tem- porary sector unprotect function is available. See “Temporary Sector Unprotect”. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. It is possible to determine whether a sector is pro- tected or unprotected. See the Sector/Sector Block Protection and Unprotection section for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the de- vice disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Sector A21–A12 Sector/ Sector Block Size SA0 0000000000

8 Kbytes

SA8–SA10 0000001XXX, 0000010XXX, 0000011XXX, 192 (3x64) Kbytes SA11–SA14 00001XXXXX 256 (4x64) Kbytes SA15–SA18 00010XXXXX 256 (4x64) Kbytes SA19–SA22 00011XXXXX 256 (4x64) Kbytes SA23–SA26 00100XXXXX 256 (4x64) Kbytes SA27-SA30 00101XXXXX 256 (4x64) Kbytes SA31-SA34 00110XXXXX 256 (4x64) Kbytes SA35-SA38 00111XXXXX 256 (4x64) Kbytes SA39-SA42 01000XXXXX 256 (4x64) Kbytes SA43-SA46 01001XXXXX 256 (4x64) Kbytes SA47-SA50 01010XXXXX 256 (4x64) Kbytes SA51-SA54 01011XXXXX 256 (4x64) Kbytes SA55–SA58 01100XXXXX 256 (4x64) Kbytes SA59–SA62 01101XXXXX 256 (4x64) Kbytes SA63–SA66 01110XXXXX 256 (4x64) Kbytes SA67–SA70 01111XXXXX 256 (4x64) Kbytes SA71–SA74 10000XXXXX 256 (4x64) Kbytes SA75–SA78 10001XXXXX 256 (4x64) Kbytes SA79–SA82 10010XXXXX 256 (4x64) Kbytes SA83–SA86 10011XXXXX 256 (4x64) Kbytes SA87–SA90 10100XXXXX 256 (4x64) Kbytes SA91–SA94 10101XXXXX 256 (4x64) Kbytes SA95–SA98 10110XXXXX 256 (4x64) Kbytes SA99–SA102 10111XXXXX 256 (4x64) Kbytes SA103–SA106 11000XXXXX 256 (4x64) Kbytes SA107–SA110 11001XXXXX 256 (4x64) Kbytes SA111–SA114 11010XXXXX 256 (4x64) Kbytes SA115–SA118 11011XXXXX 256 (4x64) Kbytes SA119–SA122 11100XXXXX 256 (4x64) Kbytes SA123–SA126 11101XXXXX 256 (4x64) Kbytes SA127–SA130 11110XXXXX 256 (4x64) Kbytes SA131–SA133 1111100XXX, 1111101XXX, 1111110XXX 192 (3x64) Kbytes SA134 1111111000 A21–A12 Sector/ Sector Block Size

October 6, 2003 A D V A N C E I N F O R M A T I O N Figure 2. In-System Sector Protect/Unprotect Algorithms Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Set up sector address Wait 150 µs Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs First Write Cycle = 60h? Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Yes Yes No PLSCNT = 25? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Set up first sector address Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Read from sector address with A6 = 1, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs Data = 00h? Last sector verified? Remove VID from RESET# Write reset command Sector Unprotect complete Yes No PLSCNT = 1000? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No All sectors protected? Yes Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Set up next sector address No Yes No Yes No No Yes No Sector Protect Algorithm Sector Unprotect Algorithm First Write Cycle = 60h? Protect another sector? Reset PLSCNT = 1

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sec- tor unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lock- able version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable de- vices from being used to replace devices that are fac- tory locked. The system accesses the SecSi Sector Secure through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector com- mand sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command se- quence, or until power is removed from the device. On power-up, or following a hardware reset, the device re- verts to sending commands to the first 256 bytes of Sector 0. Note that the ACC function and unlock by- pass modes are not available when the SecSi Sector is enabled. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number will at addresses 000000h–000007h in word mode. The se- cure ESN will be programmed in the next 8 words at addresses 000008h–00000Fh. The device is available preprogrammed with one of the following: ■A random, secure ESN only ■Customer code through the ExpressFlash service ■Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Re- gion without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region com- mand sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.

October 6, 2003 A D V A N C E I N F O R M A T I O N Figure 3. SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 11 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle, CE#f and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 7–10. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is exe- cuting an Embedded Program or embedded Erase al- gorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 7–10. The system must write the reset command to return the de- vice to reading array data. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Al- ternatively, contact an AMD representative for copies of these documents. Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 START RESET# = VIH or VID Wait 1 µs Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write reset command SecSi Sector Protect Verify complete

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N Table 7. CFI Query Identification String Table 8. System Interface String Addresses (Word Mode) Data

Description

Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Addresses (Word Mode) Data VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0003h Typical timeout per single byte/word write 2 N µs 20h 0000h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 0009h Typical timeout per individual block erase 2 N ms 22h 0000h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 0005h Max. timeout for byte/word write 2 N times typical 24h 0000h Max. timeout for buffer write 2 N times typical 25h 0004h Max. timeout per individual block erase 2 N times typical 26h 0000h Max. timeout for full chip erase 2 N times typical (00h = not supported)

October 6, 2003 A D V A N C E I N F O R M A T I O N Table 9. Device Geometry Definition Addresses (Word Mode) Data Device Size = 2 N byte 28h 29h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2 N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 007Dh 0000h 0000h 0001h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N Table 10. Primary Vendor-Specific Extended Query Addresses (Word Mode) Data Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h 0004h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode 4Ah 0077h Simultaneous Operation 00 = Not Supported, X = Number of Sectors (excluding Bank 1) 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 0001h Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom 50h 0001h Program Suspend 0 = Not supported, 1 = Supported 57h 0004h Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks 58h 0017h Bank 1 Region Information X = Number of Sectors in Bank 1 59h 0030h Bank 2 Region Information X = Number of Sectors in Bank 2 5Ah 0030h Bank 3 Region Information X = Number of Sectors in Bank 3 5Bh 0017h Bank 4 Region Information X = Number of Sectors in Bank 4

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 11 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. A reset com- mand is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the pSRAM AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 15 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, how- ever, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Table 11 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SADD). Table 2 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 11 shows the address and data requirements for both command sequences. See also “SecSi™ (Se- cured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock by- pass modes are not available when the SecSi Sector is enabled. Word Program Command Sequence The system may program the device by word. Pro- gramming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. The program address and data are written next, which in turn initiate the Embedded Program algo- rithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 11 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program opera- tion is in progress. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 11 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. (See Table 11). The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.

October 6, 2003 A D V A N C E I N F O R M A T I O N Table 11. Am29DL640H Command Definitions Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SADD = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21–A12 uniquely select any sector. Refer to Table 2 for information on sector addresses. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Address bits A21–A19 select a bank. Refer to Table 3 for information on sector addresses. Notes: See Tables 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. Unless otherwise noted, address bits A21–A12 are don’t cares for unlock and command cycles, unless SADD or PA is required. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information. The device ID must be read across the fourth, fifth, and sixth cycles. 10. The data is 80h for factory locked, 40h for customer locked and 00h for not factory/customer locked. 11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Command Sequence (Note 1) Cycles Bus Cycles (Notes 2–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 6) RA RD Reset (Note 7) XXX Autoselect (Note 8) Manufacturer ID Word 555 AA 2AA (BA)555 (BA)X00 Device ID (Note 9) Word 555 AA 2AA (BA)555 (BA)X01 (BA)X0E (BA)X0F SecSi Sector Factory Protect (Note 10) Word 555 AA 2AA (BA)555 (BA)X03 Sector/Sector Block Protect Verify (Note 11) Word 555 AA 2AA (BA)555 (SADD) X02 Enter SecSi Sector Region Word 555 AA 2AA 555 Exit SecSi Sector Region Word 555 AA 2AA 555 XXX Program Word 555 AA 2AA 555 PA PD Unlock Bypass Word 555 AA 2AA 555 Unlock Bypass Program (Note 12) XXX PA PD Unlock Bypass Reset (Note 13) XXX XXX Chip Erase Word 555 AA 2AA 555 555 AA 2AA 555 Sector Erase Word 555 AA 2AA 555 555 AA 2AA SADD Erase Suspend (Note 14) BA Erase Resume (Note 15) BA CFI Query (Note 16) Word

October 6, 2003 A D V A N C E I N F O R M A T I O N Table 12. Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle N/A No toggle Embedded Erase Algorithm Toggle Toggle Erase Suspend Mode Erase-Suspend- Read Erase Suspended Sector No toggle N/A Toggle Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle N/A N/A

October 6, 2003 A D V A N C E I N F O R M A T I O N ESD Immunity Spansion Flash memory Multi-Chip Products (MCPs) may contain component devices that are developed by FASL LLC ("Spansion components") and component devices that are developed by a third party ("third-party components") Spansion components are tested and guaranteed to the ESD immunity levels listed in the corresponding Spansion Flash memory Qualification Database. Third-party components are neither tested nor guaran- teed by FASL LLC for ESD immunity. However, ESD test results for third-party components may be avail- able from the component manufacturer. Component manufacturer contact information is listed in the Span- sion MCP Qualification Report, when available. The Spansion Flash memory Qualification Database and Spansion MCP Qualification Report are available from AMD and Fujitsu sales offices.

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N FLASH DC CHARACTERISTICS CMOS Compatible Notes: The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. Not 100% tested. CE#f refers to chip enable input of active flash (device being addressed). Typical and maximum current specifications shown are for each flash device. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current VCC = VCC max; RESET# = 12.5 V µA ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current VCC = VCC max, WP#/ACC = VACC max µA ICC1f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Byte Mode

5 MHz

1 MHz

CE#f = VIL, OE# = VIH, Word Mode Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL mA ICC3f Flash VCC Standby Current (Notes 2, 7) VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCCf ± 0.3 V 0.2 µA ICC4f Flash VCC Reset Current (Notes 2, 7) VCCf = VCC max, RESET# = VSS ± 0.3 V, WP#/ACC = VCCf ± 0.3 V 0.2 µA ICC5f Flash VCC Current Automatic Sleep Mode (Notes 2, 4, 7) VCCf = VCC max, VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 µA ICC6f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = VIL, OE# = VIH Byte mA Word ICC7f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH Byte mA Word ICC8f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = VIL, OE#f = VIH mA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 VCC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCCf = VCCs = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCCf = VCCs = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.0 2.5 V

October 6, 2003 A D V A N C E I N F O R M A T I O N pSRAM DC & OPERATING CHARACTERISTICS Notes: 1. VCC – 1.0 V for a 10 ns pulse width. 2. VCC + 1.0 V for a 10 ns pulse width. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC1s Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH, tRC = Min. mA ICC2s Page Access Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH, tPC = Min. mA VOL Output Low Voltage IOL = 1.0 mA 0.4 V VOH Output High Voltage IOH = –0.5 mA V ISB Standby Current (CMOS) CE#1 = VCCS – 0.2 V, CE2 = VCCS – 0.2 V µA IDSB Deep Power-down Standby CE2 = 0.2 V µA VIL Input Low Voltage –0.3 (Note 1) 0.4 V VIH Input High Voltage 2.4 VCC + 0.3 (Note 2) V

October 6, 2003 A D V A N C E I N F O R M A T I O N TEST CONDITIONS Table 13. Test Specifications KEY TO SWITCHING WAVEFORMS 2.7 kΩ CL 6.2 kΩ 3.3 V Device Under Test Note: Diodes are IN3064 or equivalent Figure 12. Test Setup Test Condition 56, 70, 85 Unit Output Load

1 TTL gate

Output Load Capacitance, CL (including jig capacitance) pF Input Rise and Fall Times ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V KS000010-PAL WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 3.0 V 0.0 V 1.5 V 1.5 V Output Measurement Level Input Figure 13. Input Waveforms and Measurement Levels

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N pSRAM AC CHARACTERISTICS CE#s Timing Figure 14. Timing Diagram for Alternating Between Pseudo SRAM to Flash Parameter CE#s Recover Time Min ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 12 and Table 13 for test specifications 3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must be held high during this operation. Figure 15. Read Operation Timings Parameter Std. Unit tAVAV tRC Read Cycle Time (Note 1) Min ns tAVQV tACC Address to Output Delay CE#f, OE# = VIL Max ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max ns tGLQV tOE Output Enable to Output Delay Max ns tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max ns tAXQX tOH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min ns tOEH Output Enable Hold Time (Note 1) Read Min ns Toggle and Data# Polling Min ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Note: CE#f refers to the flash device being reset (either CE#f1 or CE#f2). Figure 16. Reset Timings Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min ns tRPD RESET# Low to Standby Mode Min µs tRB RY/BY# Recovery Time Min ns RESET#1, RESET#2 RY/BY#1, RY/BY#2 RY/BY#1, RY/BY#2 tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#f, OE# tRH CE#f, OE# Reset Timings during Embedded Algorithms RESET#1, RESET#2 tRP tRB

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. 3. CE#f refers to chip enable input of active flash (device being addressed). Parameter Speed JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time Min ns tASO Address Setup Time to OE# low during toggle bit polling Min ns tWLAX tAH Address Hold Time Min ns tAHT Address Hold Time From CE#f or OE# high during toggle bit polling Min ns tDVWH tDS Data Setup Time Min ns tWHDX tDH Data Hold Time Min ns tOEPH Output Enable High during toggle bit polling Min ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min ns tELWL tCS CE#f Setup Time Min ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min ns tWHEH tCH CE#f Hold Time Min ns tWLWH tWP Write Pulse Width Min ns tWHDL tWPH Write Pulse Width High Min ns tSR/W Latency Between Read and Write Operations Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCC Setup Time (Note 1) Min µs tRB Write Recovery Time from RY/BY# Min ns tBUSY Program/Erase Valid to RY/BY# Delay Max ns

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS OE# CE#f Addresses VCCf WE# Data 2AAh SADD tGHWL tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH In Progress Complete tWHWH2 VA VA Erase Command Sequence (last two cycles) Read Status Data RY/BY# tRB tBUSY Notes: 1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”. These waveforms are for the word mode. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must be held high during this operation. Figure 19. Chip/Sector Erase Operation Timings

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Temporary Sector Unprotect Note: Not 100% tested. Parameter All Speed Options JEDEC Std VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min µs RESET# tVIDR VID VSS, VIL, or VIH VID VSS, VIL, or VIH CE#f WE# RY/BY# tVIDR tRSP Program or Erase Command Sequence tRRB Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must be held high during this operation. Figure 24. Temporary Sector Unprotect Timing Diagram

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms 1 µs RESET# SADD, A6, A1, A0 Data CE#f WE# OE# 60h 60h 40h Valid* Valid* Valid* Status Sector/Sector Block Protect or Unprotect Verify VID VIH * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address. Note: CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must be held high during this operation. Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. 3. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). Parameter Speed JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time Min ns tELAX tAH Address Hold Time Min ns tDVEH tDS Data Setup Time Min ns tEHDX tDH Data Hold Time Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time Min ns tEHWH tWH WE# Hold Time Min ns tELEH tCP CE#f Pulse Width Min ns tEHEL tCPH CE#f Pulse Width High Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH AC CHARACTERISTICS tGHEL tWS OE# CE#f WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# DOUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase tBUSY Notes: 1. Figure indicates last two bus cycles of a program or erase operation. PA = program address, SADD = sector address, PD = program data. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must be held high during this operation. 5. Waveforms are for the word mode. Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N pSRAM AC CHARACTERISTICS Read Cycle Notes: 1. tOD, tODo, tBD, and tODW are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. If CE#, LB#, or UB# goes low at the same time or before WE# goes high, the outputs will remain at high impedance. 3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. Figure 27. Pseudo SRAM Read Cycle Parameter Symbol 56, 70 tRC Read Cycle Time Min ns tACC Address Access Time Max ns tCO Chip Enable Access Time Max ns tOE Output Enable Access Time Max ns tBA Data Byte Control Access Time Max ns tCOE Chip Enable Low to Output Active Min ns tOEE Output Enable Low to Output Active Min ns tBE Data Byte Control Low to Output Active Min ns tOD Chip Enable High to Output High-Z Max ns tODO Output Enable High to Output High-Z Max ns tBD Data Byte Control High to Output High-Z Max ns tOH Output Data Hold from Address Change Min ns tPM Page Mode Time Min ns tPC Page Mode Cycle Time Min ns tAA Page Mode Address Access Time Max ns tAOH Page Output Data Hold Time Min ns tRC tACC Addresses A20 to A0 CE#1 CE2 OE# WE# LB#, UB# DOUT DQ15 to DQ0 tCO tOH Fixed High High-Z High-Z tOE tBA tOD tODO tBD Valid Data Out Indeterminate tBE tOEE tCOE

October 6, 2003 A D V A N C E I N F O R M A T I O N pSRAM AC CHARACTERISTICS Notes: 1. tOD, tODo, tBD, and tODW are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. If CE#, LB#, or UB# goes low at the same time or before WE# goes high, the outputs will remain at high impedance. 3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. Figure 28. Page Read Timing Addresses A2 to A0 Addresses A20 to A3 CE#1 CE2 OE# WE# LB#, UB# DOUT DQ15 to DQ0 tPM tRC tPC tPC tBA tOE tBE tCOE tAA tOD tCO tBD tACC tOEE tPC DOUT DOUT DOUT DOUT tAA tAA tODO tOH tAOH tAOH tAOH Fixed High Maximum 8 words

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N pSRAM AC CHARACTERISTICS Write Cycle Notes: 1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied. 2. If OE# is high during the write cycle, the outputs will remain at high impedance. 3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. 4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance. Figure 29. Pseudo SRAM Write Cycle—WE# Control Parameter Symbol 56, 70 tWC Write Cycle Time Min ns tWP Write Pulse Time Min ns tCW Chip Enable to End of Write Min ns tBW Data Byte Control to End of Write Min ns tAW Address Valid to End of Write Min ns tAS Address Setup Time Min ns tWR Write Recovery Time Min ns tODW WE# Low to Write to Output High-Z Max ns tOEW WE# High to Write to Output Active Min ns tDS Data Set-up Time Min tDH Data Hold from Write Time Min ns tCH CE2 Hold Time Min 300 µs tCEH Chip Enable High Pulse Width Min ns tWEH Write Enable High Pulse Width Min ns tWC tWP tAW tWEH tWR tCW tBW Valid Data In tAS tCH tOEW Addresses A20 to A0 WE# CE#1s CE2s LB#, UB# DIN DQ15 to DQ0 DOUT DQ15 to DQO tODW tDS tDH High-Z (Note 1) (Note 3) (Note 4)

October 6, 2003 A D V A N C E I N F O R M A T I O N pSRAM AC CHARACTERISTICS Notes: 1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied. 2. If OE# is high during the write cycle, the outputs will remain at high impedance. Figure 30. Pseudo SRAM Write Cycle—CE#1ps Control tWC Valid Data In tAS tCH Addresses A20 to A0 CE#1ps CE2ps WE# LB#, UB# DIN DQ15 to DQ0 DOUT DQ15 to DQ0 tCW tDS tDH tWP tWR tCEH tBW tBE tODW tCOE High-Z High-Z (Note 1) (Note 1)

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N pSRAM AC CHARACTERISTICS Notes: 1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied. 2. If OE# is high during the write cycle, the outputs will remain at high impedance. Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control tWC Valid Data In Addresses A20 to A0 WE# CE#1 CE2 UB#, LB# DIN DQ15 to DQ0 DOUT DQ15 to DQ0 tDS tWR tWP tCW High-Z High-Z tCH tDH tAS tBW tBE tCOE tODW

October 6, 2003 A D V A N C E I N F O R M A T I O N FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time sec Byte Program Time 150 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 120 µs Word Program Time 210 µs Chip Program Time (Note 3) Word Mode sec Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 pF COUT Output Capacitance VOUT = 0 pF CIN2 Control Pin Capacitance VIN = 0 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C Years 125°C Years

October 6, 2003 Am50DL128CH A D V A N C E I N F O R M A T I O N PHYSICAL DIMENSIONS FTA088—88-Ball Fine-Pitch Grid Array 11.6 x 8 mm 3237 \\ 16-038.14b PACKAGE FTA 088 JEDEC N/A 11.60 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.40 PROFILE 0.25 --- --- BALL HEIGHT 1.00 --- 1.11 BODY THICKNESS D 11.60 BSC. BODY SIZE E 8.00 BSC. BODY SIZE 8.80 BSC. MATRIX FOOTPRINT 7.20 BSC. MATRIX FOOTPRINT MD MATRIX SIZE D DIRECTION ME MATRIX SIZE E DIRECTION n BALL COUNT φb 0.30 0.35 0.40 BALL DIAMETER eE 0.80 BSC. BALL PITCH eD

0.80 BSC

0.40 BSC. SOLDER BALL PLACEMENT A3,A4,A5,A6,A7,A8,B1,B10,C1,C10,D1,D10 DEPOPULATED SOLDER BALLS E1,E10,F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10,M3,M4,M5,M6,M7,M8 NOTES: DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. INDEX MARK L M 88X eD CORNER C 0.15 (2X) (2X) C 0.15 SE B A A B D C E F H G J K eE SD BOTTOM VIEW b 0.20 C C 0.15 0.08 M C M C A B PIN A1 D E PIN A1 C TOP VIEW SIDE VIEW CORNER A 0.08

October 6, 2003 A D V A N C E I N F O R M A T I O N REVISION SUMMARY Revision A (October 6, 2003) Initial release. Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.