AM50DL128CG85IT

AM50DL128CG AMD | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to cu stomers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am50DL128CG Data Sheet Publication Number 26880 Revision A Amendment +2 Issue Date November 7, 2002

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26880 Rev: A Amendment/ +2 Issue Date: November 7, 2002 Refer to AMD’s Website (www.amd.com) for the latest information. Am50DL128CG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode DISTINCTIVE CHARACTERISTICS MCP Features ■ Power supply voltage of 2.7 to 3.3 volt ■ High performance — Access time as fast as 70 ns ■ Package — 88-Ball FBGA ■ Operating Temperature — –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another bank. — Zero latency between read and write operations ■ Flexible Bank architecture — Read may occur in any of the three banks not being written or erased. — Four banks may be grouped by customer to achieve desired bank divisions. ■ Manufactured on 0.17 µm process technology ■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Sector is one-time programmable. Once sector is locked, data cannot be changed. ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ■ Boot sectors — Top and bottom boot sectors in the same device ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast as 70 ns — Program time: 4 µs/word typical utilizing Accelerate function ■ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations ■ Supports Common Flash Memory Interface (CFI) ■ Program/Erase Suspend/Erase Resume — Suspends program/erase operations to allow programming/erasing in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode ■ WP#/ACC input pin — Write protect (WP#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system pSRAM Features ■ Power dissipation — Operating: 50 mA maximum — Standby: 100 µA maximum — Deep power-down standby: 5 µA ■ CE1s# and CE2s Chip Select ■ Power down features using CE1s# and CE2s ■ Data retention supply voltage: 2.7 to 3.3 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) ■ 8-word page mode access

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The Am29DL640G is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each. Word mode data appears on DQ15–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70 or 85 ns and is offered in a 88-ball FBGA package. Standard control pins—chip enable (CE#f), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors only. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can im- prove overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL640G can be organized as both a top and bottom boot sector configuration. The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, cus- tomer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as a one-time programmable area. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and soft- ware integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Bank Megabits Sector Sizes Bank 1 8 Mb Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword Bank 2 24 Mb Forty-eight 64 Kbyte/32 Kword Bank 3 24 Mb Forty-eight 64 Kbyte/32 Kword Bank 4 8 Mb Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword

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November 7, 2002 Am50DL128CG 5 PRELIMINARY PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am50DL128CG Speed Options Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory Pseudo SRAM 70 85 70 85 Max Access Time, ns 70 85 70 85 Page Access Time (pSRAM), ns N/A N/A 30 35 CE#f Access, ns 70 85 70 85 OE# Access, ns 30 40 25 30 VSSVCC s RESET#2 WE# OE# CE1#ps LB# UB# CE#f1 WP#/ACC CE2ps

64 MBit

#2 DQ15 to DQ0 DQ15 to DQ0 RY/BY#1 VSSVCC f CE#f2 DQ15 to DQ0 VSS fVCC f RY/BY#2 RESET#1

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FLASH MEMORY BLOCK DIAGRAM VCC VSS Bank 1 Address Bank 2 Address A21–A0 RESET# WE# CE# BYTE# DQ15–DQ0 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Bank 1 X-Decoder OE# BYTE# DQ15–DQ0 Status Control A21–A0 A21–A0 A21–A0A0–A21 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank 2 X-Decoder Y-gate Bank 3 X-Decoder Bank 4 X-Decoder Y-gate Bank 3 Address Bank 4 Address

November 7, 2002 Am50DL128CG 7 PRELIMINARY CONNECTION DIAGRAM Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PLCC, PDIP , SSOP). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. G3 G4 G5 G6 G7 G8 F3 F4 F5 F6 F7 F8 E3 E4 E5 E6 E7 E8 D3 D4 D5 D6 D7 D8 C3 C4 C5 C6 C7 C8 B3 B4 B5 B6 B7 B8 NC NCNCCE#f2RY/BY#2VSSNC A8 A11WE#WP#/ACCLB#A7NC A19 A12CE2psRESET#1UB#A6A3 A9 A13A20RY/BY#1A18A5A2 A10 A14NCNCA17A4A1 DQ6 NC NC NC A15 A21 NC A16NCNCDQ1V SSA0 NCNC NC NC M10 NC A10 NCNCNC H3 H4 H5 H6 H7 H8 DQ13 DQ15 VCCfDQ4DQ3DQ9OE#CE#f1 J3 J4 J5 J6 J7 J8 DQ12 DQ7 VSSVCCpsVCCfDQ10DQ0CE#1fps K3 K4 K5 K6 K7 K8 DQ5 DQ14 NCNCDQ11DQ2DQ8NC L3 L4 L5 L6 L7 L8 NC NC NCNCVCCfVSSRESET#2NC Shared Flash 1 only Flash 2 only Flash 1 and 2 shared SRAM only 88-Ball FBGA Top View

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A21–A0 = 22 Address Inputs (Common) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash 1) CE#f2 = Chip Enable 2 (Flash 2) CE1#ps = Chip Enable 1 (pSRAM) CE2ps = Chip Enable 2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY#1 = Ready/Busy Output (Flash 1) RY/BY#2 = Ready/Busy Output (Flash 2) UB# = Upper Byte Control (pSRAM) LB# = Lower Byte Control (pSRAM) RESET#1 = Hardware Reset Pin, Active Low (Flash 1) RESET#2 = Hardware Reset Pin, Active Low (Flash 2) WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCC f = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) V CC ps = pSRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL DQ15–DQ0 A21–A0 CE#f1 OE# WE# RESET#1 UB# RY/BY#1 WP#/ACC LB# CE1#ps CE2ps CE#f2 RESET#2 RY/BY#2

November 7, 2002 Am50DL128CG 9 PRELIMINARY

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Am50DL128 C G 70 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) SPEED OPTION See “Product Selector Guide” on page 5 FLASH PROCESS TECHNOLOGY G = 0.17 µm PSEUDO SRAM DEVICE DENSITY C = 64 Mbits AMD DEVICE NUMBER/DESCRIPTION Am50DL128CG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode 88-Ball Fine Pitch Ball Grid Array, 11.6 x 8, 0.80 mm pitch package (FTA088) Valid Combinations Order Number Package Marking Am50DL128CG70I T, S M500000008 Am50DL128CG85I T, S M500000009

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This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1. Device Bus Operations—Flash Word Mode

1. Other operations except for those indicated in this column are
2. Do not apply CE#f1 or 2 = VIL, CE1#s = VIL and CE2s = VIH at the
3. Active flash is device being addressed.
4. Don’t care or open LB#s or UB#s.
5. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC

= VIH the boot sectors protection will be removed.

1. The sector protect and sector unprotect functions may also be

Block Protection and Unprotection” section.

1. Data will be retained in pSRAM.
2. Data will be lost in pSRAM.
3. CE# inputs on both flash devices may be held low for this operation.

0.3 V H High-Z High-Z

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FLASH DEVICE BUS OPERATIONS Word Configuration The device is in word configuration, DQ15–DQ0 are active and controlled by CE#f and OE#. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to V IL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the Flash Read-Only Operations table for tim- ing specifications and to Figure 15 for the timing dia- gram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to V IL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Flash Device Bus Operations” for more information. The device features an Unlock Bypass mode to facil- itate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. The “Flash Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The Flash AC Characteristics section contains timing specifica- tion tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. See “Write Protect (WP#)” on page 18 for related in- formation. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Se- quence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 f and ICC7 f in the table represent the cur- rent specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at V CC ± 0.3 V.

November 7, 2002 Am50DL128CG 13 PRELIMINARY (Note that this is a more restricted voltage range than V IH.) If CE#f and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de- vice requires standard access time (t CE ) for read ac- cess when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 f in the table represents the standby current spec- ification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. I CC5 f in the table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ±0.3 V, the device draws CMOS standby current (ICC4 f). If RESET# is held at VIL but not within VSS ±0.3 V, the standby cur- rent will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not ex- ecuting (RY/BY# pin is “1”), the reset operation is com- pleted within a time of t READY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the pSRAM AC Characteristics tables for RE- SET# parameters and to Figure 16 for the timing dia- gram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

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Table 2. Am29DL640G Sector Architecture

Table 2. Am29DL640G Sector Architecture (Continued)

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Note:The address range is A21:A0. Table 3. Bank Address Table 4. SecSi Sector Addresses

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Table 5. Am29DL640G Boot Sector/Sector Block “Temporary Sector Unprotect”. The device is shipped with all sectors unprotected. AMD representative for details. Protection and Unprotection section for details. one of two provided by the WP#/ACC pin.

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Figure 2. In-System Sector Protect/Unprotect Algorithms

November 7, 2002 Am50DL128CG 21 PRELIMINARY SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sec- tor unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lock- able version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable de- vices from being used to replace devices that are fac- tory locked. The system accesses the SecSi Sector Secure through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector com- mand sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command se- quence, or until power is removed from the device. On power-up, or following a hardware reset, the device re- verts to sending commands to the first 256 bytes of Sector 0. Note that the ACC function and unlock by- pass modes are not available when the SecSi Sector is enabled. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number will at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). The secure ESN will be programmed in the next 8 words at addresses 000008h–00000Fh (or 000010h–000020h in byte mode). The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either V IH or VID. This allows in-system protection of the SecSi Sector Re- gion without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region com- mand sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.

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Figure 3. SecSi Sector Protect Verify and power-down transitions, or from system noise. or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility.

Table 7. CFI Query Identification String Table 8. System Interface String

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Table 9. Device Geometry Definition

Table 10. Primary Vendor-Specific Extended Query

26 Am50DL128CG November 7, 2002

Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 11 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. A reset com- mand is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the pSRAM AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 15 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, how- ever, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Table 11 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SADD). Table 2 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi

November 7, 2002 Am50DL128CG 27 PRELIMINARY Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 11 shows the address and data requirements for both command sequences. See also “SecSi™ (Se- cured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock by- pass modes are not available when the SecSi Sector is enabled. Word Program Command Sequence The system may program the device by word. Pro- gramming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. The program address and data are written next, which in turn initiate the Embedded Program algo- rithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 11 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program opera- tion is in progress. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 11 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. (See Table 11). The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.

28 Am50DL128CG November 7, 2002

Figure 4. Program Operation section for information on these status bits. reading array data, to ensure data integrity. and Figure 19 section for timing diagrams. ings during these operations. time-out period resets that bank to the read mode. quence and any additional addresses and commands. Note:See Table 11 for program command sequence.

30 Am50DL128CG November 7, 2002

Table 11. Am29DL640G Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE#f pulse, whichever happens first. Table 2 for information on sector addresses. bank. Refer to Table 3 for information on sector addresses.

1. See Tables 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A21–A12 are don’t cares for

unlock and command cycles, unless SADD or PA is required.

1. No unlock or command cycles required when bank is reading
2. The Reset command is required to return to the read mode (or to

the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The device ID must be read across the fourth, fifth, and sixth
2. The data is 80h for factory locked and 00h for not factory locked.
3. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

32 Am50DL128CG November 7, 2002

Table 12 shows the outputs for RY/BY#. complete, DQ6 stops toggling. Table 12 shows the outputs for Toggle Bit I on DQ6. also the subsection on DQ2: Toggle Bit II. Figure 7. Toggle Bit Algorithm

34 Am50DL128CG November 7, 2002

Table 12. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

36 Am50DL128CG November 7, 2002

Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. 6. CE#f refers to chip enable input of active flash (device being addressed). FLASH DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC , VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current V CC = VCC max ; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC , VCC = VCC max ±1.0 µA ILR Reset Leakage Current V CC = VCC max = 12.5 V 35 µA ILIA ACC Input Leakage Current VCC = VCC max , WP#/ACC = VACC max 35 µA ICC1 f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Word Mode

5 MHz 10 16

1 MHz 2 4

ICC2 f Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL 15 30 mA ICC3 f Flash VCC Standby Current (Note 2) VCC f = VCC max , CE#f, RESET#, WP#/ACC = V CC f ± 0.3 V 0.2 5 µA ICC4 f Flash VCC Reset Current (Note 2) VCC f = VCC max , RESET# = VSS ± 0.3 V, WP#/ACC = V CC f ± 0.3 V 0.2 5 µA ICC5 f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCC f = VCC max , VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = VIL, OE# = VIH Word 21 45 mA ICC7 f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH Word 21 45 mA ICC8 f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = VIL, OE#f = VIH 17 35 mA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 VCC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 11.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC f = VCC s = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC f = VCC s = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC –0.4 VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

November 7, 2002 Am50DL128CG 37 PRELIMINARY pSRAM DC & OPERATING CHARACTERISTICS Notes: 1. VCC – 1.0 V for a 10 ns pulse width. 2. VCC + 1.0 V for a 10 ns pulse width. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V IN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC Operating Power Supply Current IIO = 0 mA, CE1#s = VIL, CE2s = VIH, VIN = VIH or VIL 2m A ICC1 s Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH, tRC = Min. 50 mA ICC2 s Page Access Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH, tPC = Min. 25 mA VOL Output Low Voltage I OL = 1.0 mA 0.4 V VOH Output High Voltage I OH = –0.5 mA 2 V ISB Standby Current (CMOS) CE#1 = V CCS – 0.2 V, CE2 = VCCS – 0.2 V 100 µA IDSB Deep Power-down Standby CE2 = 0.2 V 5 µA VIL Input Low Voltage –0.3 (Note 1) 0.4 V VIH Input High Voltage 2.4 VCC + 0.3 (Note 2) V

38 Am50DL128CG November 7, 2002

Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 11. Typical ICC1 vs. Frequency

40 Am50DL128CG November 7, 2002

CE#s Timing Figure 14. Timing Diagram for Alternating

Description

Test Setup All Speeds Unit JEDEC Std —t CCR CE#s Recover Time — Min 0 ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

1. See Figure 12 and Table 13 for test specifications
2. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC /2. The time from OE# high to the

device must be held high during this operation. Figure 15. Read Operation Timings

0 VRY/BY#

42 Am50DL128CG November 7, 2002

Note:CE#f refers to the flash device being reset (either CE#f1 or CE#f2). Figure 16. Reset Timings

November 7, 2002 Am50DL128CG 43 PRELIMINARY FLASH AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. 3. CE#f refers to chip enable input of active flash (device being addressed). Parameter Speed JEDEC Std Description 70 85 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 85 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 40 45 ns tAHT Address Hold Time From CE#f or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 40 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min 0 ns tELWL tCS CE#f Setup Time Min 0 ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min 0 ns tWHEH tCH CE#f Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 7 µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

44 Am50DL128CG November 7, 2002

1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
3. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash

device must be held high during this operation. Figure 17. Program Operation Timings Figure 18. Accelerated Program Timing Diagram

1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”.
2. These waveforms are for the word mode.
3. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must

be held high during this operation. Figure 19. Chip/Sector Erase Operation Timings

46 Am50DL128CG November 7, 2002

device must be held high during this operation. Figure 20. Back-to-back Read/Write Cycle Timings

1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
2. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash

device must be held high during this operation. Figure 21. Data# Polling Timings (During Embedded Algorithms)

48 Am50DL128CG November 7, 2002

device must be held high during this operation. Figure 24. Temporary Sector Unprotect Timing Diagram

• For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.

device must be held high during this operation. Figure 25. Sector/Sector Block Protect and

50 Am50DL128CG November 7, 2002

Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. 3. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). Parameter Speed JEDEC Std Description 70 85 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 85 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 40 45 ns tDVEH tDS Data Setup Time Min 40 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE#f Pulse Width Min 40 45 ns tEHEL tCPH CE#f Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SADD = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2). The chip enable input of the inactive flash device must

be held high during this operation.

1. Waveforms are for the word mode.

Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

52 Am50DL128CG November 7, 2002

1. tOD, tODo , tBD , and tODW are defined as the time at which

not referenced to output voltage levels.

1. If CE#, LB#, or UB# goes low at the same time or before

WE# goes high, the outputs will remain at high impedance.

1. If CE#, LB#, or UB# goes low at the same time or after WE#

goes low, the outputs will remain at high impedance. Figure 27. Pseudo SRAM Read Cycle

1. tOD, tODo , tBD , and tODW are defined as the time at which the outputs achieve the open circuit condition and are not referenced
2. If CE#, LB#, or UB# goes low at the same time or before WE# goes high, the outputs will remain at high impedance.
3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.

Figure 28. Page Read Timing

54 Am50DL128CG November 7, 2002

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1s, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1s, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.

Figure 29. Pseudo SRAM Write Cycle—WE# Control

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.

Figure 30. Pseudo SRAM Write Cycle—CE1#s Control

56 Am50DL128CG November 7, 2002

1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.

Figure 31. Pseudo SRAM Write Cycle—

November 7, 2002 Am50DL128CG 57 PRELIMINARY FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC , 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note:Includes all pins except VCC . Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 56 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 4 120 µs Word Program Time 7 210 µs Chip Program Time (Note 3) Byte Mode 42 126 sec Word Mode 28 84 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 11 14 pF C OUT Output Capacitance V OUT = 0 12 16 pF C IN2 Control Pin Capacitance V IN = 0 14 16 pF C IN3 WP#/ACC Pin Capacitance V IN = 0 17 20 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

58 Am50DL128CG November 7, 2002

1. Typical values are not 100% tested.

Figure 32. Deep Power-down Timing Figure 33. Power-on Timing

60 Am50DL128CG November 7, 2002

FTA088—88-Ball Fine-Pitch Grid Array 11.6 x 8 mm 3237 \\ 16-038.14b PACKAGE FTA 088 JEDEC N/A 11.60 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.40 PROFILE A1 0.25 --- --- BALL HEIGHT A2 1.00 --- 1.11 BODY THICKNESS D 11.60 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 88 BALL COUNT φb 0.30 0.35 0.40 BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A3,A4,A5,A6,A7,A8,B1,B10,C1,C10,D1,D10DEPOPULATED SOLDER BALLS E1,E10,F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10,M3,M4,M5,M6,M7,M8 NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. INDEX MARK LM 88X eD CORNER C0.15 (2X) (2X) C0.15 7SE B A D1 ABDCEFHG JK eE SD BOTTOM VIEW b 0.20 C C 0.15 0.08 MC MC AB PIN A17 D E PIN A1 C TOP VIEW SIDE VIEW CORNER A 0.08

Removed 8 M x 8-Bit from product description. Switched the #1 and #2 on RESET# in diagram. Added a 1 to the H2 pin (CE#f1). Added a #1 and #2 to Chip Enable 1 and 2. Table 1. Device Bus Operations–Flash Word Mode Removed CIOf = VIH from table title. Table 2. Device Bus Operations–Flash Byte Mode, Removed table, no byte mode offered on this MCP. Table 3. Am29DL640G Sector Architecture Removed (x8) Address Range from table. Table 7. CFI Query Identification String, Table 8. Removed Addresses (Byte Mode) from tables. Added ILR parameter to table. Table 12. Am29DL640G Command Definitions command sequence from BA to XXX. Programmed or Protected at the factory. are not available when the SecSi sector is enabled. Changed CFI website address.

62 Am50DL128CG November 7, 2002

Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.