AM486DE2 AMD | Alldatasheet
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A Amendment Issue Date April 1996 DISTINCTIVE CHARACTERISTICS ■ High-Performance Design — 66-MHz operating frequency — Frequent instructions execute in one clock — 105.6-million bytes/second burst bus at 33 MHz — Flexible write-through address control — Dynamic bus sizing for 8-, 16-, and 32-bit buses — Soft reset capability ■ High On-Chip Integration — 8-Kbyte unified code and data cache — Floating-point unit — Paged, virtual memory management ■ Enhanced System and Power Management — Stop clock control for reduced power consumption — Industry-standard, two-pin System Management Interrupt (SMI) for power management indepen- dent of processor operating mode and operating system — Static design with Auto Halt Power-Down support — Wide range of chipsets supporting SMM avail- able to allow product differentiation ■ Complete 32-Bit Architecture — Address and data buses — All registers — 8-, 16-, and 32-bit data types ■ Standard Features — 3-V core with 5-V-tolerant I/O — Binary compatible with all Am486 ® DX and Am486DX2 microprocessors — Wide range of support available through the AMD FusionE86SM Program ■ IEEE 1149.1 JTAG Boundary-Scan Compatibility ■ Supports Environmental Protection Agency's Energy Star program — 3-V operation reduces power consumption up to 40% — Energy management capability provides an ex- cellent base for energy-efficient design — Works with a variety of energy-efficient, power- managed devices ■ 208-Lead SQFP or 168-Pin PGA Package GENERAL DESCRIPTION The Am486DE2 microprocessor is an addition to the AMD Am486 microprocessor family. The Am486DE2 enhances system performance by incorporating flexible clock control and enhanced SMM. The Am486DE2 CPU clock control feature permits the CPU to be stopped under controlled conditions, allowing reduced power consumption during system inactivity. The SMM function is implemented with an industry-stan- dard, two-pin interface. FINAL Am486 DE2 8-Kbyte Write-Through Embedded Microprocessor
2 Am486DE2 Microprocessor
ADS, W/R, D/C, M/IO, PCD, PWT, RDY , LOCK, PLOCK, BOFF, A20M, BREQ, HOLD, HLDA, RESET, INTR, NMI, FERR, UP, IGNNE, SMI, SMIACT, SRESET Control ROM Floating- Point Register File Floating- Point Unit Micro-instruction Decoded Instruction Path Instruction Decode Code Stream Displacement Bus 32-Byte Code Queue 2x16 Bytes Prefetcher 128 JTAG TDI, TCK, TDO, TMS PCHK, DP3–DP0 Parity Generation and Control Cache Control KEN, FLUSH, AHOLD, CACHE, EADS, INV, WB/WT , HITM BS16, BS8 Bus Size Control Burst Bus Control BRDY , BLAST Bus Control Request Sequencer Data Bus Transceivers D31–D0 Writeback Buffers 4x32 Copyback Buffers 4x32 Write Buffers 4x32 Address Drivers A31–A2 BE3–BE0 Bus Interface Clock Generator CLK STPCLK Clock Interface 32-Bit Data Bus 32-Bit Data Bus 32-Bit Linear Address Barrel Shifter Register File 24 ALU Physical Address Segmentation Unit Descriptor Registers Limit and Attribute PLA Paging Unit Translation Lookaside Buffer PCD, PWT Physical Address 24 8-Kbyte Cache Cache Unit 32 Central and Protection Test Unit VOLDET V, VCC SS Power Plane
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. Valid order numbers are formed by a combination of the elements below. H = 208-Lead SQFP G= 168-Pin PGA Am486 DE2 –66 V 8 T CACHE TYPE CACHE SIZE VOLTAGE SPEED OPTION VERSION DEVICE NUMBER/DESCRIPTION T = Write-through 8 = 8 Kbyte V = V CC is 3 V with 5-V tolerance –66 = 66 MHz DE2 = Clock-doubled with FPU Am486 high-performance CPU Valid Combination Comment Am486DE2-66V8THC SQFP package Am486DE2-66V8TGC PGA package Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. HC PACKAGE TYPE TEMPERATURE RANGE C = Commercial
4 Am486DE2 Microprocessor
6 Am486DE2 Microprocessor
Figure 15 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with Figure 16 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Caching Figure 17 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Figure 21 PCHK Figure 23 RDY TABLES Table 15 Thermal Resistance (°C/W) θ
CONNECTION DIAGRAMS AND PIN DESIGNATIONS 168-Pin Grid Array (PGA) Package A B C D E F G H J K L M N P Q R S A B C D E F G H J K L M N P Q R S D 20 D 19 D 11 D 9 VS S D P1 VSS VSS IN C VSS VSS VSS D 2 D 0 A31 A28 A27 D 22 D 21 D 18 D 13 VC C D 8 VC C D 3 D 5 VC C D 6 VC C D 1 A29 VSS A25 A26 TC K VS S C LK D 17 D 10 D 15 D 12 D P2 D 16 D 14 D 7 D 4 D P0 A30 A17 VC C A23 D 23 VSS VC C A19 VSS VO LD ET D P3 VSS VC C D 13 VC C D 8 VC C D 3 D 5 VC C D 6 VC C D 1 A29 A21 A18 A14 D 24 D 25 D 27 D 13 VC C D 8 VC C D 3 D 5 VC C D 6 VC C D 1 A29 A24 VC C VSS VSS VC C D 26 D 13 VC C D 8 VC C D 3 D 5 VC C D 6 VC C D 1 A29 A22 A15 A12 D 29 D 31 D 28 D 13 VC C D 8 VC C D 3 D 5 VC C D 6 VC C D 1 A29 A20 VC C VS S VSS VC C D 30 D 13 VC C D 8 VC C D 3 D 5 VC C D 6 VC C D 1 A29 A16 VC C VSS TD I TM S FER R A2 VC C VSS IN V SM I SR ESET VC C D 8 VC C D 3 D5 VC C D 6 VC C D 1 A29 A13 VC C VSS VSS VC C U P D 13 VC C D 8 VC C D 3 D5 VC C D 6 VC C D 1 A29 A9 VC C VS S H ITM C AC H E SM IAC T A5 A11 VSS IN C W B/W T IN C A7 A8 A10 IG N N E N M I FLU SH A20M H O LD KEN STPC LK BR DY BE2 BE0 PW T D /C LO C K H LDA BR EQ A3 A6 IN TR TD O R ESET BS8 VC C R DY VC C VC C BE1 VC C VC C VC C M /IO VC C PLO C K BLAST A4 AH O LD EAD S BS16 BO FF VSS BE3 VSS VSS PC D VSS VSS VSS W /R VSS PC H K L AD SINC Pin Side View
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168-Pin PGA Designations (Functional Grouping) Address Data Control Test INC Vcc Vss Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin No. Pin No. Pin No. A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Q-14 R-15 S-16 Q-12 S-15 Q-13 R-13 Q-11 S-13 R-12 S-7 Q-10 S-5 R-7 Q-9 Q-3 R-5 Q-4 Q-8 Q-5 Q-7 S-3 Q-6 R-2 S-2 S-1 R-1 P-2 P-3 Q-1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 P-1 N-2 N-1 H-2 M-3 J-2 L-2 L-3 F-2 D-1 E-3 C-1 G-3 D-2 K-3 F-3 J-3 D-3 C-2 B-1 A-1 B-2 A-2 A-4 A-6 B-6 C-7 C-6 C-8 A-8 C-9 B-8 A20M ADS AHOLD BE0 BE1 BE2 BE3 BLAST BOFF BRDY BREQ BS8 BS16 CACHE CLK D/C DP0 DP1 DP2 DP3 EADS FERR FLUSH HITM HLDA HOLD IGNN E INTR INV KEN LOCK M/IO NMI PCD PCHK PLOCK PWT RDY RESET SMI SMIACT SRESET STPCLK UP VOLDET WB/WT W/R D-15 S-17 A-17 K-15 J-16 J-15 F-17 R-16 D-17 H-15 Q-15 D-16 C-17 B-12 C-3 M-15 N-3 F-1 H-3 A-5 B-17 C-14 C-15 A-12 P-15 E-15 A-15 A-16 A-10 F-15 N-15 N-16 B-15 J-17 Q-17 Q-16 L-15 F-16 C-16 B-10 C-12 C-10 G-15 C-11 S-4 B-13 N-17 TCK TDI TDO TMS A-3 A-14 B-16 B-14 A-13 C-13 J-1 R-17 B-7 B-9 B-11 C-4 C-5 E-2 E-16 G-2 G-16 H-16 K-2 K-16 L-16 M-2 M-16 P-16 R-3 R-6 R-8 R-9 R-10 R-11 R-14 A-7 A-9 A-11 B-3 B-4 B-5 E-1 E-17 G-1 G-17 H-1 H-17 K-1 K-17 L-1 L-17 M-1 M-17 P-17 Q-2 R-4 S-6 S-8 S-9 S-10 S-11 S-12 S-14 Notes: VOLDET is connected internally to VSS . INC = Internal No Connect
208-Lead Shrink Quad Flat Pack (SQFP) Package VSS VCC INC PCHK BRDY BOFF BS16 BS8 VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK VCC HLDA W/R VSS VCC BREQ BE 0 BE 1 BE 2 BE 3 VCC VSS M/IO VCC D/C PWT PCD VCC VSS VCC VCC EADS A20M RESET FLUSH INTR NMI VSS INC RDY KEN VCC VSS VSS VCC A25 A26 A27 A28 V CC A29 A30 A31 VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC INC DP1 V SS VCC VSS D10 D11 D12 D13 VSS VCC D14 D15 VCC VSS DP2 D16 VSS VCC VSS VSS DP0 VSS LOCK PLOCK VCC BLAST ADS VSS VCC VSS V CC VSS VCC A10 VCC VSS VCC A11 VSS A12 VCC A13 A14 VCC VSS A15 A16 VCC A17 VSS VCC TDI TMS A18 A19 A20 V CC VCC A21 A22 A23 A24 V SS VCC UP VSS VCC VSS VCC VSS SRESET SMIACT VCC VSS VCC TDO VCC CACHE INV IGNNE STPCLK D31 D30 V SS VCC D29 D28 VCC VSS VCC D27 D26 D25 VCC D24 VSS VCC DP3 D23 D22 D21 V SS VCC INC VSS VCC D20 D19 D18 V CC D17 VSS HITM WB/WT SMI FERR INC 208 207 206 205 204 203 202 201 200 199 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 198 197 196 195 194 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 146 145 144 143 142 Top View
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208-Lead SQFP Designations (Functional Grouping) Address Data Control Test INC Vcc Vss A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 202 197 196 195 193 192 190 187 186 182 180 178 177 174 173 171 166 165 164 161 160 159 158 154 153 152 151 149 148 147 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 144 143 142 141 140 130 129 126 124 123 119 118 117 116 113 112 108 103 101 100 A20M ADS AHOLD BE 0 BE 1 BE 2 BE 3 BLAST BOFF BRDY BREQ BS 8 BS 16 CACHE CLK D/C DP0 DP1 DP2 DP3 EADS FERR FLUSH HITM HLDA HOLD IGNNE INTR INV KEN LOCK M/IO NMI PCD PCHK PLOCK PWT RDY RESET SMI SMIACT SRESET STPCL K U P WB/WT W/R 203 204 145 125 109 207 206 194 TCK TDI TDO TMS 168 167 127 102 106 111 114 121 128 131 133 134 136 137 139 150 155 162 163 169 172 176 179 183 185 188 191 198 200 205 104 105 107 110 115 120 122 132 135 138 146 156 157 170 175 181 184 189 199 201 208 Note: INC = Internal No Connect
Am486DE2 Microprocessor 11 LOGIC SYMBOL DP3–DP0 A31–A4 CLK A20M M/IO Am486DE2 CPU W/R D/C LOCK
4 BE3 –BE0
A3–A2 BRDY BLAST PWT PCD KEN FLUSH EADS AHOLD Data Parity Data Bus Burst Control Page Cacheability Invalidation Cache Control/ D31–D0 TMS TDI TDO TCK IEEE Test Port Access FERRIGNNE Numeric Error Reporting Bus Arbitration BREQ HOLD HLDA BOFF CACHE Mask HITM INV SMI SMIACT SMM SRESET STPCLKStop Clock UPUpgrade VOLDETVoltage Detect Present WB/WT
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The Am486DE2 microprocessor is a new member of the AMD Am486 family, which also includes the Enhanced Am486 and the Am486DX microprocessors. Like the AMD Enhanced Am486 family, the Am486DE2 adds new signals to those used by the Am486DX pro- cessors. These added signals support new processor features and are indicated as new in the pin description titles. Although the Am486DE2 processor is based on and compatible with the Enhanced Am486 microprocessors, it has no support for write-back cache. Because of this, some Am486DE2 signals are supported differently than the signals in either the Enhanced Am486 or the Am486DX microprocessors. These signals are indicat- ed as modified in the pin descriptions below. All other processor signals provide the same function- ality as the standard Am486DX processor. A20M Address Bit 20 Mask (Active-Low Input) A Low signal on the A20M pin causes the microproces- sor to mask address line A20 before performing a lookup to the internal cache, or driving a memory cycle on the bus. Asserting A20M causes the processor to wrap the address at 1 Mbyte, emulating Real mode operation. The signal is asynchronous, but must meet setup and hold times t 20 and t21 for recognition during a specific clock. During normal operation, A20M should be sam- pled High at the falling edge of RESET. A31–A2 Address Lines A31-A4 (Inputs/Outputs) Address Lines A3-A2 (Outputs) Pins A31–A2 define a physical area in memory or indi- cate an input/output (I/O) device. Address lines A31–A4 drive addresses into the microprocessor to perform cache line invalidations. Input signals must meet setup and hold times t 22 and t23. A31–A2 are not driven during bus or address hold. A DS Address Status (Active-Low Output) A Low output from this pin indicates that a valid bus cycle definition and address are available on the cycle defini- tion lines and address bus. ADS is driven active by the same clock as the addresses. ADS is active Low and is not driven during bus hold. AHOLD (Modified) Address Hold (Input) The external system may assert AHOLD to perform a cache snoop. In response to the assertion of AHOLD, the microprocessor stops driving the address bus A31– A2 in the next clock. The data bus remains active and data can be transferred for previously issued read or write bus cycles during address hold. AHOLD is recog- nized even during RESET and LOCK . The earliest that AHOLD can be deasserted is two clock cycles after EADS is asserted to start a cache snoop. BE 3–BE 0 Byte Enable (Active-Low Outputs) The byte enable pins indicate which bytes are enabled and active during read or write cycles. During the first cache fill cycle, however, an external system should ig- nore these signals and assume that all bytes are active. ■ BE3 for D31–D24 ■ BE2 for D23–D16 ■ BE1 for D15–D8 ■ BE0 for D7–D0 BE3 –BE0 are active Low and are not driven during bus hold. BLAST (Modified) Burst Last (Active-Low Output) Burst Last goes Low to tell the CPU that the next BRDY signal completes the burst bus cycle. BLAST is active for both burst and non-burst cycles. BLAST is active Low and is not driven during a bus hold. BOFF Back Off (Active-Low Input) This input signal forces the microprocessor to float all pins normally floated during hold, but HLDA is not as- serted in response to BOFF . BOFF has higher priority than RDY or BRDY; if both are returned in the same clock, BOFF takes effect. The microprocessor remains in bus hold until BOFF goes High. If a bus cycle is in progress when BOFF is asserted, the cycle restarts. BOFF must meet setup and hold times t18 and t19 for proper operation. BOFF has an internal weak pull-up. BRDY Burst Ready Input (Active-Low Input) The BRDY signal performs the same function during a burst cycle that RDY performs during a non-burst cycle. BRDY indicates that the external system has presented valid data in response to a read, or that the external system has accepted data in response to write. BRDY
ing copy-back or write-back cycles. In Write-through mode, this signal always floats. (PLL) to generate the internal operating frequency. subsequent clocks of write cycles. same timing as the data driven by the microprocessor. during the second and subsequent clocks of write cycles. as the hold remains active and HITM remains inactive. asserted. EADS has an internal weak pull-up. Table 1. EADS Sample Time
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This signal is used in cache snooping. The Am486DE2 processor does not support write-back cache. EADS has a weak internal pull-up, which disables this pin. FERR Floating-Point Error (Active-Low Output) Driven active when a floating-point error occurs, FERR is similar to the ERROR pin on a 387 math coprocessor. FERR is included for compatibility with systems using DOS-type floating-point error reporting. FERR is active Low and is not floated during bus hold, except during Three-state Test mode (see FLUSH FLUSH (Modified) Cache Flush (Active-Low Input) In Write-through mode, FLUSH invalidates the cache without issuing a special bus cycle. FLUSH is an active Low input that needs to be asserted only for one clock. FLUSH is asynchronous, but setup and hold times t20 and t21 must be met for recognition in any specific clock. Sampling FLUSH Low in the clock before the falling edge of RESET causes the microprocessor to enter Three-state Test mode. HITM (New) Hit Modified Line (Active-Low Output) In Write-through mode, HITM floats at all times. HLDA Hold Acknowledge (Output) The HLDA signal is activated in response to a hold re- quest presented on the HOLD pin. HLDA indicates that the microprocessor has given the bus to another local bus master. HLDA is driven active in the same clock in which the microprocessor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active High and remains driven during bus hold. HLDA is floated only during Three-state Test mode. (See FLUSH HOLD Bus Hold Request (Input) HOLD gives control of the microprocessor bus to anoth- er bus master. In response to HOLD going active, the microprocessor floats most of its output and input/output pins. HLDA is asserted after completing the current bus cycle, burst cycle, or sequence of locked cycles. The microprocessor remains in this state until HOLD is deas- serted. HOLD is active High and does not have an in- ternal pull-down resistor. HOLD must satisfy setup and hold times t 18 and t19 for proper operation. IGNNE Ignore Numeric Error (Active-Low Input) When this pin is asserted, the Am486DE2 microproces- sor will ignore a numeric error and continue executing non-control floating-point instructions. When IGNNE is deasserted, the Am486DE2 microprocessor will freeze on a non-control floating-point instruction if a previous floating-point instruction caused an error. IGNNE has no effect when the NE bit in Control Register 0 is set. IGNNE is active Low and is provided with a small internal pull-up resistor. IGNNE is asynchronous but must meet setup and hold times t20 and t21 to ensure recognition in any specific clock. INTR Maskable Interrupt (Input) When asserted, this signal indicates that an external interrupt has been generated. If the internal interrupt flag is set in EFLAGS, active interrupt processing is initiated. The microprocessor generates two locked interrupt ac- knowledge bus cycles in response to the INTR pin going active. INTR must remain active until the interrupt ac- knowledges have been performed to ensure that the interrupt is recognized. INTR is active High and is not provided with an internal pull-down resistor. INTR is asynchronous, but must meet setup and hold times t and t21 for recognition in any specific clock. INV (New) Invalidate (Input) The external system asserts INV to invalidate the cache- line state when an external bus master proposes a write. It is sampled together with A31–A4 during the clock in which EADS is active. INV has an internal weak pull-up. INV is ignored in Write-through mode. K EN Cache Enable (Active-Low Input) KEN determines whether the current cycle is cacheable. When the microprocessor generates a cacheable cycle and KEN is active one clock before RDY or BRDY during the first transfer of the cycle, the cycle becomes a cache- line-fill cycle. Returning KEN active one clock before RDY during the last read in the cache line fill causes the line to be placed in the on-chip cache. KEN is active Low and is provided with a small internal pull-up resistor. KEN must satisfy setup and hold times t14 and t15 for proper operation. LOCK Bus Lock (Active-Low Output) A Low output on this pin indicates that the current bus cycle is locked. The microprocessor ignores HOLD when LOCK is asserted (although it does acknowledge AHOLD and BOFF ). LOCK goes active in the first clock of the first locked bus cycle and goes inactive after the
Am486DE2 Microprocessor 15 last clock of the last locked bus cycle. The last locked cycle ends when RDY is returned. LOCK is active Low and is not driven during bus hold. Locked read cycles are not transformed into cache fill cycles if KEN is active. M/IO Memory/IO (Output) A High output indicates a memory cycle. A Low output indicates an I/O cycle. NMI Non-Maskable Interrupt (Input) A High NMI input signal indicates that an external non- maskable interrupt has occurred. NMI is rising-edge sensitive. NMI must be held Low for at least four CLK periods before this rising edge. The NMI input does not have an internal pull-down resistor. The NMI input is asynchronous, but must meet setup and hold times t and t21 for recognition in any specific clock. PCD Page Cache Disable (Output) This pin reflects the state of the PCD bit in the page table entry or page directory entry (programmable through the PCD bit in CR3). If paging is disabled, the CPU ignores the PCD bit and drives the PCD output Low. PCD has the same timing as the cycle definition pins (M/IO , D/C, and W/R). PCD is active High and is not driven during bus hold. PCD is masked by the Cache Disable Bit (CD) in Control Register 0 (CR0). PCHK Parity Status (Active-Low Output) Parity status is driven on the PCHK pin the clock after RDY for read operations. The parity status reflects data sampled at the end of the previous clock. A Low PCHK indicates a parity error. Parity status is checked only for enabled bytes as is indicated by the byte enable and bus size signals. PCHK is valid only in the clock imme- diately after read data is returned to the microprocessor; at all other times PCHK is inactive High. PCHK is floated only during Three-state Test mode. (See FLUSH.) PLOCK (Modified) Pseudo-Lock (Active-Low Output) When PLOCK is asserted in Write-through mode, it in- dicates that the current bus transaction requires more than one bus cycle. Examples of such operations are segment table descriptor reads (8 bytes) and cache line fills (16 bytes). The microprocessor drives PLOCK ac- tive until the addresses for the last bus cycle of the trans- action have been driven, whether or not RDY or BRDY is returned. PLOCK is a function of the BS8, BS16, and KEN inputs. PLOCK should be sampled on the clock when RDY is returned. PLOCK is active Low and is not driven during bus hold. PWT Page Write-Through (Output) This pin reflects the state of the PWT bit in the page table entry or page directory entry (programmable through the PWT bit in CR3). If paging is disabled, the CPU ignores the PWT bit and drives the PWT output Low. PWT has the same timing as the cycle definition pins (M/IO , D/C, and W/R). PWT is active High and is not driven during bus hold. R DY Non-Burst Ready (Active-Low Input) A Low input on this pin indicates that the current bus cycle is complete, that is, either the external system has presented valid data on the data pins in response to a read, or the external system has accepted data from the microprocessor in response to a write. RDY is ignored when the bus is idle and at the end of the bus cycle’s first clock. RDY is active during address hold. Data can be returned to the processor while AHOLD is active. RDY is active Low and does not have an internal pull- up resistor. RDY must satisfy setup and hold times t16 and t17 for proper chip operation. RESET Reset (Input) RESET forces the microprocessor to initialize. The microprocessor cannot begin instruction execution of instructions until at least 1 ms after V CC and CLK have reached their proper DC and AC specifications. To ensure proper microprocessor operation, the RESET pin should remain active during this time. RESET is active High. RESET is asynchronous, but must meet setup and hold times t 20 and t21 to ensure recognition on any specific clock. SMI (New) SMM Interrupt (Active-Low Input) A Low signal on the SMI pin signals the processor to enter System Management Mode (SMM). SMI is the highest-level processor interrupt. The SMI signal is rec- ognized on an instruction boundary, similar to the NMI and INTR signals. SMI is sampled on every rising clock edge. SMI is a falling-edge sensitive input. Recognition of SMI is guaranteed in a specific clock if it is asserted synchronously and meets the setup and hold times. If SMI is asserted asynchronously, it must go High for a minimum of two clocks before going Low, and it must remain Low for at least two clocks to guarantee recog- nition. When the CPU recognizes SMI , it enters SMM before executing the next instruction and saves internal registers in SMM space.
16 Am486DE2 Microprocessor
SMIACT (New) SMM Interrupt Active (Active-Low Output) SMIACT goes Low in response to SMI. It indicates that the processor is operating under SMM control. SMIACT remains Low until the processor receives a RESET sig- nal or executes the Resume instruction (RSM) to leave SMM. This signal is always driven. It does not float dur- ing bus HOLD or BOFF Note: Do not use SRESET to exit from SMM. The sys- tem should block SRESET during SMM. SRESET (New) Soft Reset (Input) The CPU samples SRESET on every rising clock edge. If SRESET is sampled active, the SRESET sequence begins on the next instruction boundary. SRESET resets the processor, but, unlike RESET, does not cause it to sample UP or WB/WT, or affect the FPU, cache, CD and NW bits in CR0, and SMBASE. SRESET is asynchronous and must meet the same timing as RESET. STPCLK (New) Stop Clock (Active-Low Input) A Low input signal indicates a request has been made to turn off the CLK input. When the CPU recognizes a STPCLK , the processor: ■ stops execution on the next instruction boundary (unless superseded by a higher priority interrupt) ■ empties all internal pipelines and write buffers ■ generates a Stop Grant acknowledge bus cycle STPCLK is active Low and has an internal pull-up resis- tor. STPCLK is asynchronous, but it must meet setup and hold times t20 and t21 to ensure recognition in any specific clock. STPCLK must remain active until the Stop Clock special bus cycle is issued and the system returns either RDY or BRDY. TCK Test Clock (Input) Test Clock provides the clocking function for the JTAG boundary scan feature. TCK clocks state information and data into the component on the rising edge of TCK on TMS and TDI, respectively. Data is clocked out of the component on the falling edge of TCK on TDO. TDI Test Data Input (Input) TDI is the serial input that shifts JTAG instructions and data into the tested component. TDI is sampled on the rising edge of TCK during the SHIFT-IR and the SHIFT- DR TAP (Test Access Port) controller states. During all other TAP controller states, TDI is ignored. TDI uses an internal weak pull-up. TDO Test Data Output (Output) TDO is the serial output that shifts JTAG instructions and data out of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR TAP controller states. Otherwise, TDO is three-stated. TMS Test Mode Select (Input) TMS is decoded by the JTAG TAP to select the opera- tion of the test logic. TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior of the TAP controller, the TMS pin has an internal pull-up resistor. UP Upgrade Present (Input) The processor samples the Upgrade Present (UP) pin in the clock before the falling edge of RESET. If it is Low, the processor three-states its outputs immediately. UP must remain asserted to keep the processor inactive. The pin uses an internal pull-up resistor. VOLDET (New, 168-Pin PGA Package only) Voltage Detect (Output) VOLDET provides an external signal to allow the system to determine the CPU input power level (3 V or 5 V). For the Am486DE2, the pin ties internally to V SS . WB/WT (New) Write-Back/Write-Through (Input) WB/WT is sampled Low at RESET, and all cache-line fills are write-through. WB/WT has an internal weak pull- down. This pin should be tied Low for the Am486DE2 microprocessor. W/R Write/Read (Output) A High output indicates a write cycle. A Low output in- dicates a read cycle. Note: The Am486DE2 microprocessor does not use the VCC5 pin used by some 3-V, clock-tripled, 486-based processors. The corresponding pin on the Am486DE2 microprocessor is an Internal No Connect (INC).
Am486DE2 Microprocessor 17 FUNCTIONAL DESCRIPTION Note: This Am486DE microprocessor does not support Write-back mode. If you are designing in a shared-mem- ory system or using cache coherency (including snoop- ing and locked accesses), use one of the Am486DE products that supports write back. Overview The Am486DE2 microprocessor uses a 32-bit architec- ture with on-chip memory management and cache memory units. The instruction set includes the complete 486 microprocessor instruction set, along with exten- sions to serve the new extended applications. All soft- ware written for the 486 microprocessor and previous members of the x86 architectural family can run on the Am486DE2 microprocessor without modification. The on-chip Memory Management Unit (MMU) is com- pletely compatible with the 486 MMU. The MMU in- cludes a segmentation unit and a paging unit. Segmentation allows management of the logical ad- dress space by providing easy data and code relocat- ability and efficient sharing of global resources. The paging mechanism operates beneath segmentation and is transparent to the segmentation process. Paging is optional and can be disabled by system software. Each segment can be divided into one or more 4-Kbyte seg- ments. To implement a virtual memory system, the Am486DE2 microprocessor supports full restartability for all page and segment faults. Memory Memory is organized into one or more variable length segments, each up to 4 Gbyte (2 32 bytes). A segment can have attributes associated with it, including its loca- tion, size, type (e.g., stack, code, or data), and protection characteristics. Each task on a microprocessor can have a maximum of 16,381 segments, each up to 4 Gbyte. Thus, each task has a maximum of 64 Tbyte of virtual memory. The segmentation unit provides four levels of protection for isolating and protecting applications and the operat- ing system from each other. The hardware-enforced protection allows high-integrity system designs. Modes of Operation The Am486DE2 microprocessor has four modes of op- eration: Real Address mode (Real mode), Virtual 8086 Address mode (Virtual mode), Protected Address mode (Protected mode), and System Management mode (SMM). Real Mode In Real mode, the Am486DE2 microprocessor operates as a fast 8086. Real mode is required primarily to set up the processor for Protected mode operation. Virtual Mode In Virtual mode, the processor appears to be in Real mode, but can use the extended memory accessing of Protected mode. Protected Mode Protected mode provides access to the sophisticated memory management paging and privilege capabilities of the processor. System Management Mode SMM is a special operating mode described in detail in “System Management Mode” on page 22. Write-Through Cache Architecture The Am486DE2 microprocessor supports the standard 486DX-type write-through cache architecture, which is characterized by the following: ■ External read accesses are placed in the cache if they meet proper caching requirements. ■ Subsequent reads to the data in the cache are made if the address is stored in the cache tag array. ■ Write operations to a valid address in the cache are updated in the cache and to external memory. This data writing technique is called write-through. The write-through cache implementation forces all writes to flow through to the external bus and back to main memory. Consequently, the write-through cache generates a large amount of bus traffic on the external data bus. Cache Replacement Description The cache-line-replacement algorithm uses the stan- dard Am486 CPU pseudo LRU (least recently used) strategy. When a line must be placed in the internal cache, the microprocessor first checks to see if there is an invalid line available in the set. If no invalid line is available, the LRU algorithm replaces the least-recently used cache line in the four-way set with the new cache line. If the cache line for replacement is modified, the modified cache line is placed into the copy-back buffer for copying back to external memory, and the new cache line is placed into the cache. This copy-back ensures that the external memory is updated with the modified data upon replacement. Memory Configuration In computer systems, memory regions require specific caching and memory write methods. For example, some memory regions are noncacheable while others are cacheable but are write-through. To allow maximum memory configuration, the microprocessor supports
18 Am486DE2 Microprocessor
specific memory region requirements. All bus masters, such as DMA controllers, must reflect all data transfers on the microprocessor local bus so that the micropro- cessor can respond appropriately. Cacheability The Am486DE2 processor caches data based on the state of the CD and NW bits in CR0, in conjunction with the KEN signal, at the time of a burst read access from memory. When the WB/WT signal is Low during the first BRDY , KEN meets the standard setup and hold require- ments, and the four 32-bit doublewords are placed in the cache. However, all cacheable accesses in this mode are considered write-through. Note: The CD bit in CR0 enables (0) or disables (1) the internal cache. The NW bit in CR0 enables (0) or dis- ables (1) write-through and snooping cycles. RESET sets CD and NW to 1. Unlike RESET, however, SRESET does not invalidate the cache nor does it modify the values of CD and NW in CR0. Write-Through When the WB/WT signal is Low during the first BRDY of the cache line read access, the cache line is consid- ered a write-through access. Therefore, all writes to this location in the cache are reflected on the external bus, even if the cache line is write protected. CLOCK CONTROL Clock Generation The Am486DE2 CPU is driven by a 1X clock that relies on phased-lock loop (PLL) to generate the two internal clock phases: phase one and phase two. The rising edge of CLK corresponds to the start of phase one (ph1). All external timing parameters are specified relative to the rising edge of CLK. Stop Clock The Am486DE2 CPU also provides an interrupt mech- anism, STPCLK , that allows system hardware to control the power consumption of the CPU by stopping the in- ternal clock to the CPU core in a sequenced manner. The first low-power state is called the Stop Grant state. If the CLK input is completely stopped, the CPU enters into the Stop Clock state (the lowest power state). When the CPU recognizes a STPCLK interrupt, the processor: ■ stops execution on the next instruction boundary (unless superseded by a higher priority interrupt) ■ waits for completion of cache flush ■ stops the pre-fetch unit ■ empties all internal pipelines and write buffers ■ generates a Stop Grant bus cycle ■ stops the internal clock At this point the CPU is in the Stop Grant state The CPU cannot respond to a STPCLK request from an HLDA state because it cannot empty the write buffers and, therefore, cannot generate a Stop Grant cycle. The rising edge of STPCLK signals the CPU to return to pro- gram execution at the instruction following the interrupt- ed instruction. Unlike the normal interrupts (INTR and NMI), STPCLK does not initiate interrupt acknowledge cycles or interrupt table reads. External Interrupts in Order of Priority In Write-through mode, the priority order of external in- terrupts is: 1. RESET/SRESET 2. FLUSH 3. SMI 4. NMI 5. INTR 6. STPCLK STPCLK is active Low and has an internal pull-up resis- tor. STPCLK is asynchronous, but setup and hold times must be met to ensure recognition in any specific clock. STPCLK must remain active until the Stop Grant special bus cycle is asserted and the system responds with ei- ther RDY or BRDY. When the CPU enters the Stop Grant state, the internal pull-up resistor is disabled, re- ducing the CPU power consumption. The STPCLK input must be driven High (not floated) to exit the Stop Grant state. STPCLK must be deasserted for a minimum of five clocks after RDY or BRDY is returned active for the Stop Grant bus cycle before being asserted again. There are two regions for the Low-Power-mode supply current: Low Power: Stop Grant state (fast wake-up, frequency- and voltage-dependent) 2. Lowest Power: Stop Clock state (slow wake-up, voltage-dependent)
nals that are three-stated during the HOLD/HLDA state. state they were before the HOLD/HLDA sequence. the input signals with pull-down resistors are not driven High. consumption during Stop Grant or Stop Clock modes. achieve the lowest possible power consumption. Table 2. Pin State During Stop Grant Bus State Figure 1. Entering Stop Grant State
20 Am486DE2 Microprocessor
Clock Control State Diagram Figure 2 shows the state transitions during a Stop Clock cycle. Normal State This is the normal operating state of the CPU. While in the normal state, the CLK input can be dynamically changed within the specified CLK period stability limits. Stop Grant State The Stop Grant state provides a low-power state that can be entered by simply asserting the external STPCLK interrupt pin. When the Stop Grant bus cycle has been placed on the bus, and either RDY or BRDY is returned, the CPU is in this state. The CPU returns to the normal execution state 10–20 clock periods after STPCLK has been deasserted. While in the Stop Grant state, the pull-up resistors on STPCLK and UP are disabled internally. The system must continue to drive these inputs to the state they were in immediately before the CPU entered the Stop Grant state. For minimum CPU power consumption, all other input pins should be driven to their inactive level while the CPU is in the Stop Grant state. A RESET or SRESET brings the CPU from the Stop Grant state to the Normal state. The CPU recognizes the inputs required for cache invalidations (HOLD, AHOLD, BOFF , and EADS), as explained later. The CPU does not recognize any other inputs while in the Stop Grant state. Input signals to the CPU are not rec- ognized until 1 clock after STPCLK is deasserted (see Figure 3). While in the Stop Grant state, the CPU does not recog- nize transitions on the interrupt signals (SMI, NMI, and INTR). Driving an active edge on either SMI or NMI does not guarantee recognition and service of the interrupt request following exit from the Stop Grant state. However, if one of the interrupt signals (SMI , NMI or INTR) is driven active while the CPU is in the Stop Grant state, and held active for at least one CLK after STPCLK is deasserted, the corresponding interrupt will be ser- viced. The Am486DE2 processor requires INTR to be held active until the CPU issues an interrupt acknowl- edge cycle to guarantee recognition. This condition also applies to the existing Am486 CPUs. In the Stop Grant state, the system can stop or change the CLK input. When the clock stops, the CPU enters the Stop Clock state. The CPU returns to the Stop Grant state immediately when the CLK input is restarted. You must hold the STPCLK input Low until a stabilized fre- quency has been maintained for at least 1 ms to ensure that the PLL has had sufficient time to stabilize. The CPU generates a Stop Grant bus cycle when en- tering the state from the Normal or the Auto Halt Power- Down state. When the CPU enters the Stop Grant state from the Stop Clock state or the Stop Clock Snoop state, the CPU does not generate a Stop Grant bus cycle. Stop Clock State Stop Clock state is entered from the Stop Grant state by stopping the CLK input (either logic High or logic Low). None of the CPU input signals should change state while the CLK input is stopped. Any transition on an input signal (except INTR) before the CPU has returned to the Stop Grant state may result in unpredictable behavior. If INTR goes active while the CLK input is stopped, and stays active until the CPU issues an interrupt acknowl- edge bus cycle, it is serviced in the normal manner. Sys- tem design must ensure the CPU is in the correct state prior to asserting cache invalidation or interrupt signals to the CPU. Auto Halt Power-Down State A HALT instruction causes the CPU to enter the Auto Halt Power-Down state. The CPU issues a normal HALT bus cycle, and only transitions to the Normal state when INTR, NMI, SMI , RESET, or SRESET occurs. The system can generate a STPCLK while the CPU is in the Auto Halt Power-Down state. The CPU generates a Stop Grant bus cycle when it enters the Stop Grant state from the HALT state. When the system deasserts the STPCLK interrupt, the CPU returns execution to the HALT state. The CPU generates a new HALT bus cycle when it reenters the HALT state from the Stop Grant state. SRESET FUNCTION The Am486DE2 microprocessor supports a soft reset function through the SRESET pin. SRESET forces the processor to begin execution in a known state. The pro- cessor state after SRESET is the same as after RESET except that the internal caches, CD and NW in CR0, write buffers, SMBASE registers, and floating-point reg- isters retain the values they had prior to SRESET, and cache snooping is allowed. The processor starts execu- tion at physical address FFFFFFF0h. SRESET can be used to help performance for DOS extenders written for the 80286 processor. SRESET provides a method to switch from Protected to Real mode while maintaining the internal caches, CR0, and the FPU state. SRESET may not be used in place of RESET after power-up.
22 Am486DE2 Microprocessor
The Am486DE2 microprocessor supports four modes: Real, Virtual, Protected, and System Management Mode (SMM). As an operating mode, SMM has a distinct processor environment, interface, and hardware/soft- ware features. SMM lets the system designer add new software-controlled features to the computer products that always operate transparent to the operating system (OS) and software applications. SMM is intended for use only by system firmware, not by applications software or general-purpose systems software. The SMM architectural extension consists of the follow- ing elements: 1. System Management Interrupt (SMI) hardware interface 2. Dedicated and secure memory space (SMRAM) for SMI handler code and CPU state (context) data with a status signal for the system to decode access to that memory space, SMIACT 3. Resume (RSM) instruction, for exiting SMM 4. Special features, such as I/O Restart and I/O instruction information, for transparent power management of I/O peripherals, and Auto Halt Restart Terminology The following terms are used throughout the discussion of System Management Mode. ■ SMM: System Management Mode. This is the operating environment that the processor (system) enters when servicing a System Management Interrupt. ■ SMI: System Management Interrupt. This is the trigger mechanism for the SMM interface. When SMI is asserted (SMI pin asserted Low), it causes the processor to invoke SMM. The SMI pin is the only means of entering SMM. ■ SMI handler: System Management Mode handler. This is the code that is executed when the processor is in SMM. An example application that this code might implement is a power-management-control or a system-control function. ■ RSM: Resume instruction. This instruction is used by the SMI handler to exit the SMM and return to the interrupted OS or application process. ■ SMRAM: This is the physical memory dedicated to SMM. The SMI handler code and related data reside in this memory. The processor also uses this memory to store its context before executing the SMI handler. The operating system and applications should not have access to this memory space. ■ SMBASE: This is a control register that contains the base address that defines the SMRAM space. ■ Context: This term refers to the processor state. The SMM discussion refers to the context, or processor state, just before the processor invokes SMM. The context normally consists of the CPU registers that fully represent the processor state. ■ Context Switch: A context switch is the process of either saving or restoring the context. The SMM discussion refers to the context switch as the process of saving/restoring the context while invoking/exiting SMM, respectively. ■ SMSAVE: A mechanism that saves and restores all internal registers to and from SMRAM. System Management Interrupt Processing The system interrupts the normal program execution and invokes SMM by generating a System Management Interrupt (SMI) to the CPU. The CPU services the SMI by executing the following sequence (see Figure 4). 1. The CPU asserts the SMIACT signal, instructing the system to enable the SMRAM. 2. The CPU saves its state (internal register) to SMRAM. It starts at the SMBASE relative address location (see “SMRAM” on page 24), and proceeds downward in a stack-like fashion. 3. The CPU switches to the SMM processor environment (an external pseudo-Real mode). 4. The CPU then jumps to the absolute address of SMBASE + 8000h in SMRAM to execute the SMI handler. This SMI handler performs the system management activities. Note: If the SMRAM shares the same physical address location with part of the system RAM, it is “overlaid” SMRAM. To preserved cache consistency and correct SMM operation in systems using overlaid SMRAM, the cache must be flushed via the FLUSH pin when entering SMM. 5. The SMI handler then executes the RSM instruction, which restores the CPU’s context from SMRAM, deasserts the SMIACT signal, and then returns control to the previously interrupted program execution.
24 Am486DE2 Microprocessor
designer-specific information. as SMI for systems using overlaid SMRAM. dress range from 38000h–3FFFFh as SMRAM area. Figure 6. SMI Timing for Servicing an I/O Trap
26 Am486DE2 Microprocessor
register images are read-only, and must not be modified. on values stored in a reserved area. must be saved to nonvolatile memory. isters in the CPU, it must also save and restore them. the three modes and then return. Table 3. SMRAM State Save Map Note: *Upper 2 bytes are not modified.
system management RAM (SMRAM). system or applications are disabled upon SMM entry. returns control to the interrupted program.
- Auto Halt Restart. It is possible for the SMI request
operation is to restart the HALT instruction.
- I/O Trap Restart. If the SMI was generated on an I/O
instruction by setting the I/O Trap Restart slot.
- SMBASE Relocation . The system can relocate the
aligned on 32-Kbyte boundaries. A RESET also causes execution to exit from SMM. are not acknowledged while the processor is in SMM. Figure 9. Transition to and from SMM
28 Am486DE2 Microprocessor
30000h, as shown in Table 5. loaded into the segment base cache. in the 4-Gbyte logical address space. cation from accidentally breaking into an SMI handler. Table 4. SMM Initial CPU Core Register Settings Table 5. Segment Register Initial States
- The segment limit check is 4 Gbyte instead of the usual
- The Selector value for CS remains at 3000h even if the
sure that an SMM-compliant debug handler is available. DR7 must then be initialized with the appropriate values. flag in the EFLAGS register (using the STI instruction). erties and location as the Real mode vector table. NMI interrupts are blocked on entry to the SMI handler. latched and serviced after the processor exits SMM. Only one NMI request is latched during the SMI handler. the next instruction of the interrupted code sequence. manner in which they are handled outside of SMM. at the time it performs a save state. in unpredictable processor behavior. Table 6. System Management Mode Revision Identifier Table 7. SMM Revision Identifier Bit Definitions
30 Am486DE2 Microprocessor
not in the internal cache), and execute a HALT bus cycle. the RSM instruction is executed. terrupted I/O instruction (see Figure 11). then the CPU does not reexecute the I/O instruction. has generated an SMI on an I/O instruction boundary. was a valid I/O instruction. Table 9 shows the layout. Figure 10. Auto Halt Restart Register Offset Table 8. Auto Halt Restart Configuration Figure 11. I/O Instruction Restart Register Offset Table 9. I/O Trap Word Configuration
32 Am486DE2 Microprocessor
not required (see Figure 17). exit (see Figure 16 and Figure 17). cache functionality to its pre-SMM state. Figure 14. SMRAM Location Figure 15. SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with
34 Am486DE2 Microprocessor
To account for these two situations, the system designer must ensure that A20M is deasserted on entry to SMM. A20M must be driven inactive before the first cycle of the SMM state save, and must be returned to its original level after the last cycle of the SMM state restore. This can be done by blocking the assertion of A20M when SMIACT is active. CPU Reset During SMM The system designer should take into account the fol- lowing restrictions while implementing the CPU Reset logic: ■ When running software written for the 80286 CPU, a CPU RESET switches the CPU from Protected mode to Real mode. RESET and SRESET have a higher priority than SMI . When the CPU is in SMM, the SRESET to the CPU during SMM should be blocked until the CPU exits SMM. SRESET must be blocked beginning from the time when SMI is driven active. Care should be taken not to block the global system RESET, which may be necessary to recover from a system crash. ■ During execution of the RSM instruction to exit SMM, there is a small time window between the deassertion of SMIACT and the completion of the RSM microcode. If a Protected mode to Real mode SRESET is asserted during this window, it is possible that the SMRAM space will be violated. The system designer must guarantee that SRESET is blocked until at least 20 CPU clock cycles after SMIACT has been driven inactive or until the start of a bus cycle. ■ Any request for a CPU RESET for the purpose of switching the CPU from Protected mode to Real mode must be acknowledged after the CPU has exited SMM. To maintain software transparency, the system logic must latch any SRESET signals that are blocked during SMM. For these reasons, the SRESET signal should be used for any soft resets, and the RESET signal should be used for all hard resets. SMM and Second-Level Write Buffers Before the processor enters SMM, it empties its internal write buffers. This is to ensure that the data in the write buffers is written to normal memory space, not SMM space. When the CPU is ready to begin writing an SMM state save to SMRAM, it asserts SMIACT . SMIACT may be driven active by the CPU before the system memory controller has had an opportunity to empty the second- level write buffers. To prevent the data from these second-level write buff- ers from being written to the wrong location, the system memory controller needs to direct the memory write cy- cles to either SMM space or normal memory space. This can be accomplished by saving the status of SMIACT with the address for each word in the write buffers. Nested SMI and I/O Restart Special care must be taken when executing an SMI han- dler for the purpose of restarting an l/O instruction. When the CPU executes a Resume (RSM) instruction with the l/O restart slot set, the restored EIP is modified to point to the instruction immediately preceding the SMI re- quest, so that the l/O instruction can be reexecuted. If a new SMI request is received while the CPU is executing an SMI handler, the CPU services this SMI request be- fore restarting the original I/O instruction. If the I/O re- start slot is set when the CPU executes the RSM instruction for the second SMI handler, the RSM micro- code decrements the restored EIP again. EIP then points to an address different from the originally inter- rupted instruction, and the CPU begins execution at an incorrect entry point. To prevent this from occurring, the SMI handler routine must not set the I/O restart slot dur- ing the second of two consecutive SMI handlers. SMM Software Considerations SMM Code Considerations The default operand size and the default address size are 16 bits; however, operand-size override and ad- dress-size override prefixes can be used as needed to directly access data anywhere within the 4-Gbyte logical address space. With operand-size override prefixes, the SMI handler can use jumps, calls and returns to transfer a control to any location within the 4-Gbyte space. Note, however, the following restrictions: ■ Any control transfer that does not have an operand- size override prefix truncates EIP to 16 Low-order bits. ■ Due to the Real mode style of base-address formation, a long jump or call cannot transfer control segment with a base address of more than 20 bits (1 Mbyte). Exception Handling Upon entry into SMM, external interrupts that require handlers are disabled (the IF in EFLAGS is cleared). This is necessary because, while the processor is in SMM, it is running in a separate memory space. Con- sequently, the vectors stored in the interrupt descriptor table (IDT) for the prior mode are not applicable. Before allowing exception handling (or software interrupts), the SMM program must initialize new interrupt and excep-
Am486DE2 Microprocessor 35 tion vectors. The interrupt vector table for SMM has the same format as for Real mode. Until the interrupt vector table is correctly initialized, the SMI handler must not generate an exception (or software interrupt). Even though hardware interrupts are disabled, exceptions and software interrupts can still occur. Only a correctly written SMI handler can prevent internal exceptions. When new exception vectors are initialized, internal ex- ceptions can be serviced. The restrictions follow: ■ Due to the Real mode style of base address formation, an interrupt or exception cannot transfer control to a segment with a base address of more than 20 bits. ■ An interrupt or exception cannot transfer control to a segment offset of more than 16 bits. ■ If exceptions or interrupts are allowed to occur, only the Low order 16 bits of the return address are pushed onto the stack. If the offset of the interrupted procedure is greater than 64 Kbytes, it is not possible for the interrupt/exception handler to return control to that procedure. (One workaround is to perform software adjustment of the return address on the stack.) ■ The SMBASE Relocation feature affects the way the CPU returns from an interrupt or exception during an SMI handler. Note: The execution of an IRET instruction enables Non-Maskable Interrupt (NMI) processing. HALT during SMM HALT should not be executed during SMM, unless in- terrupts have been enabled. Interrupts are disabled on entry to SMM. INTR and NMI are the only events that take the CPU out of HALT within SMM. Relocating SMRAM to an Address above 1 Mbyte Within SMM (or Real mode), the segment base registers can be updated only by changing the segment register. The segment registers contain only 16 bits, which allows only 20 bits to be used for a segment base address (the segment register is shifted left 4 bits to determine the segment base address). If SMRAM is relocated to an address above 1 Mbyte, the segment registers can no longer be initialized to point to SMRAM. These areas can still be accessed by using address override prefixes to generate an offset to the correct address. For example, if the SMBASE has been relo- cated immediately below 16M, the DS and ES registers are still initialized to 0000 0000h. Data in SMRAM can still be accessed by using 32-bit displacement registers: move esi,OOFFxxxxh;64K segment immediately below 16M move ax,ds:[esi]
36 Am486DE2 Microprocessor
provided in earlier Am486DX and DX2 microprocessors. tion of the field functions. up, this is the tag for the selected entry in the cache. valid bit for the selected entry and set. these are the four Valid bits of the accessed set. doublewords in a cache line. Table 10. Test Register (TR4) Table 11. Test Register (TR5)
Am486 and the Am486DX microprocessors. support for write-back cache. standard Am486DX microprocessor specification. ■ After reset, the STATUS bits of all lines are set to 0. CPU type/stepping identifier (see Table 13). position EFLAGS.21, referred to as the EFLAGS.ID bit. parameter values (see Table 14). Table 12. Am486DE2 Microprocessor Functional Differences Table 13. CPU ID Codes
38 Am486DE2 Microprocessor
The CPUID instruction requires the user to pass an input parameter to the CPU in the EAX register. The CPU response is returned to the user in registers EAX, EBX, ECX, and EDX. When the parameter passed in EAX is zero, the register values returned upon instruction execution are: The values in EBX, ECX, and EDX indicate an AMD microprocessor. When taken in the proper order: ■ EBX (least significant bit to most significant bit) ■ EDX (least significant bit to most significant bit) ■ ECD (least significant bit to most significant bit) they decode to: ‘AuthenticAMD’ When the parameter passed in EAX is 1, the register values returned are: The value returned in EAX after CPUID instruction ex- ecution is identical to the value loaded into EDX upon device reset. Software must avoid any dependency upon the state of reserved processor bits. When the parameter passed in EAX is greater than one, register values returned upon instruction execution are: Table 14. CPUID Instruction Description
Description
EAX[31:0] 00000001h EBX[31:0] 68747541h ECX[31:0] 444D4163h EDX[31:0] 69746E65h EAX[3:0] Stepping ID* EAX[7:4] Model: Am486DE2CPU— Write-through mode = 3h EAX[11:8] Family Am486 CPU = 4h EAX[15:12] 0000 EAX[31:16] RESERVED EBX[31:0] 00000000h ECX[31:0] 00000000h EDX[31:0] 00000001h = all versions The 1 in bit 0 indicates that the FPU is present Note: *Please contact AMD for stepping ID details. EAX[31:0] 00000000h EBX[31:0] 00000000h ECX[31:0] 00000000h EDX[31:0] 00000000h Flags affected: No flags are affected. Exceptions: None
Am486DE2 Microprocessor 39 ELECTRICAL DATA The following sections describe recommended electri- cal connections for the Am486DE2 microprocessor, and electrical specifications. Power Connections The Am486DE2 microprocessor has modest power re- quirements. However, the high clock-frequency output buffers can cause power surges as multiple output buff- ers drive new signal levels simultaneously. For clean, on-chip power distribution at high frequency, 23 V CC pins and 28 VSS pins feed the microprocessor in the 168-pin PGA package. The 208-lead SQFP package includes 53 V CC pins and 38 VSS pins. Power and ground connections must be made to all ex- ternal VCC and VSS pins of the microprocessors. On a circuit board, all VCC pins must connect to a VCC plane. Likewise, all VSS pins must connect to a common GND plane. The Am486DE2 microprocessor requires only 3.3 V as input power. Unlike other 3-V 486 processors, the Am486DE2 microprocessor does not require a VCC5 in- put of 5 V to indicate the presence of 5-V I/O devices on the system motherboard. For socket compatibility, this pin is INC (Internal No Connect), allowing the Am486DE2 CPU to operate in 3-V sockets in systems that use 5-V I/O. Power Decoupling Recommendations Liberal decoupling capacitance should be placed near the microprocessor. The microprocessor, driving its 32- bit parallel address and data buses at high frequencies, can cause transient power surges, particularly when driving large capacitive loads. Low-inductance capacitors and interconnects are rec- ommended for best high-frequency electrical perfor- mance. Inductance can be reduced by shortening circuit board traces between the microprocessor and the de- coupling capacitors. Capacitors designed specifically for use with PGA packages are commercially available. Other Connection Recommendations For reliable operation, always connect unused inputs to an appropriate signal level. Active Low inputs should be connected to V CC through a pull-up resistor. Pull-ups in the range of 20 kΩ are recommended. Active High in- puts should be connected to GND.
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cc +2.6 V Supply voltage with Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Operating Ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES VCC = 3.3 V ± 0.3 V; TCASE = 0°C to + 85°C Symbol Parameter Min Max Notes VIL Input Low Voltage – 0.3 V +0.8 V VIH Input High Voltage 2.0 V VCC + 2.4 V VOL Output Low Voltage 0.45 V Note 1 VOH Output High Voltage 2.4 V Note 2 ICC Power Supply Current: 66 MHz 660 mA Typical supply current: 528 mA @ 66 MHz Inputs at rails, outputs unloaded. ICCSTOPGRANT or ICCAUTOHALT Input Current in Stop Grant or Auto Halt mode:
66 MHz
66 mA Typical supply current for Stop Grant or Auto Halt mode: 20 mA @ 66 MHz and
75 MHz, 30 mA @ 80 MHz, 50 mA @
100 MHz, and 60 mA @ 120 MHz. ICCSTPCLK Input Current in Stop Clock mode 5 mA Typical supply current in Stop Clock mode is 600 µA. ILI Input Leakage Current ± 15 µA Note 3 IIH Input Leakage Current 200 µA Note 4 IIL Input Leakage Current – 400 µA Note 5 ILO Output Leakage Current ± 15 µA C IN Input Capacitance 10 pF FC = 1 MHz (Note 6) C O I/O or Output Capacitance 14 pF FC = 1 MHz (Note 6) C CLK CLK Capacitance 12 pF FC = 1 MHz (Note 6) Notes: 1. This parameter is measured at: Address, Data, BEn = 4.0 mA; Definition, Control = 5.0 mA 2. This parameter is measured at: Address, Data, BEn = - 1.0 mA; Definition, Control = - 0.9 mA 3. This parameter is for inputs without internal pull-ups or pull-downs and 0 ≤ VIN ≤ VCC . 4. This parameter is for inputs with internal pull-downs and VIH = 2.4 V. 5. This parameter is for inputs with internal pull-ups and VIL = 0.45 V. 6. Not 100% tested.
Figure 36. All timings are referenced to 1.5 V unless for correct microprocessor operation.
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Switching Characteristics for 33-MHz Bus (66-MHz Microprocessor) VCC = 3.3 V ±0.3 V; TCASE = 0°C to + 85°C; CL = 50 pF unless otherwise specified1 Symbol Parameter Min Max Unit Figure Notes Frequency 8 33 MHz Note 2 t1 CLK Period 30 125 ns 39 t1a CLK Period Stability 0.1% Δ Adjacent Clocks Notes 3 and 4 t2 CLK High Time at 2 V 11 ns 39 Note 3 t3 CLK Low Time at 0.8 V 11 ns 39 Note 3 t4 CLK Fall Time (2 V–0.8 V) 3 ns 39 Note 3 t5 CLK Rise Time (0.8 V–2 V) 3 ns 39 Note 3 A31–A2, PWT, PCD, BE3–BE0 , M/IO, D/C, CACHE , W/R , ADS, LOCK, FERR, BREQ, HLDA, SMIACT , HITM Valid Delay 3 14 ns 40 Note 5 t7 A31–A2, PWT, PCD, BE3–BE0 , M/IO, D/C, CACHE , W/R , ADS, LOCK Float Delay 3 20 ns 41 Note 3 t8 PCHK Valid Delay 3 14 ns 42 t8a BLAST , PLOCK, Valid Delay 3 14 ns 40 t9 BLAST , PLOCK, Float Delay 3 20 ns 41 Note 3 t10 D31–D0, DP3–DP0 Write Data Valid Delay 3 14 ns 40 t11 D31–D0, DP3–DP0 Write Data Float Delay 3 20 ns 41 Note 3 t12 EADS , INV, WB/WT Setup Time 5 ns 43 t13 EADS , INV, WB/WT Hold Time 3 ns 43 t14 KEN , BS16, BS8 Setup Time 5 ns 43 t15 KEN , BS16, BS8 Hold Time 3 ns 43 t16 RDY , BRDY Setup Time 5 ns 44 t17 RDY , BRDY Hold Time 3 ns 44 t18 HOLD, AHOLD Setup Time 6 ns 43 t18a BOFF Setup Time 7 ns 43 t19 HOLD, AHOLD, BOFF Hold Time 3 ns 43 t20 RESET, FLUSH , A20M, NMI, INTR, IGNNE, STPCLK , SRESET, SMI Setup Time 5 ns 43 Note 5 t21 RESET, FLUSH , A20M, NMI, INTR, IGNNE, STPCLK , SRESET, SMI Hold Time 3 ns 43 Note 5 t22 D31–D0, DP3–DP0, A31–A4 Read Setup Time 5 ns 43, 44 t23 D32–D0, DP3–DP0, A31–A4 Read Hold Time 3 ns 43, 44 Notes: 1. Specifications assume CL = 50 pF. I/O Buffer model must be used to determine delays due to loading (trace and component). First-order I/O buffer models for the processor are available. 2. 0-MHz operation guaranteed during stop clock operation or 1x Static Clock mode. 3. Not 100% tested. Guaranteed by design characterization. 4. For faster transitions (>0.1% between adjacent clocks), use the Stop Clock protocol to switch operating frequency. 5. All timings are referenced at 1.5 V (as illustrated in the listed figures) unless otherwise noted.
Figure 18. CLK Waveforms
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Figure 19. Output Valid Delay Timing Figure 20. Maximum Float Delay Timing
Figure 21. PCHK Valid Delay Timing
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Figure 22. Input Setup and Hold Timing
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top surface opposite the pins. 3.3 V as tabulated in the DC Characteristics. Figure 25. Test Signal Timing Diagram
*0.350″ high unidirectional heat sink (Al alloy 6063-T5, 40 mil fin width, 155 mil center-to-center fin spacing). Table 15. Thermal Resistance (°C/W) θJC and θJA for the Am486DE2 in 168-Pin PGA Package Table 16. Maximum TA at Various Airflows in °C Figure 26. . Heat Sink Dimensions
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Ceramic Pin Grid Array, CGM 168 1.735 1.765 1.735 1.765 Bottom View (Pins Facing Up) Base Plane Seating Plane 0.140 0.180 0.110 0.140 0.105 0.125 0.017 0.020 Side View 0.025 0.045 1.595 1.605 1.595 1.605 Index Corner 0.090 0.110 Notes: 1. All measurements are in inches. 2. Not to scale. For reference only. 3. BSC is an ANSI standard for Basic Space Centering.
Am486DE2 Microprocessor 51 208-Lead SQFP Shrink Quad Flat Pack, PDE 208 Seating Plane 30.40 30.80 See Detail H 27.90 28.10 25.50 REF 18.00 18.00 25.50 REF 27.90 28.10 30.40 30.80 Pin One I.D. 3.0 R Ref. Typ. Pin 1 Pin 208 Pin 156 Pin 104 Pin 52 –A– –D– –B– –A– –C– S S 4.00 0.25 0.42 3.25 3.45
0.50 Basic
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Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. DATUM Plane -A- is located at the mold parting line, and is coincedent with the bottom of the lead where the lead exits the plastic body. 3. Dimensions “D1" and ”E1" do not include mold protrusions. Allowable protrusion is 0.25mm per side. Dimensions “D1" and ”E1" include mold mismatch, and are determined at DATUM plane -A-. 4. Dimension “b” does not include DAMBAR protrusion. 5. Controlling dimensions: Millimeter. 6. Dimensions “D” and “E” are measured from outermost points. 7. Pin No. 1 ID may be inside top ejector mark, or separate. 8. Heatsink centerline to be aligned with package centerline ±0.30. 11. Lead coplanarity with respect to the seating plane shall not exeed 0.08[0.0031"]. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386, and Am486 are registered trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 0.10 0.20 Gage Plane 0.25 0.20± 0.10 0° Min. 0.40 Min. Flat Shoulder 12~ 16° 12~ 16° 0°-7° 0.084 4.00 Detail H 0.50 0.75 1.30 Nom. Section S-S 0.17 0.27 0.17 0.27