AM4701

AM4701 AMD | Alldatasheet

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Technical content

Dual 512 x 8 Bidirectional Parity Generator/Checker, D acre Bypass Mode, Programmable AE/AF Flags a DISTINCTIVE CHARACTERISTICS Two 512 x8 FIFO butters Programmable Almost-Full and Aimost-Empty Full and Empty Flags flags Bult in parity checker/generator it Bypass made—Changes the Am4701 toa ™@ Programmable Interrupt request . idiroction 1 maiibo ‘cation Generates and detects framing bit s A otek a x commun © Low power consumption yt on rea Bidirectional full duplex communication a GENERAL DESCRIPTION The Am4701 is a CMOS RAM-based, fully asynchro- most Empty condition. Parity generation/checking, pro- nous, byte-wide bidirectional First In First Out (FIFO) _grammable interrupt requests, byte-detection, framing device that is 512 words deep with 8-bit wide words in and port-to port communication through mail boxes are each direction. It contains two 512x9 FIFOs with the provided on chip. The Am4701 can also operate in By- ninth bit in each array used for framing and parity pass Mode where it behaves like a transceiver. ft fi . lunctions The Am4701 is ideally suited for bidirectional inter- The Am4701 can accept and output data asynchro- processor communication and data-buttering between ously and simultaneously at data rates from 0 to 22.2 aCPU and a peripheral device. The ability to bufferlarge MHz for standard commercial temperature range prod- _transfers of data and its rate adaption capabilities make ucts. Interrupt driven status flags are provided to signify the Am4701 useful in communication, image process- Full, Empty and userprogrammable Aimost Full and Al- ing, DSP and printing systems. BLOCK DIAGRAM 2-512 x 9 BIFIFO _ PontA Por B _ CIDA c/iB

9 Data 9 Data

DAO-7: Selector => Selector DBOo-7 i ba | | St2x9 | a0 ir it fom WRK Framing im K | Framing and Parity RDB RDA Gener/Checker FIFO Gener./Checker WRB GND Data AD. Data ° L | mu | TROQA — Registers S12x9 WR Registers ROB RD Addr. FIFO WR Addr, 11120C-1 2-124 Issue Date: September 1992

amo £4 PRODUCT SELECTOR GUIDE [Par Number | amavor-s5 | ama701-45 [AccessTime | a5ns 45s Maximum Power Supply [_120mA_ | 100mA_| Operating Frequency [22.2MHz_| _16.7MHz Operating Range CONNECTION DIAGRAMS Top View DIP PLCC cia J 1° 28 [] ROB <i < |e ical EBS oR ea WRA(}s 26 f] oa: ft 37 Tew) DAo 4 251] pBe DAL] 5 ° 29 f]pB, va: Ys 241) DBs pa, 6 28 [DB DA2 6 23 [] DBs DAL] 7 27 [Nc Vec []7 221] GND Vec[] 8 26 [JDB, DAs I & 2110) pps DAa[] 9 25 []GND enn 9 20 {] DBs GNO[] 10 24 [DBs DAs [J 10 19 [] DB7 oA 1 23 []0B. Nef] 12 22 []0B, W rn Das : 2 ° ; ae DAs[] 13 21 [] PARITY DAs i ‘ 1415 16 17 18 19 20 Dar (J13 16 |] ROB oj oo TAGE —— 111200-2 f\\gQoale moa = is fl coe 226 28BE 11120C-3 Notes: Pin 1 is marked for orientation for plastic packages. NC = No Connection. LOGIC SYMBOL 8 8 | Dto-Dar DBo-DB7K 52 PARITY PORT A CiDA cB PORT B RDA ‘ADB | WRA WRB] IROA IRQB) 11120C-4 Am4701 2-125

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of: AMA701 “35 P cB TL. or rionat processin Blank = Standard processing TEMPERATURE RANGE = Commercial (0°C to +70°C) PACKAGE TYPE P = 28-Pin Plastic DIP (PD 028) J. = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) ‘SPEED OPTION -35 = 35 nsta -45 = 45 ns ta DEVICE NUMBER/DESCRIPTION Am4701 Dual 512 x 8 Bidirectional Parity Generator/Checker, Bypass Mode, Programmable AE/AF Flags Valid Combinations Valid Combinations list configurations planned to Valid Combinations be supported in volume for this device. Consult the loca! AMD sales office to confirm availabilty of ‘AM4701-35 specific valid combinations, to check on newly re- PC, JC leased combinations, and to obtain additional data on AMD's standard military grade products. 2-126 Am4701

AMD Pa | PIN DESCRIPTION DA7DAo, DB7-DBo ci 8-bit bidirectional data bus for port A,B. Command/Data selection for port A or B. GID = High: Read or Write to the internal registers. PARITY C/D = Low: Read or Write to the FIFO. Bidirectional parity/raming bit (Port B only) TROA, ROB RDA, RDB Interrupt request output of port A, B. The TAC lag will be Read input forport A or B. The falling edge of Read initi- active low by any changes of status in the appropriate Glee a read trom the FIFO orthe internaltegisters. Both Port and is reset by reading the status register of the ports can be read simultaneously by RDA and RDB. bial rte Port's IRQ flag can be masked by its WRA, WRB Vee Write input to port A or B. The falling edge of Write initi- ates a write cycle. Data must be valid tow prior to WA Power Supply Pin, input, +5 Volts rising, and held valid throughout the write cycle. Boh = GND ports can write simultaneously by WRAand WRB, Ground Supply Pin, Input, 0 Volts Am4701 2-127

The Am4701 BiFIFO consists of two 512 x 8 FIFOs con- Read/Write Operations Nected to provide bidirectional FIFO actionbetweentwo —_am4701 read and write operations are controlled by RD, data ports, A and B. One FIFO provides buffering inthe Wrand C/D control ines for each port. AD gates BiFIFO direction from A to B; the other FIFO provides butfering gata to the bus, and the rising edge of the WR signal from Bto A. The Am4701 also provides a set of applica” _ latches data from the bus into registers or a FIFO in the tion specific support logic to support communicationbe- = am4701. tween microprocessors and peripheral devices. This _ logic includes the following functions: The C/B input selects the source or destination of the ic " data. When C/D is low, data is written into or read from * Optional FIFO bypass for direct data transfer the appropriate FIFO for that port, with one exception: 9th bit for framing bit generation when Port A is in the Bypass mode, data will be trans- ° ing bit generation and detect ferred directly between Port A and Port B, bypassing the © Optional parity generate and detect on Port B FIFOs. When C/D is high, data is written to orread from + Optional parity error insertion as framing bit one of the registers in the port register set. « Byte detect The register set for the Am4701 is shown in Table 1. All yt registers are read or written in a two cycle operation. * Mailbox registers The first cycle loads a Pointer register to select the regis- terto be read, and the second cycle performs the reador * Programmable Almost Empty and Almost Full write data transfer to the selected register. The Pointer flags register is cleared to zero by the data transfer cycle. Be- ite poi cause the Pointer register is cleared to zero, the Status + Read and write pointer reset register may also be read directly in a single cycle. This ‘* Interrupt on flag assertion is because the zero select code corresponds to the . . Status register. The Status register is therefore aways Operation of the Am4701 BiFIFO is controlled by wo selected and available to be read unless the Pointer reg- sets of registers, one for each port. Command registers ister has been set to another value. in each set determine the operating mode for each port, chip operations. The remaining registers in each set provide data to support status bit generation. Though Table 1- Register Address Assignments the registers will be reset to the default state during Reg power up, it is recommended to always use the master Addrs Read reset to ensure proper operation. An interrupt pin is pro- Videdtoreachport. Thispincanbeactivatedbybitsinits | _0 | Pointer | Status associated Status register and allow extemalhardware [1 | Command ‘| Command detection of a change in the status of the BiFIFO. a There are a variety of applications of the Am47o1 |_3_| Byte Detect _ Byte Detect _ BiFIFO. The bidirectional FIFO buffering feature simpli. {__4 | Outbound Mailbox [Outbound Mailbox fies CPU to CPU communication. The parity logic on [ 5 | AE/AF «|: AB/AF Port B allows convenient communication between a [6 _| Reset Read Pointer | Inbound Mailbox CPU anda bus which requires parity generation and de- Reset Write Pointer] =i tection. The direct connect transceiver function provides efficient communication of command and status data between a CPU and a peripheral chip such as a disk controller while the FIFO function provides efficient butt- ering of its high speed data. 2-128 Am4701

7 6 5 4 3 2 1 ° Ley TT 7 Peat] 111206-5 The Pointer register contents select which register inthe ister select cycle and register data transfer cycle. The register set is to be read or written, as shown in Table 1. Pointer register is set by the register select cycle, and it The Pointer register is a write-only register. All register is reset to zero by the completion of the data transfer cy- accesses are performed in two consecutive cycles: reg- cle. The format of the Pointer register is as follows. Bit Name Function FB Framing Bit Writes a framing bit into the FIFO. This bit is set by writing it twice to the Pointer register. An 80 (hex) code is written to select the Pointer register and an 80 code is written to the Pointer register during the transfer cycle. A2-AO Reg Select Selects a register for read or write transfer per Table 1. See Command Register 7 6 5 4 3 2 1 ° 1112066 The Command register sets the operating mode for and Port B can enable its parity generate/detect logic as each port. The Command register format for Port A and well as determine its polarity. The format of the com- Port B are different. Port Acanbe put into Bypass mode, mand registers is as follows. Bit Name Function MR Master Reset Software master reset. Resets both FIFOs and the register sets on both ports. Either port can set the master reset bit. The MR bit in the command register must be written twice consecu tively and the status register of the same port must be read to complete a master reset opera- tion. This prevents accidental resets. Setting the MR inthe command register sets the MR bit in both status registers. SH Shift Selects the FULL, EMPTY, AE and AF flags from the other port for display in the Status regis- ter. This allows displaying current status of the other port. BP Bypass Bypass mode select (Port A only). See Bypass mode section. PE Parity Enable Parity generate and check enable. (Port B only.) When this bitis set, the parity logic on Port B generates and checks bus parity at the Port B I/O inputs. See Parity Generate and Check section. PO/PE Odd/Even Parity Odd or Even select. PO/PE = 1 for odd parity, PO/PE = 0 for even. Status Register 7 6 5 4 3 2 1 0 [we Tru [ewer] ar Tae ] wa | bor [pero] 111200-7 The Status register indicates the status of various condi- condition causing the bit to be set is still prevalent, then tions on its associated port. The bits in the status regis- reading the status counter makes these bit “dynamic” terwill be set automatically when those conditions occur and reflect the real condition of the FIFO until the FIFO. and will activate the TRQ pin for the appropriate port. _exits and re-enters that condition. Then, the IRQ signal Reading the Status register will clear the PE/FD, MR, and the appropriate bit will be asserted again. Note that and the BDT bits. The mailbox bit is cleared by reading when the Shift bit in the Command register is a one, the the Inbound Mailbox register. FULL, EMPTY, AF, and Status register will display the FULL, EMPTY, AF, and AE are cleared by reading the status register provided AE flags for the other port. The format of the Status reg- the condition making the bit go true ceased to exist. Ifthe ister is as follows. Am4701 2-129

MR Master Set when either port has issued a master reset. The MR bit will be cleared by reading the Reset status register. FULL Full Outbound FIFO is full. Write command will be ignored as long as the FIFO is tull. The flag is. cleared by reading the status register and reading the FIFO in either order (see explanation above). The flag is also cleared by MR. EMPT Empty Inbound FIFO is empty. Read command will be ignored as long as the FIFO is empty. The flags cleared by reading the status register and writing to the FIFO in either order (see expla- nation above). The flag is also cleared by MR. AF Almost Outbound FIFO is almost full. Set when the FIFO reaches or exceeds the depth limit pro- Full grammed into the AE/AF register. Cleared by reading the status register and making the FIFO go below the depth limit (see explanation above). The flag is also cleared by MR. AE Almost Inbound FIFO is almost empty. Set when the FIFO reaches or is under the depth limit pro- Empty grammed into the AE/AF register. Cleared by reading the status register and making the FIFO go above the depth limit (see explanation above). The flag is also cleared by MR MB Mailbox The Inboard Mailbox register has been written into by the other port. Cleared by reading the Inbound Mailbox register or by MR. BDT Byte Set when the data at the output of the inbound FIFO matches the data in the Byte Detect Detect register. Cleared by reading Status register or MR. PE/FD Parity Error! Set by the 9thbit of the inbound FIFO. Indicates a framing bit or Frame Detect parity errorwas Frame Detect inserted into the FIFO by the other port. Cleared by reading Status register or MR Mask Register 7 6 5 4 3 2 1 ° [Tru [ewer] ar [ae [wo [ sor [Pe 5] 11120C-8 The Mask register masks the bits of the Status register ‘sponding bit in the Status register; a zero in the Mask which will generate the interrupt request, IRQ. The bits register disables it. The MR bit of the Status register is are set in the Status register by the appropriate condi- —_ unmaskable and will aways cause an interrupt when tions but do not trigger the IRQ signal if masked out. A —_set. The bit definitions for the Mask register are the ‘one in the Mask register enables interrupt by the corre- same as for the Status register. Byte Detect Register 7z 6 5 4 3 2 1 0 Lo Jo Tos To | om | om] o | & | 11120C-9 The Byte Detect register contains aprogrammable byte —_Byte Detect register, the BDT flag in the Status register to be detected while reading the FIFO. When the data _is set. being read from the FIFO matches the contents of the 2-130 ‘Am4701

amo © AE/AF Register 7 6 5 4 3 2 1 CO) [ars [Are | afr] Aro | aes [ ace | ats [ At | 111206-10 The contents of the AE/AF register defines the limits for and (512-16) for the Almost full flag. A code of F for the Almost Empty and Almost Full flags. Limit program- either limit corresponds to 256 for the Almost empty flag ming is done in increments of 16. A code of 0 (hex) for and (512-256) forthe Almost Full flag. Master reset sets either limit corresponds to 16 for the Almost Empty flag _ this register to 00 (hex code). Bit Name Function AFs0 Almost Full Almost Full limit code: 0000 = 16, 0001 = 32, etc. 1111 = 256. AEso Almost Empty Almost Empty limit code: 0000 = (512-16), 0001 = (512-32), etc. EE Outbound Mailbox Register 7 6 5 4 3 2 1 ° 191200-11 Each port has an 8-bit mailbox where it can receive mes- The Outbound Mailbox register can be read as well as sages fromthe other port. The mailbox for agivenportis written. The contents of the Outbound Mailbox register called the Inbound Mailbox. The mailbox for the other will be cleared to zero and zeros will be read back when port is called the outbound Mailbox. The Outbound Mail- the other port reads its Inbound Mailbox register. This box register is the mailbox register for the other port. can be used to determine whether the other port has re- This register is written into when a message is to be sent ceived the message. to the other port. Writing to this register will cause the MB bit to be set in the Status register of the other port and will cause a mailbox interrupt on that port if enabled by its Mask register. EE Inbound Mailbox Register 7 6 5 4 3 2 1 ° [or To. Tos | To [To | & | vooa 111200. The Inbound Mailbox register receives 8-bit messages When the mailbox register has been written into, the MB. from the other port. The other port sends a message by bit is set in the Status register. The MB bit is reset and writing into its Outbound Mailbox register. The message ‘the mailbox register is cleared to zeros when the In- thus written appears in the Inbound Mailbox for this port. bound Mailbox register is read. FIFO Read and Write Pointer Reset The read pointer for the inbound FIFO and the write Resetting the read or write pointers may cause errone- pointer for the outbound FIFO can be reset by writing ‘ous AF and AE flags. Only a master reset will cause with the appropriate register select code. The operation correct AF and AE flags. It is recommended that the requires two cycle as for any other register write opera- AF and AE flags be masked by the Mask register when. tion: address latching and a (dummy) write. No data is using these pointer reset commands. actually transferred, but the appropriate pointer is reset. Resetting the write pointer allows overwriting a block that may have contained bad data. Resetting the read pointer allows rereading a block. Am4701 2131

Master Reset ter of the same port must be read to complete a master i reset operation. This prevents accidental resets. Setting The master reset operation resets both FIFOs andthe the NR in the command register sets the MR bit in both register sets on both ports. Either port caninitiate amas- status registers. A master reset sequence is outlined ter reset operation. The MR bit in the command register. Below: 7 must be written twice consecutively and the status regis- . Port 1 Port 2 Port 1 writes a 1 into the MR bit of the command register (a 2-cycle register operation). Port 1 writes a 1 into the MR bit of the command register (a 2-cycle register operation) again. Both TAG signals are asserted ‘The MR bits in both status registers are set It port 2 reads its status register, its TRO signal will be deasserted. The MR bit in the status register will not be cleared. Port 1 reads its status register ‘The master reset operation is complete Port 1 TRO signal is deasserted ‘The MR bit of port 1's status register is cleared. It port 2 has already read its status register, the MR bit will now be cleared. If port 2 has not read its status register yet, both TRG and the MR bit will be cleared once port 2 reads it. After a master reset, the Am4701 will come up in the detault state described below. Both FIFOs cleared to empty ‘* Command registers cleared — Port A Bypass mode disabled ~ Port B Parity generate and detect disabled * AEJAF register cleared to zero: i.e., AF and AE flags set to 16 * Mask registers set to Full and Empty flags only enabled + TRGis deasserted on both ports due to Master Reset (despite Empty condition on both ports) The registers will typically be reset to the default state by power up; however, this power up reset cannot be guar- anteed. Therefore, a Master Reset should always be performed after power up to insure proper operation. Status Interrupts Status register interrupts are used to signal the CPU on ” , “ a port that something interesting has happened rather Ita condition for an interrupt occurs, the corresponding Ps " “it bitin the status register will be automatically set. lt that. “84 having to continually poll for activity. bit is enabled by its corresponding bit in the Mask regis- a ter, the IRQ signal for that port will be asserted. Reading Framing Bit the status register clears the IRQ signal and may clear The FIFOs in the Am4701 are 512 x 9 in organization. Haran rtnwiten oan arty bac soar en isthe Eight data bits communicate wih the external port data , Mailbox bit which can only be cleared by reading —_byses; the ninth bit is used as a framing bit to identi the Inbound Mailbox register. " no ity 2-132 Am4701

in the FB location and address 0. This willcause aoneto _ingly. port that a block of data has been received. truth table for this operation is shown in Table 2. to the bus provides the required bus parity bit along with the other port is a “slave” only. mand registeris set, datacoming into the FiFOonportB and register data transfer. Table 2. Bypass Mode Truth Table

Mailbox Operations The Outbound Mailbox register can be read as well as Each porthas ané-bit mailbox where itcanreceivemes- Witten. The contents of the Outbound Mailbox register ' will be cleared to zero and zeros will be read back when Sages from the other port. The mailbox for agivenportis the other port reads its inbound Mailbox register. This called the Inbound Mailbox. The mailbox for the other an be used to determine whether the other port has re- Portis called the outbound Mailbox. The Outbound Mail Ceiveq the message box register is the mailbox register for the other port. 7 This register is written into when a message istobe sent An example of the mailbox passing protocol is given to the other port. Writing to this register will cause the below. MB bit to be set in the Status register of the other port and will cause a mailbox interrupt on that port if enabled by its Mask register. Port 1 Port 2 Port 1 writes a message byte to Port 2 by writing to its Outbound Mailbox register Port 2 TRO signal is asserted and MB bit set Port,2 reads its Status register and recognizes the MB bit. The IRQ signal is reset. Port 2 reads its Incoming Mailbox. The mailbox fagister, and the MB bit are reset. Port 1 reads the message it wrote in its ‘Outbound Mailbox register. If all bits are zero, Port 2 must have read its mail. 2-134 Am4701

APPLICATIONS

The Am4701 provides bidirectional butfering of high Figure 2 shows an example of the Am4701 used to pro- speed digital data. ts application support logic makes it. —_ vide communication between a CPU anda bus with byte well suited to providing communication between two parity. In this case, the parity generation and check logic CPUs, between a CPU and a bus and between a CPU available on Port B is used to provide the parity genera- and a peripheral device. tion and checking required by the bus. The Am4701 pro- . vides this function without requiring any external logic, An example of a simple 8-bit CPU-to-CPU connection is i anas in chit shown in Figure 1. In this case, parity is not used, and a conplonty a savings in chip count, board space and simple, high speed communication pathis setup using a single chip. Card #1 CPU Ht PORTA ‘Am4701 PORTB iRQ Ra cD WR RD Bit -_ = CY wef | Parity Bit Not Connected 111206-13, Figure 1. CPU-CPU Communication

8 Bit

set of the Am4701. The bidirectional FIFO function pro- direct manner. Figure 3. CPU-Perlpheral Communication with Bypass

amo £4 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute ‘maximum ratings for extended periods may affect device reli- ability. Absolute maximum ratings are for system design refer- ence; parameters given are not tested. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter | Parameter Test |___cown_] Symbol__| Description Conditions La | une | Output High Vou = 2.4 V, mA Current Voc = 4.5 V Output Low Va=0.4V, +6.0 Current Voc =4.5V Vin Input High (Note 1) Veco +0.5] V Voltage Va Input LOW v Voltage Input Leakage GND < Vi < Veo -10 BA Current Voc = 5.5V Output Leakage GND <VoursVec | -10 HA Current Voc = 5.5V Static Operating GND < Vour < Voc mA Supply Current Voc = 5.5 V (Note 2) Dynamic Operating GND < Vout < Veo 100 | mA Current, (16.7 MHz Max.) | Voc = 5.5 V (Note 2) loca Dynamic Operating GND < Vour $ Vec Current, (22.5 MHz Max.) | Voc = 5.5 V (Note 2) Notes: 1. Vivand Vin are input conditions of output tests and are not themselves directly tested. Vit and Via are absolute voltages with respect to device ground and include all overshoots due to system and/ortester noise. Do not attempt to test these values without suitable equipment. 2, lec measurements are made with outputs open. CAPACITANCE (Note 3) (Vcc = 5.0 V, Ta = 25°C, f = 1.0 MHz) Parameter Symbol Parameter Descriptions Test Conditions [Gr | Input Capacitance [vweov InpuvOutput Capacitance Note: 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected Am4z701 2137

SWITCHING CHARACTERISTICS over COMMERCIAL operating range unless otherwise Specified [_ com. | = | 35ns_ | a5ns | ama Description Lin. [ wax_[ win. [ max | [1 [we | Aeadooeime Ts TT co fT | [2 [tm | ReadAccessime | | 5 | Tass | [3 [tw | Read Accesstimewin Panty || 45 | ss ns | [+ | tw | ReadPusewith | os TT as [ns | [5 | twa | ReadRecoveytime | to OT Ts Ts | [6 | ton | Ouputtowaterad | Ss | Ts | ns | [7 [wz [rdtowtooupuaave Ts PTs TT ns | [s [tz | ROHigntoOupudsabie || as Tf 30 Ts | [e [| tw | CHoWtimeaternDorwA | 5 | | 6 fs | [10 [us | cioSewpTimetondorwa [| s [ [5 {| ns | [11 [twos [Write EndtoBeginRead(notea) [20 | [0 [ns | [12 [ wor | ReadendioBeonwine woes | 20 [ | ao | I os | [13 [tw | witecycetme | as TT oo fs | [aa] we | wine Puwewam Sit | |e | [as [tow [Data seupimewowa siz ao | | oT | [te | tor | Datars time aterwa ‘| o | | s | | rs | [are wite Reooveytine SSS tf | | [ae [| Far tnvougn tine is | | oo | | [21 [mar | witetowioin@rw Furtiag | | 4s | | 55 Ts | [21 | maz | witemowtoIRabw (aria | | 85 | dT 75 [rs | [22 | twas [| witerintomoow | Ts | as [ns | [es [ww [Read status higntoiROngh | {35 | | 6 | rs | 24] tru Read low to IRQ low To [aera TT TEL [24 | tune | ReadiowtoRGiow(Acfag | | 5 [Ts Ts | [25 | tau | Readhigntomaiow | Tas | Tas ns | [2s [inn | ReadowiomBtagrest | | | | | ve | [27 [ie Fiow Through Delay (Gypassy Ts TT oo TT ts | Notes: 4, This parameter refers to read/write on the same port. 5. Switching Wavelorms Reterence numbers. *” Subgroups 7 and 8 apply to functional tests. SS 2-138 Am4701

Input pulse levels GND to 3.0 V Veo Input rise and fall times [5n5 si Input timing reference levels wk Output timing reference levels Output Output loads See AC Test Load 6802 == 30pF* - 11120C-16 * Includes jig and scope capacitances AC Test Load KEY TO SWITCHING WAVEFORMS. WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady : May Will Be Change Changing fromHtoL from H to May Will Bo Change Changing fromLtoH —— fromLtoH Don't Care, Changing Any Change State Permitted Unknown Does Not Center Apply Line is High Impedence “OH” State KS000010 am4701 2-139

Re (1) Tas (10) TAH 9) ha KK ee eee _ a a ADA, ROB t * RA (2), TRAP (3) H2(8) Bes ber K<<GED), tz tou (6), ‘LB (27) DBO - DB7 — [Fon daa Pon Adan hye oke DAo - DA7 Port AB data to Port B/A data in Bypass Mode 11120C-17 Read Timing twe (13) TAS (10) taH (9) ey ha ae ee > Gee ee ae RDA, ROB V N twe (14) DBO - DB7 | > ‘tow (15) toH (16) 11120C-18 Write Timing 2-140 Am4701

amo £4 SWITCHING WAVEFORMS WRA, WRB ADA, ROB TWLIL1,2 (21 t 'RLILY2 83 IRHIH (23) TARGA, IROB "RLIH (26) 'RHIH (26) TROA, TROB ‘WHIL (22) 'RHIL (25) 111200-19 1RQ Timing Am4701 2-141