AM45DL3208G

AM45DL3208G AMD | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am45DL3208G Data Sheet Publication Number 26460 Revision B Amendment +1 Issue Date March 12, 2004

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26460 Rev: B Amendment/+1 Issue Date: March 12, 2004 Refer to AMD’s Website (www.amd.com) for the latest information. Am45DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance Access time as fast as 70 ns Package 73-Ball FBGA Operating Temperature –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations Data can be continuously read from one bank while executing erase/program functions in another bank. Zero latency between read and write operations Flexible Bank™ architecture Read may occur in any of the three banks not being written or erased. Four banks may be grouped by customer to achieve desired bank divisions. Manufactured on 0.17 µm process technology SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data Customer lockable: Sector is one-time programmable. Once sector is locked, data cannot be changed. Zero Power Operation Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. Top or bottom boot sectors Compatible with JEDEC standards Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance Access time as fast as 70 ns Program time: 4 µs/word typical utilizing Accelerate function Ultra low power consumption (typical values) 2 mA active read current at 1 MHz 10 mA active read current at 5 MHz 200 nA in standby or automatic sleep mode Minimum 1 million write cycles guaranteed per sector 20 year data retention at 125°C Reliable operation for the life of the system SOFTWARE FEATURES Data Management Software (DMS) AMD-supplied software manages data programming, enabling EEPROM emulation Eases historical sector erase flash limitations Supports Common Flash Memory Interface (CFI) Program/Erase Suspend/Erase Resume Suspends program/erase operations to allow programming/erasing in same bank Data# Polling and Toggle Bits Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) Hardware method of resetting the internal state machine to the read mode WP#/ACC input pin Write protect (WP#) function protects sectors 0 and 1 (bottom boot) or 69 and 70 (top boot), regardless of sector protect status Acceleration (ACC) function accelerates program timing Sector protection Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector Temporary Sector Unprotect allows changing data in protected sectors in-system Pseudo SRAM Features Power dissipation Operating: 30 mA maximum Standby: 100 µA maximum CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 2.7 to 3.3 volt Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

March 12, 2004 P R E L I M I N A R Y GENERAL DESCRIPTION Am29DL320G Features The Am29DL320G is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70 or 85 ns and is offered in a 73-ball FBGA package. Standard control pins—chip enable (CE#f), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 4 Mb banks with small and large sectors, and two 12 Mb banks of large sectors only. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can im- prove overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL320G can be organized as both a top and bottom boot sector configuration. The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, cus- tomer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as a one-time programmable area. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and soft- ware integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Bank Megabits Sector Sizes Bank 1 4 Mb Eight 8 Kbyte/4 Kword, Seven 64 Kbyte/32 Kword Bank 2 12 Mb Forty-eight 64 Kbyte/32 Kword Bank 3 12 Mb Forty-eight 64 Kbyte/32 Kword Bank 4 4 Mb Sixteen 64 Kbyte/32 Kword

March 12, 2004 Am45DL3208G P R E L I M I N A R Y PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am45DL3208G Speed Options Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory Pseudo SRAM Max Access Time (ns) CE#f Access (ns) OE# Access (ns) VSS/VSSQ VCCs/VCCQ RESET# WE# CE#f OE# CE1#s VSS VCCf RY/BY# LB#s UB#s CIOf WP#/ACC CE2s SA CIOs

8 MBit

32 MBit

A–1 A18 to A0

March 12, 2004 P R E L I M I N A R Y FLASH MEMORY BLOCK DIAGRAM VCC VSS Bank 1 Address Bank 2 Address A20–A0 RESET# WE# CE# BYTE# DQ15–DQ0 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Bank 1 X-Decoder OE# BYTE# DQ15–DQ0 Status Control A20–A0 A20–A0 A20–A0 A20–A0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank 2 X-Decoder Y-gate Bank 3 X-Decoder Bank 4 X-Decoder Y-gate Bank 3 Address Bank 4 Address

March 12, 2004 Am45DL3208G P R E L I M I N A R Y CONNECTION DIAGRAM Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC NC NC NC CE#f CE1#s VSS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 NC WP#/ACC RESET# RY/BY# DQ3 VCCf DQ11 NC WE# CE2s A20 DQ4 VCCs CIOs A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 SA DQ15/A-1 DQ7 DQ14 A15 NC NC A16 CIOf VSS NC NC NC NC NC NC Pseudo SRAM only Shared Flash only 73-Ball FBGA Top View

March 12, 2004 P R E L I M I N A R Y PIN DESCRIPTION A18–A0 = 19 Address Inputs (Common) A20–A19, A-1 = 3 Address Inputs (Flash) SA = Lowest Order Address Pin (PSRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#1s = Chip Enable 1 (PSRAM) CE2s = Chip Enable 2 (PSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (PSRAM) LB#s = Lower Byte Control (PSRAM) CIOf = I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) CIOs = I/O Configuration (PSRAM) CIOs = VIH = Word mode (x16), CIOs = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = PSRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ15–DQ0 A18–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC SA A20–A19, A-1 LB#s CIOf CIOs CE1#s CE2s

March 12, 2004 Am45DL3208G P R E L I M I N A R Y

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-3 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am45DL320 G T I T TAPE AND REEL T 7 inches S 13 inches TEMPERATURE RANGE I Industrial (–40°C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT SECTOR T Top boot B Bottom boot PROCESS TECHNOLOGY G 0.17 µm PSEUDO SRAM DEVICE DENSITY

8 Mbits

AMD DEVICE NUMBER/DESCRIPTION Am45DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL320G 32 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Pseudo Static RAM Valid Combinations Order Number Package Marking Am45DL3208GT70I Am45DL3208GB70I T, S M450000008 M450000009 Am45DL3208GT85I Am45DL3208GB85I T, S M45000000A M45000000B

March 12, 2004 P R E L I M I N A R Y Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH; P SRAM Word Mode, CIOs = VCC Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = PSRAM Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# SA Addr. LB#s UB#s RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ8 Read from Flash L H X L H X AIN X X H L/H DOUT DOUT X L Write to Flash L H X H L X AIN X X H (Note 4) DIN DIN X L Standby VCC ± 0.3 V H X X X X X X X VCC ± 0.3 V H High-Z High-Z X L Output Disable L L H H H X X L X H L/H High-Z High-Z H H X X X L Flash Hardware Reset X H X X X X X X X L L/H High-Z High-Z X L Sector Protect (Note 5) L H X H L X SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X X L Sector Unprotect (Note 5) L H X H L X SADD, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X X L Temporary Sector Unprotect X H X X X X X X X VID (Note 6) DIN High-Z X L Read from PSRAM H L H L H X AIN L L H X DOUT DOUT H L High-Z DOUT L H DOUT High-Z Write to PSRAM H L H X L X AIN L L H X DIN DIN H L High-Z DIN L H DIN High-Z

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Table 2. Device Bus Operations—Flash Word Mode, CIOf = VIH; PSRAM Byte Mode, CIOs = VSS Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = PSRAM Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# SA Addr. LB#s (Note 3) UB#s (Note 3) RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ8 Read from Flash L H X L H X AIN X X H L/H DOUT DOUT X L Write to Flash L H X H L X AIN X X H (Note 3) DIN DIN X L Standby VCC ± 0.3 V H X X X X X X X VCC ± 0.3 V H High-Z High-Z X L Output Disable L L H H H SA X X X H L/H High-Z High-Z Flash Hardware Reset X H X X X X X X X L L/H High-Z High-Z X L Sector Protect (Note 5) L H X H L X SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X X L Sector Unprotect (Note 5) L H X H L X SADD, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X X L Temporary Sector Unprotect X H X X X X AIN X X VID (Note 6) DIN High-Z X L Read from PSRAM H L H L H SA AIN X X H X DOUT High-Z Write to PSRAM H L H X L SA AIN X X H X DIN High-Z

March 12, 2004 P R E L I M I N A R Y Table 3. Device Bus Operations—Flash Byte Mode, CIOf = VSS; PSRAM Word Mode, CIOs = VCC Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = PSRAM Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# SA Addr. LB#s (Note 3) UB#s (Note 3) RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ8 Read from Flash L H X L H X AIN X X H L/H DOUT High-Z X L Write to Flash L H X H L X AIN X X H (Note 3) DIN High-Z X L Standby VCC ± 0.3 V H X X X X X X X VCC ± 0.3 V H High-Z High-Z X L Output Disable L L H H H X X L X H L/H High-Z High-Z X L Flash Hardware Reset X H X X X X X X X L L/H High-Z High-Z X L Sector Protect (Note 5) L H X H L X SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X X L Sector Unprotect (Note 5) L H X H L X SADD, A6 = L, A1 = H, A0 = L X X VID (Note 6) DIN X X L Temporary Sector Unprotect X H x X X X AIN X X VID (Note 6) DIN High-Z X L Read from PSRAM H L H L H X AIN L L H X DOUT DOUT H L High-Z DOUT L H DOUT High-Z Write to PSRAM H L H X L X AIN L L H X DIN DIN H L High-Z DIN L H DIN High-Z

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Table 4. Device Bus Operations—Flash Byte Mode, CIOf = VIL; PSRAM Byte Mode, CIOs = VSS Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = PSRAM Address Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection”. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. FLASH DEVICE BUS OPERATIONS Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ15–DQ0 are active and controlled by CE#f and OE#. If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are active and controlled by CE#f and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to VIL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at VIH. The CIOf pin determines Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# SA Addr. LB#s (Note 3) UB#s (Note 3) RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ8 Read from Flash L H X L H X AIN X X H L/H DOUT High-Z X L Write to Flash L H X H L X AIN X X H (Note 3) DIN High-Z X L Standby VCC ± 0.3 V H X X X X X X X VCC ± 0.3 V H High-Z High-Z X L Output Disable H L H H H SA X X X H L/H High-Z High-Z Flash Hardware Reset X H X X X X X X X L L/H High-Z High-Z X L Sector Protect (Note 5) L H X H L X SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X X L Sector Unprotect (Note 5) L H X H L X SADD, A6 = L, A1 = H, A0 = L X X VID (Note 6) DIN X X L Temporary Sector Unprotect X H X X X X AIN X X VID (Note 6) DIN High-Z X L Read from SRAM H L H L H SA AIN X X H X DOUT High-Z Write to SRAM H L H X L SA AIN X X H X DIN High-Z

March 12, 2004 P R E L I M I N A R Y whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Read-Only Operations table for timing specifications and to Figure 15 for the timing diagram. ICC1 in the DC Characteristics table represents the ac- tive current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to VIL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more in- formation. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Byte/Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 5 and 7 indicate the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. The “Flash Command Defini- tions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase opera- tion. The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The Flash AC Characteristics section contains timing specifica- tion tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to nor- mal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. See “Write Protect (WP#)” on page 20 for related infor- mation. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Se- quence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 22 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6f and ICC7f in the table represent the cur- rent specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE#f and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de- vice requires standard access time (tCE) for read ac- cess when the device is in either of these standby modes, before it is ready to read data.

March 12, 2004 Am45DL3208G P R E L I M I N A R Y If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3f in the table represents the standby current spec- ification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5f in the table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4f). If RESET# is held at VIL but not within VSS±0.3 V, the standby cur- rent will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo- rithms). The system can read data tRH after the RE- SET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 5. Top Boot Sector Addresses Bank Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Bank 4 SA0 000000xxx 000000h–00FFFFh 000000h–07FFFh SA1 000001xxx 010000h–01FFFFh 008000h–0FFFFh SA2 000010xxx 020000h–02FFFFh 010000h–17FFFh SA3 000011xxx 030000h–03FFFFh 018000h–01FFFFh SA4 000100xxx 040000h–04FFFFh 020000h–027FFFh SA5 000101xxx 050000h–05FFFFh 028000h–02FFFFh SA6 000110xxx 060000h–06FFFFh 030000h–037FFFh SA7 000111xxx 070000h–07FFFFh 038000h–03FFFFh Bank 3 SA8 001000xxx 080000h–08FFFFh 040000h–047FFFh SA9 001001xxx 090000h–09FFFFh 048000h–04FFFFh SA10 001010xxx 0A0000h–0AFFFFh 050000h–057FFFh SA11 001011xxx 0B0000h–0BFFFFh 058000h–05FFFFh SA12 001100xxx 0C0000h–0CFFFFh 060000h–067FFFh SA13 001101xxx 0D0000h–0DFFFFh 068000h–06FFFFh SA14 001110xxx 0E0000h–0EFFFFh 070000h–077FFFh SA15 001111xxx 0F0000h–0FFFFFh 078000h–07FFFFh SA16 010000xxx 100000h–10FFFFh 080000h–087FFFh SA17 010001xxx 110000h–11FFFFh 088000h–08FFFFh SA18 010010xxx 120000h–12FFFFh 090000h–097FFFh

March 12, 2004 P R E L I M I N A R Y Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits are A20–A18. Bank 3 (continued) SA19 010011xxx 130000h–13FFFFh 098000h–09FFFFh SA20 010100xxx 140000h–14FFFFh 0A0000h–0A7FFFh SA21 010101xxx 150000h–15FFFFh 0A8000h–0AFFFFh SA22 010110xxx 160000h–16FFFFh 0B0000h–0B7FFFh SA23 010111xxx 170000h–17FFFFh 0B8000h–0BFFFFh SA24 011000xxx 180000h–18FFFFh 0C0000h–0C7FFFh SA25 011001xxx 190000h–19FFFFh 0C8000h–0CFFFFh SA26 011010xxx 1A0000h–1AFFFFh 0D0000h–0D7FFFh SA27 011011xxx 1B0000h–1BFFFFh 0D8000h–0DFFFFh SA28 011100xxx 1C0000h–1CFFFFh 0E0000h–0E7FFFh SA29 011101xxx 1D0000h–1DFFFFh 0E8000h–0EFFFFh SA30 011110xxx 1E0000h–1EFFFFh 0F0000h–0F7FFFh SA31 011111xxx 1F0000h–1FFFFFh 0F8000h–0FFFFFh Bank 2 SA32 100000xxx 200000h–20FFFFh 100000h–107FFFh SA33 100001xxx 210000h–21FFFFh 108000h–10FFFFh SA34 100010xxx 220000h–22FFFFh 110000h–117FFFh SA35 100011xxx 230000h–23FFFFh 118000h–11FFFFh SA36 100100xxx 240000h–24FFFFh 120000h–127FFFh SA37 100101xxx 250000h–25FFFFh 128000h–12FFFFh SA38 100110xxx 260000h–26FFFFh 130000h–137FFFh SA39 100111xxx 270000h–27FFFFh 138000h–13FFFFh SA40 101000xxx 280000h–28FFFFh 140000h–147FFFh SA41 101001xxx 290000h–29FFFFh 148000h–14FFFFh SA42 101010xxx 2A0000h–2AFFFFh 150000h–157FFFh SA43 101011xxx 2B0000h–2BFFFFh 158000h–15FFFFh SA44 101100xxx 2C0000h–2CFFFFh 160000h–167FFFh SA45 101101xxx 2D0000h–2DFFFFh 168000h–16FFFFh SA46 101110xxx 2E0000h–2EFFFFh 170000h–177FFFh SA47 101111xxx 2F0000h–2FFFFFh 178000h–17FFFFh SA48 110000xxx 300000h–30FFFFh 180000h–187FFFh SA49 110001xxx 310000h–31FFFFh 188000h–18FFFFh SA50 110010xxx 320000h–32FFFFh 190000h–197FFFh SA51 110011xxx 330000h–33FFFFh 198000h–19FFFFh SA52 110100xxx 340000h–34FFFFh 1A0000h–1A7FFFh SA53 110101xxx 350000h–35FFFFh 1A8000h–1AFFFFh SA54 110110xxx 360000h–36FFFFh 1B0000h–1B7FFFh SA55 110111xxx 370000h–37FFFFh 1B8000h–1BFFFFh Bank 1 SA56 111000xxx 380000h–38FFFFh 1C0000h–1C7FFFh SA57 111001xxx 390000h–39FFFFh 1C8000h–1CFFFFh SA58 111010xxx 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA59 111011xxx 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA60 111100xxx 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA61 111101xxx 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA62 111110xxx 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA63 111111000 3F0000h–3F1FFFh 1F8000h–1F8FFFh SA64 111111001 3F2000h–3F3FFFh 1F9000h–1F9FFFh SA65 111111010 3F4000h–3F5FFFh 1FA000h–1FAFFFh SA66 111111011 3F6000h–3F7FFFh 1FB000h–1FBFFFh SA67 111111100 3F8000h–3F9FFFh 1FC000h–1FCFFFh SA68 111111101 3FA000h–3FBFFFh 1FD000h–1FDFFFh SA69 111111110 3FC000h–3FDFFFh 1FE000h–1FEFFFh SA70 111111111 3FE000h–3FFFFFh 1FF000h–1FFFFFh Table 5. Top Boot Sector Addresses (Continued) Bank Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Table 6. Top Boot SecSi™ Sector Addresses Device Sector Address A20–A12 Sector Size (Bytes/Words) (x8) Address Range (x16) Address Range Am29DL320GT 111111xxx 3FE000h–3FE0FFh 1F0000h–1FF07Fh Table 7. Bottom Boot Sector Addresses Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Bank 1 SA0 000000000 000000h–001FFFh 000000h–000FFFh SA1 000000001 002000h–003FFFh 001000h–001FFFh SA2 000000010 004000h–005FFFh 002000h–002FFFh SA3 000000011 006000h–007FFFh 003000h–003FFFh SA4 000000100 008000h–009FFFh 004000h–004FFFh SA5 000000101 00A000h–00BFFFh 005000h–005FFFh SA6 000000110 00C000h–00DFFFh 006000h–006FFFh SA7 000000111 00E000h–00FFFFh 007000h–007FFFh SA8 000001xxx 010000h–01FFFFh 008000h–00FFFFh SA9 000010xxx 020000h–02FFFFh 010000h–017FFFh SA10 000011xxx 030000h–03FFFFh 018000h–01FFFFh SA11 000100xxx 040000h–04FFFFh 020000h–027FFFh SA12 000101xxx 050000h–05FFFFh 028000h–02FFFFh SA13 000110xxx 060000h–06FFFFh 030000h–037FFFh SA14 000111xxx 070000h–07FFFFh 038000h–03FFFFh Bank 2 SA15 001000xxx 080000h–08FFFFh 040000h–047FFFh SA16 001001xxx 090000h–09FFFFh 048000h–04FFFFh SA17 001010xxx 0A0000h–0AFFFFh 050000h–057FFFh SA18 001011xxx 0B0000h–0BFFFFh 058000h–05FFFFh SA19 001100xxx 0C0000h–0CFFFFh 060000h–067FFFh SA20 001101xxx 0D0000h–0DFFFFh 068000h–06FFFFh SA21 001110xxx 0E0000h–0EFFFFh 070000h–077FFFh SA22 001111xxx 0F0000h–0FFFFFh 078000h–07FFFFh SA23 010000xxx 100000h–10FFFFh 080000h–087FFFh SA24 010001xxx 110000h–11FFFFh 088000h–08FFFFh SA25 010010xxx 120000h–12FFFFh 090000h–097FFFh SA26 010011xxx 130000h–13FFFFh 098000h–09FFFFh SA27 010100xxx 140000h–14FFFFh 0A0000h–0A7FFFh SA28 010101xxx 150000h–15FFFFh 0A8000h–0AFFFFh SA29 010110xxx 160000h–16FFFFh 0B0000h–0B7FFFh SA30 010111xxx 170000h–17FFFFh 0B8000h–0BFFFFh SA31 011000xxx 180000h–18FFFFh 0C0000h–0C7FFFh SA32 011001xxx 190000h–19FFFFh 0C8000h–0CFFFFh SA33 011010xxx 1A0000h–1AFFFFh 0D0000h–0D7FFFh SA34 011011xxx 1B0000h–1BFFFFh 0D8000h–0DFFFFh SA35 011100xxx 1C0000h–1CFFFFh 0E0000h–0E7FFFh SA36 011101xxx 1D0000h–1DFFFFh 0E8000h–0EFFFFh SA37 011110xxx 1E0000h–1EFFFFh 0F0000h–0F7FFFh SA38 011111xxx 1F0000h–1FFFFFh 0F8000h–0FFFFFh

March 12, 2004 P R E L I M I N A R Y Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits are A20–A18. Table 8. Bottom Boot SecSi™ Sector Addresses Bank 3 SA39 100000xxx 200000h–20FFFFh 100000h–107FFFh SA40 100001xxx 210000h–21FFFFh 108000h–10FFFFh SA41 100010xxx 220000h–22FFFFh 110000h–117FFFh SA42 100011xxx 230000h–23FFFFh 118000h–11FFFFh SA43 100100xxx 240000h–24FFFFh 120000h–127FFFh SA44 100101xxx 250000h–25FFFFh 128000h–12FFFFh SA45 100110xxx 260000h–26FFFFh 130000h–137FFFh SA46 100111xxx 270000h–27FFFFh 138000h–13FFFFh SA47 101000xxx 280000h–28FFFFh 140000h–147FFFh SA48 101001xxx 290000h–29FFFFh 148000h–14FFFFh SA49 101010xxx 2A0000h–2AFFFFh 150000h–157FFFh SA50 101011xxx 2B0000h–2BFFFFh 158000h–15FFFFh SA51 101100xxx 2C0000h–2CFFFFh 160000h–167FFFh SA52 101101xxx 2D0000h–2DFFFFh 168000h–16FFFFh SA53 101110xxx 2E0000h–2EFFFFh 170000h–177FFFh SA54 101111xxx 2F0000h–2FFFFFh 178000h–17FFFFh SA55 111000xxx 300000h–30FFFFh 180000h–187FFFh SA56 110001xxx 310000h–31FFFFh 188000h–18FFFFh SA57 110010xxx 320000h–32FFFFh 190000h–197FFFh SA58 110011xxx 330000h–33FFFFh 198000h–19FFFFh SA59 110100xxx 340000h–34FFFFh 1A0000h–1A7FFFh SA60 110101xxx 350000h–35FFFFh 1A8000h–1AFFFFh SA61 110110xxx 360000h–36FFFFh 1B0000h–1B7FFFh SA62 110111xxx 370000h–37FFFFh 1B8000h–1BFFFFh Bank 4 SA63 111000xxx 380000h–38FFFFh 1C0000h–1C7FFFh SA64 111001xxx 390000h–39FFFFh 1C8000h–1CFFFFh SA65 111010xxx 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA66 111011xxx 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA67 111100xxx 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA68 111101xxx 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA69 111110xxx 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA70 111111xxx 3F0000h–3FFFFFh 1F8000h–1FFFFFh Table 7. Bottom Boot Sector Addresses (Continued) Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Device Sector Address A20–A12 Sector Size (Bytes/Words) (x8) Address Range (x16) Address Range Am29DL320GB 000000xxx 000000h–0000FFh 00000h–00007Fh

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 9 and 10). The hardware sector protection feature disables both program and erase operations in any sector. The hard- ware sector unprotection feature re-enables both pro- gram and erase operations in previously protected sectors. Sector protection/unprotection can be imple- mented via two methods. Table 9. Top Boot Sector/Sector Block Addresses for Protection/Unprotection Table 10. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Note that the sector unprotect algorithm un- protects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector un protect function is available. See “Temporary Sector Unprotect”. Sector Protection/Unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 27 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previ- Sector A20–A12 Sector/ Sector Block Size SA0 000000XXX

64 Kbytes

SA1–SA3 000001XXX, 000010XXX 000011XXX 192 (3x64) Kbytes SA4–SA7 0001XXXXX 256 (4x64) Kbytes SA8–SA11 0010XXXXX 256 (4x64) Kbytes SA12–SA15 0011XXXXX 256 (4x64) Kbytes SA16–SA19 0100XXXXX 256 (4x64) Kbytes SA20–SA23 0101XXXXX 256 (4x64) Kbytes SA24–SA27 0110XXXXX 256 (4x64) Kbytes SA28–SA31 0111XXXXX 256 (4x64) Kbytes SA32–SA35 1000XXXXX 256 (4x64) Kbytes SA36–SA39 1001XXXXX 256 (4x64) Kbytes SA40–SA43 1010XXXXX 256 (4x64) Kbytes SA44–SA47 1011XXXXX 256 (4x64) Kbytes SA48–SA51 1100XXXXX 256 (4x64) Kbytes SA52–SA55 1101XXXXX 256 (4x64) Kbytes SA56–SA59 1110XXXXX 256 (4x64) Kbytes SA60–SA62 111100XXX, 111101XXX, 111110XXX 192 (4x64) Kbytes SA63 111111000

8 Kbytes

A20–A12 Sector/Sector Block Size SA70 111111XXX 111110XXX, 111101XXX, 111100XXX 192 (3x64) Kbytes SA66-SA63 1110XXXXX 256 (4x64) Kbytes SA62-SA59 1101XXXXX 256 (4x64) Kbytes SA58-SA55 1100XXXXX 256 (4x64) Kbytes SA54-SA51 1011XXXXX 256 (4x64) Kbytes SA50-SA47 1010XXXXX 256 (4x64) Kbytes SA46-SA43 1001XXXXX 256 (4x64) Kbytes SA42-SA39 1000XXXXX 256 (4x64) Kbytes SA38-SA35 0111XXXXX 256 (4x64) Kbytes SA34-SA31 0110XXXXX 256 (4x64) Kbytes SA30-SA27 0101XXXXX 256 (4x64) Kbytes SA26-SA23 0100XXXXX 256 (4x64) Kbytes SA22–SA19 0011XXXXX 256 (4x64) Kbytes SA18-SA15 0010XXXXX 256 (4x64) Kbytes SA14-SA11 0001XXXXX 256 (4x64) Kbytes SA10-SA8 000011XXX, 000010XXX, 000001XXX 192 (3x64) Kbytes SA7 000000111

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Figure 2. In-System Sector Protect/Unprotect Algorithms Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Set up sector address Wait 150 µs Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs First Write Cycle = 60h? Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Yes Yes No PLSCNT = 25? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Set up first sector address Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Read from sector address with A6 = 1, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs Data = 00h? Last sector verified? Remove VID from RESET# Write reset command Sector Unprotect complete Yes No PLSCNT = 1000? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No All sectors protected? Yes Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Set up next sector address No Yes No Yes No No Yes No Sector Protect Algorithm Sector Unprotect Algorithm First Write Cycle = 60h? Protect another sector? Reset PLSCNT = 1

March 12, 2004 P R E L I M I N A R Y SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sec- tor unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lock- able version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable de- vices from being used to replace devices that are fac- tory locked. The system accesses the SecSi Sector Secure through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector com- mand sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command se- quence, or until power is removed from the device. On power-up, or following a hardware reset, the device re- verts to sending commands to the first 256 bytes of Sector 0. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number will at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). The secure ESN will be programmed in the next 8 words at addresses 000008h–00000Fh (or 000010h–000020h in byte mode). The device is available preprogrammed with one of the following: ■A random, secure ESN only ■Customer code through the ExpressFlash service ■Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Re- gion without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region com- mand sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Figure 3. SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 15 and 16 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle, CE#f and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 11–14. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is exe- cuting an Embedded Program or embedded Erase al- gorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 11–14. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alterna- tively, contact an AMD representative for copies of these documents. Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 START RESET# = VIH or VID Wait 1 µs Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write reset command SecSi Sector Protect Verify complete

March 12, 2004 P R E L I M I N A R Y Table 11. CFI Query Identification String Addresses (Word Mode) Addresses (Byte Mode) Data

Description

Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists)

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Table 12. System Interface String Table 13. Device Geometry Definition Addresses (Word Mode) Addresses (Byte Mode) Data VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2 N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2 N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2 N times typical (00h = not supported) Addresses (Word Mode) Addresses (Byte Mode) Data Device Size = 2 N byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2 N (00h = not supported) 2Ch 58h 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 003Eh 0000h 0000h 0001h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)

March 12, 2004 P R E L I M I N A R Y Table 14. Primary Vendor-Specific Extended Query Addresses (Word Mode) Addresses (Byte Mode) Data Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h 8Ah 0004h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode 4Ah 94h 0038h Simultaneous Operation 00 = Not Supported, X = Number of Sectors (excluding Bank 1) 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 9Ch 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 9Eh 000xh Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device

March 12, 2004 Am45DL3208G P R E L I M I N A R Y FLASH COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Tables 15 and 16 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to read- ing array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the section for more information. The Read-Only Opera- tions table provides the read parameters, and Figure 15 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Tables 15 and 16 show the address and data require- ments. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SADD). Tables 5 and 7 show the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi

March 12, 2004 P R E L I M I N A R Y Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Tables 15 and 16 show the address and data require- ments for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the CIOf pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cy- cles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. Tables 15 and 16 show the ad- dress and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Tables 15 and 16 show the re- quirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Flash Erase and Program Opera- tions table in the AC Characteristics section for parameters, and Figure 19 for timing diagrams.

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Table 15. Command Definitions (Flash Word Mode) Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SADD = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Notes: See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. Unless otherwise noted, address bits A20–A12 are don’t cares. No unlock or command cycles required when bank is in read mode. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. See the Autoselect Command Sequence section for more information. The device ID must be read across three cycles. The device ID is 01h for top boot and 00h for bottom boot. 10. The data is 82h for factory locked and 02h for not factory locked. 11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Command Sequence (Note 1) Cycles Bus Cycles (Notes 2–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 6) RA RD Reset (Note 7) XXX Autoselect (Note 8) Manufacturer ID 555 AA 2AA (BA)555 (BA)X00 0001 Device ID (Note 9) 555 AA 2AA (BA)555 (BA)X01 (BA) (BA) 0000/ 0001 SecSi Sector Factory Protect (Note 10) 555 AA 2AA (BA)555 (BA)X03 Sector Protect Verify (Note 11) 555 AA 2AA (BA)555 (SADD) X02 Enter SecSi Sector Region 555 AA 2AA 555 Exit SecSi Sector Region 555 AA 2AA 555 XXX Program 555 AA 2AA 555 PA PD Unlock Bypass 555 AA 2AA 555 Unlock Bypass Program (Note 12) XXX PA PD Unlock Bypass Reset (Note 13) XXX XXX Chip Erase 555 AA 2AA 555 555 AA 2AA 555 Sector Erase 555 AA 2AA 555 555 AA 2AA SADD Erase Suspend (Note 14) BA Erase Resume (Note 15) BA CFI Query (Note 16)

March 12, 2004 P R E L I M I N A R Y Table 16. Command Definitions (Flash Byte Mode) Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SADD = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Notes: See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. Unless otherwise noted, address bits A20–A12 are don’t cares. No unlock or command cycles required when bank is in read mode. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information. The device ID must be read across three cycles. The device ID is 00h for top boot and 01h for bottom boot. 10. The data is 80h for factory locked and 00h for not factory locked. 11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Command Sequence (Note 1) Cycles Bus Cycles (Notes 2–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 6) RA RD Reset (Note 7) XXX Autoselect (Note 8) Manufacturer ID AAA AA 555 (BA) AAA (BA) 00 Device ID (Note 9) AAA AA 555 (BA) AAA (BA) 02 (BA) (BA) SecSi™ Sector Factory Protect (Note 10) AAA AA 555 (BA) AAA (BA) X06 Sector Protect Verify (Note 11) AAA AA 555 (BA) AAA (SADD) X04 Enter SecSi Sector Region AAA AA 555 AAA Exit SecSi Sector Region AAA AA 555 AAA XXX Program AAA AA 555 AAA PA PD Unlock Bypass AAA AA 555 AAA Unlock Bypass Program (Note 12) XXX PA PD Unlock Bypass Reset (Note 13) XXX XXX Chip Erase AAA AA 555 AAA AAA AA 555 AAA Sector Erase AAA AA 555 AAA AAA AA 555 SADD Erase Suspend (Note 14) BA Erase Resume (Note 15) BA CFI Query (Note 16)

March 12, 2004 P R E L I M I N A R Y Table 17. Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle N/A No toggle Embedded Erase Algorithm Toggle Toggle Erase Suspend Mode Erase-Suspend- Read Erase Suspended Sector No toggle N/A Toggle Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle N/A N/A

March 12, 2004 P R E L I M I N A R Y Notes: The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. Not 100% tested. FLASH DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V µA ILIT RESET# Input Load Current VCC = VCC max; RESET# = 12.5 V µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current VCC = VCC max, WP#/ACC = VACC max µA ICC1f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Byte Mode

5 MHz

1 MHz

CE#f = VIL, OE# = VIH, Word Mode Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL mA ICC3f Flash VCC Standby Current (Note 2) VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCCf ± 0.3 V 0.2 µA ICC4f Flash VCC Reset Current (Note 2) VCCf = VCC max, RESET# = VSS ± 0.3 V, WP#/ACC = VCCf ± 0.3 V 0.2 µA ICC5f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCCf = VCC max, VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 µA ICC6f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = VIL, OE# = VIH Byte mA Word ICC7f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH Byte mA Word ICC8f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = VIL, OE#f = VIH mA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 VCC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCCf = VCCs = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCCf = VCCs = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

March 12, 2004 P R E L I M I N A R Y Pseudo SRAM DC AND OPERATING CHARACTERISTICS (NOTE 1) Notes: 1. TA= –40° to 85°C, otherwise specified. 2. Overshoot: VCC+1.0V if pulse width ≤ 20 ns. 3. Undershoot: –1.0V if pulse width ≤ 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested. 5. Stable power supply required 200 µs before device operation. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC Operating Power Supply Current IIO = 0 mA, CE1#s = VIL, CE2s = VIH, VIN = VIH or VIL mA ICC1s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V mA ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH mA VIL Input Low Voltage –0.2 (Note 3) 0.4 V VIH Input High Voltage 2.2 VCC+0.2 (Note 2) V VOL Output Low Voltage IOL = 2.0 mA 0.4 V VOH Output High Voltage IOH = –1.0 mA 2.2 V ISB Standby Current (TTL) CE1#s = VIH, CE2 = VIL, Other inputs = VIH or VIL 0.3 mA ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –

0.2 V (CE1#s controlled) or CE2 ≤

0.2 V (CE2s controlled), CIOs =

VSS or VCC, Other input = 0 ~ VCC 100 µA

March 12, 2004 Am45DL3208G P R E L I M I N A R Y TEST CONDITIONS Table 18. Test Specifications KEY TO SWITCHING WAVEFORMS 2.7 kΩ CL 6.2 kΩ 3.3 V Device Under Test Note: Diodes are IN3064 or equivalent Figure 12. Test Setup Test Condition 70, 85 Unit Output Load

1 TTL gate

Output Load Capacitance, CL (including jig capacitance) pF Input Rise and Fall Times ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V KS000010-PAL WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 3.0 V 0.0 V 1.5 V 1.5 V Output Measurement Level Input Figure 13. Input Waveforms and Measurement Levels

March 12, 2004 P R E L I M I N A R Y AC CHARACTERISTICS Pseudo SRAM CE#s Timing Figure 14. Timing Diagram for Alternating Between Pseudo SRAM and Flash Parameter CE#s Recover Time Min ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

March 12, 2004 Am45DL3208G P R E L I M I N A R Y FLASH AC CHARACTERISTICS Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 12 and Table 18 for test specifications 3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF Parameter Std. Unit tAVAV tRC Read Cycle Time (Note 1) Min ns tAVQV tACC Address to Output Delay CE#f, OE# = VIL Max ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max ns tGLQV tOE Output Enable to Output Delay Max ns tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max ns tAXQX tOH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min ns tOEH Output Enable Hold Time (Note 1) Read Min ns Toggle and Data# Polling Min ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF Figure 15. Read Operation Timings

March 12, 2004 P R E L I M I N A R Y FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min ns tRPD RESET# Low to Standby Mode Min µs tRB RY/BY# Recovery Time Min ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#f, OE# tRH CE#f, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB Figure 16. Reset Timings

March 12, 2004 P R E L I M I N A R Y FLASH AC CHARACTERISTICS Flash Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options Unit JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time (WE# to Address) Min ns tASO Address Setup Time to OE# or CE#f Low During Toggle Bit Polling Min ns tWLAX tAH Address Hold Time (WE# to Address) Min ns tAHT Address Hold Time From CE#f or OE# High During Toggle Bit Polling Min ns tDVWH tDS Data Setup Time Min ns tWHDX tDH Data Hold Time Min ns tOEH OE# Hold Time Read Min ns Toggle and Data# Polling Min ns tOEPH Output Enable High During Toggle Bit Polling Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) Min ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min ns tELWL tCS CE#f Setup Time (WE# to CE#f) Min ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min ns tWHEH tCH CE#f Hold Time (CE#f to WE#) Min ns tWLWH tWP Write Pulse Width Min ns tELEH tCP CE#f Pulse Width Min ns tWHDL tWPH Write Pulse Width High Min ns tSR/W Latency Between Read and Write Operations Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ µs Word Typ tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCCf Setup Time (Note 1) Min µs tRB Write Recovery Time From RY/BY# Min ns tBUSY Program/Erase Valid To RY/BY# Delay Max ns

March 12, 2004 P R E L I M I N A R Y FLASH AC CHARACTERISTICS OE# CE#f Addresses VCCf WE# Data 2AAh SADD tGHWL tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH In Progress Complete tWHWH2 VA VA Erase Command Sequence (last two cycles) Read Status Data RY/BY# tRB tBUSY Notes: 1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”. These waveforms are for the word mode. Figure 21. Chip/Sector Erase Operation Timings

March 12, 2004 Am45DL3208G P R E L I M I N A R Y FLASH AC CHARACTERISTICS Temporary Sector Unprotect Note: Not 100% tested. Parameter All Speed Options JEDEC Std VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min µs RESET# tVIDR VID VSS, VIL, or VIH VID VSS, VIL, or VIH CE#f WE# RY/BY# tVIDR tRSP Program or Erase Command Sequence tRRB Figure 26. Temporary Sector Unprotect Timing Diagram

March 12, 2004 P R E L I M I N A R Y FLASH AC CHARACTERISTICS Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms 1 µs RESET# SADD, A6, A1, A0 Data CE#f WE# OE# 60h 60h 40h Valid* Valid* Valid* Status Sector/Sector Block Protect or Unprotect Verify VID VIH * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address. Figure 27. Sector/Sector Block Protect and Unprotect Timing Diagram

March 12, 2004 Am45DL3208G P R E L I M I N A R Y FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time Min ns tELAX tAH Address Hold Time Min ns tDVEH tDS Data Setup Time Min ns tEHDX tDH Data Hold Time Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time Min ns tEHWH tWH WE# Hold Time Min ns tELEH tCP CE#f Pulse Width Min ns tEHEL tCPH CE#f Pulse Width High Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ µs Word Typ tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

March 12, 2004 P R E L I M I N A R Y FLASH AC CHARACTERISTICS tGHEL tWS OE# CE#f WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# DOUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase tBUSY Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SADD = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Pseudo SRAM AC CHARACTERISTICS Power Up Time When powering up the SRAM, maintain VCCs for 100 µs minimum with CE#1s at VIH. Read Cycle Notes: 1. CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL 2. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs. Figure 29. Pseudo SRAM Read Cycle—Address Controlled Parameter Symbol tCO1, tCO2 Chip Enable to Output Max ns tOE Output Enable Access Time Max ns tBA LB#s, UB#s to Access Time Max ns tLZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output Min ns tBLZ UB#, LB# Enable to Low-Z Output Min ns tOLZ Output Enable to Low-Z Output Min ns tHZ1, tHZ2 Chip Disable to High-Z Output Max ns tBHZ UB#s, LB#s Disable to High-Z Output Max ns tOHZ Output Disable to High-Z Output Max ns tOH Output Data Hold from Address Change Min ns Address Data Out Previous Data Valid Data Valid tAA tRC tOH

March 12, 2004 P R E L I M I N A R Y Pseudo SRAM AC CHARACTERISTICS Read Cycle Notes: 1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing. 2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. 4. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs. Figure 30. Pseudo SRAM Read Cycle Data Valid High-Z tRC CE#1s Address OE# Data Out tOH tAA tCO1 tOE tOLZ tBLZ tLZ tOHZ tHZ CE2s tCO2

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Pseudo SRAM AC CHARACTERISTICS Write Cycle Notes: 1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 31. Pseudo SRAM Write Cycle—WE# Control Parameter Symbol Chip Enable to End of Write Min ns tAS Address Setup Time Min ns tAW Address Valid to End of Write Min ns tBW UB#s, LB#s to End of Write Min ns tWP Write Pulse Time Min ns tWR Write Recovery Time Min ns tWHZ Write to Output High-Z Min ns Max tDW Data to Write Time Overlap Min ns tDH Data Hold from Write Time Min ns tOW End Write to Output Low-Z min ns Address CE1#s Data Undefined WE# Data In Data Out tWC tCW (See Note 1) tAW High-Z High-Z Data Valid CE2s tCW (See Note 1) tWP (See Note 4) tAS (See Note 3) tWR tDW tDH tOW tWHZ

March 12, 2004 P R E L I M I N A R Y Pseudo SRAM AC CHARACTERISTICS Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 32. Pseudo SRAM Write Cycle—CE1#s Control Address Data Valid UB#s, LB#s WE# Data In Data Out High-Z High-Z tWC CE1#s CE2s tAW tAS (See Note 2 ) tBW tCW (See Note 3) tWR (See Note 4) tWP (See Note 5) tDW tDH

March 12, 2004 Am45DL3208G P R E L I M I N A R Y Pseudo SRAM AC CHARACTERISTICS Notes: 1. UB#s and LB#s controlled, CIOs must be high. 2. tCW is measured from CE1#s going low to the end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. tAS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (tWP) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 33. Pseudo SRAM Write Cycle— UB#s and LB#s Control Address Data Valid UB#s, LB#s WE# Data In Data Out High-Z High-Z tWC CE1#s CE2s tAW tBW tDW tDH tWR (See Note 3) tAS (See Note 4) tCW (See Note 2) tCW (See Note 2) tWP (See Note 5)

March 12, 2004 P R E L I M I N A R Y FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 15 and 16 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time sec Byte Program Time 150 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 120 µs Word Program Time 210 µs Chip Program Time (Note 3) Byte Mode sec Word Mode Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 pF COUT Output Capacitance VOUT = 0 pF CIN2 Control Pin Capacitance VIN = 0 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C Years 125°C Years

March 12, 2004 P R E L I M I N A R Y PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm

002h for not factory locked. Programmed or Protected at the factory. are not available when the SecSi sector is enabled. Changed CFI website address. Table 15. Command Definitions (Flash Word Mode) Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc.

©2003 Advanced Micro Devices, Inc. Printed in USA One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400 TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics.The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. For specific testing details, contact your local AMD sales representative.The company assumes no responsibility for the use of any circuits described herein. © Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo and combination thereof, are trademarks of Advanced Micro Devices, Inc. Other product names are for informational purposes only and may be trademarks of their respective companies. North America CALIFORNIA, FLORIDA, ILLINOIS, NEW JERSEY, TEXAS, International CHINA, GERMANY, JAPAN, UNITED KINGDOM, Representatives in U.S. and Canada ARIZONA, CALIFORNIA, CANADA, COLORADO, FLORIDA, GEORGIA, ILLINOIS, INDIANA, IOWA, KANSAS, MASSACHUSETTS, MICHIGAN, MINNESOTA, MISSOURI, NEW JERSEY, NEW YORK, NORTH CAROLINA, OHIO, OREGON, UTAH, VIRGINIA, WASHINGTON, WISCONSIN, Representatives in Latin America ARGENTINA, CHILE, COLUMBIA, MEXICO, PUERTO RICO, Sales Offices and Representatives es