AM42DL1632DB45IS

AM42DL16X2D AMD | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am42DL16x2D Data Sheet Publication Number 25561 Revision A Amendment +2 Issue Date February 6, 2004

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 25561 Rev: A Amendment/+2 Issue Date: February 6, 2004 Refer to AMD’s Website (www.amd.com) for the latest information. Am42DL16x2D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance Access time as fast as 70 ns Package 69-Ball FBGA Operating Temperature –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations Data can be continuously read from one bank while executing erase/program functions in other bank Zero latency between read and write operations Secured Silicon (SecSi) Sector: Extra 64 KByte sector Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed Zero Power Operation Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero Top or bottom boot block Manufactured on 0.23 µm process technology Compatible with JEDEC standards Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance 70 ns access time Program time: 4 µs/word typical utilizing Accelerate function Ultra low power consumption (typical values) 2 mA active read current at 1 MHz 10 mA active read current at 5 MHz 200 nA in standby or automatic sleep mode Minimum 1 million write cycles guaranteed per sector

20 Year data retention at 125°C

Reliable operation for the life of the system SOFTWARE FEATURES Data Management Software (DMS) AMD-supplied software manages data programming and erasing, enabling EEPROM emulation Eases sector erase limitations Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume Suspends erase operations to allow programming in same bank Data# Polling and Toggle Bits Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) Hardware method of resetting the internal state machine to reading array data WP#/ACC input pin Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status Acceleration (ACC) function accelerates program timing Sector protection Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector Temporary Sector Unprotect allows changing data in protected sectors in-system SRAM Features Power dissipation Operating: 20 mA maximum Standby: 10 µA maximum CE1#s and CE2s Chip Select Power down features using CE1#s and CE2s Data retention supply voltage: 1.5 to 3.3 volt Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)

February 6, 2004 GENERAL DESCRIPTION Am29DL16xD Features The Am29DL16xD family is a 16 megabit, 3.0 volt-only flash memory device, organized as 1,048,576 words of 16 bits or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data ap- pears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with access times of 70 ns or 85 ns. The device is offered in a 69-ball FBGA pack- age. Standard control pins—chip enable (CE#f), write enable (WE#), and output enable (OE#)—control nor- mal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. The Am29DL16xD devices uses multiple bank archi- tectures to provide flexibility for different applications. Four devices are available with the following bank sizes: The Secured Silicon (SecSi) Sector is an extra 64 Kbit sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number). Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Device Bank 1 Bank 2 DL161 0.5 Mb 15.5 Mb DL162 2 Mb 14 Mb DL163 4 Mb 12 Mb DL164 8 Mb 8 Mb

February 6, 2004 Am42DL16x2D PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am42DL16x2D Speed Options Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM Max Access Time (ns) CE# Access (ns) OE# Access (ns) VSS/VSSQ VCCs/VCCQ RESET# WE# CE#f OE# CE1#s VSS VCCf RY/BY# LB#s UB#s CIOf WP#/ACC CE2s

2 Mbit

16 Mbit

DQ15 to DQ0/A–1 DQ15 to DQ0/A–1 DQ0 to DQ15/A–1 A19 to A0 A0 to A19 A0 to A19 A–1 A16 to A0

February 6, 2004 FLASH MEMORY BLOCK DIAGRAM VCC VSS Upper Bank Address A0–A20 RESET# WE# CE# BYTE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ0–DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address Status Control A0–A20 A0–A20 A0–A20 A0–A20 DQ0–DQ15 DQ0–DQ15 Mux Mux Mux

February 6, 2004 Am42DL16x2D CONNECTION DIAGRAM Special Handling Instructions for FBGA Package Special handling is required for Flash Memory prod- ucts in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. NC NC NC NC NC DQ8 DQ14 CE1#s LB#s WP#/ACC WE# A11 UB#s RESET# CE2s A19 A12 A15 A18 RY/BY# NC A13 NC A17 A10 A14 NC E10 VSS DQ1 DQ6 NC A16 F10 CE#f DQ0 OE# DQ9 DQ3 DQ4 DQ13 DQ15/A-1 CIOf DQ10 VCCf VCCs DQ12 DQ7 VSS DQ2 DQ11 NC DQ5 NC NC NC NC A10 NC NC NC NC K10 SRAM only Shared Flash only 69-Ball FBGA Top View

February 6, 2004 PIN DESCRIPTION A0–A16 = 17 Address Inputs (Common) A–1, A19–A17 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL DQ15–DQ0 A16–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC A–1, A19–A17 LB#s CIOf CE1#s CE2s

February 6, 2004 Am42DL16x2D

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Am42DL16x D T I T TAPE AND REEL T 7 inches S 13 inches TEMPERATURE RANGE I Industrial (–40°C to +85°C) FLASH SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T Top Sector B Bottom Sector FLASH PROCESS TECHNOLOGY D 0.23 µm, CS49S SRAM DEVICE DENSITY

2 Mbits

AMD DEVICE NUMBER/DESCRIPTION Am42DL16x2D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM Valid Combinations Order Number Package Marking Am42DL1612DT70I Am42DL1612DB70I T, S M42000000I M42000000J Am42DL1612DT85I Am42DL1612DB85I M42000000K M42000000L Am42DL1622DT70I Am42DL1622DB70I M42000000M M42000000N Am42DL1622DT85I Am42DL1622DB85I M42000000O M42000000P Am42DL1632DT70I Am42DL1632DB70I M42000000Q M42000000R Am42DL1632DT85I Am42DL1632DB85I M42000000S M42000000T Am42DL1642DT70I Am42DL1642DB70I M420000004 M420000005 Am42DL1642DT85I Am42DL1642DB85I M420000006 M420000007

February 6, 2004 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. The following subsections describe each of these operations in further detail.

February 6, 2004 Am42DL16x2D Table 1. Device Bus Operations—Flash Word Mode (CIOf = VIH), SRAM Word Mode (CIOs = VCC) Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# Addr. LB#s UB#s RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ0 Read from Flash L H X L H AIN X X H L/H DOUT DOUT X L Write to Flash L H X H L AIN X X H (Note 4) DIN DIN X L Standby VCC ± 0.3 V H X X X X X X VCC ± 0.3 V H High-Z High-Z X L Output Disable L L H H H X L X H L/H High-Z High-Z X L Flash Hardware Reset X H X X X X X X L L/H High-Z High-Z X L H X Sector Protect (Note 5) L X L H L SA, A6 = L, A1 = H, A0 = L X X VID L/H DIN X H X Sector Unprotect (Note 5) L X L H L SA, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X Temporary Sector Unprotect X H X X X AIN X X VID (Note 6) DIN High-Z X L Read from SRAM H L H L H AIN L L H X DOUT DOUT H L High-Z DOUT L H DOUT High-Z Write to SRAM H L H X L AIN L L H X DIN DIN H L High-Z DIN L H DIN High-Z

February 6, 2004 Table 2. Device Bus Operations—Flash Byte Mode (CIOf = VSS), SRAM Word Mode (CIOs = VCC) Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# Addr. LB#s (Note 3) UB#s (Note 3) RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ0 Read from Flash L H X L H AIN X X H L/H DOUT High-Z X L Write to Flash L H X H L AIN X X H (Note 3) DIN High-Z X L Standby VCC ± 0.3 V H X X X X X X VCC ± 0.3 V H High-Z High-Z X L Output Disable L L H H H X L X H L/H High-Z High-Z H X X X L Flash Hardware Reset X H X X X X X X L L/H High-Z High-Z X L Sector Protect (Note 5) L H X H L SA, A6 = L, A1 = H, A0 = L X X VID L/H DIN X X L Sector Unprotect (Note 5) L H X H L SA, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X X L Temporary Sector Unprotect X H X X X AIN X X VID (Note 6) DIN High-Z X L Read from SRAM H L H L H AIN L L H X DOUT DOUT H L High-Z DOUT L H DOUT High-Z Write to SRAM H L H X L AIN L L H X DIN DIN H L High-Z DIN L H DIN High-Z

February 6, 2004 Am42DL16x2D Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ0–DQ15 are active and controlled by CE# and OE#. If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to VIL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at VIH. The CIOf pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Flash Read-Only Opera- tions table for timing specifications and to Figure 14 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to VIL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 4–5 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively.

February 6, 2004 Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE#f and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de- vice requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard ad- dress access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ± 0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo- rithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 3. Device Bank Division Device Part Number Bank 1 Bank 2 Megabits Sector Sizes Megabits Sector Sizes Am29DL161D

0.5 Mbit

15.5 Mbit

64 Kbyte/32 Kword

Eight 8 Kbyte/4 Kword, three 64 Kbyte/32 Kword

14 Mbit

4 Mbit

Eight 8 Kbyte/4 Kword, seven 64 Kbyte/32 Kword

12 Mbit

8 Mbit

Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword

February 6, 2004 Am42DL16x2D Table 4. Sector Addresses for Top Boot Sector Devices Note: The address range is A19:A-1 in byte mode (CIOf=VIL) or A19:A0 in word mode (CIOf=VIH). The bank address bits are A19–A15 for Am29DL161DT, A19–A17 for Am29DL162DT, A19 and A18 for Am29DL163DT, and A19 for Am29DL164DT Table 5. SecSi Sector Addresses for Top Boot Devices Am29DL164DT Am29DL163DT Am29DL162DT Am29DL161DT Sector Sector Address A19–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Bank 2 Bank 2 Bank 2 Bank 2 SA0 00000xxx 000000h-00FFFFh 00000h–07FFFh SA1 00001xxx 010000h-01FFFFh 08000h–0FFFFh SA2 00010xxx 020000h-02FFFFh 10000h–17FFFh SA3 00011xxx 030000h-03FFFFh 18000h–1FFFFh SA4 00100xxx 040000h-04FFFFh 20000h–27FFFh SA5 00101xxx 050000h-05FFFFh 28000h–2FFFFh SA6 00110xxx 060000h-06FFFFh 30000h–37FFFh SA7 00111xxx 070000h-07FFFFh 38000h–3FFFFh SA8 01000xxx 080000h-08FFFFh 40000h–47FFFh SA9 01001xxx 090000h-09FFFFh 48000h–4FFFFh SA10 01010xxx 0A0000h-0AFFFFh 50000h–57FFFh SA11 01011xxx 0B0000h-0BFFFFh 58000h–5FFFFh SA12 01100xxx 0C0000h-0CFFFFh 60000h–67FFFh SA13 01101xxx 0D0000h-0DFFFFh 68000h–6FFFFh SA14 01110xxx 0E0000h-0EFFFFh 70000h–77FFFh SA15 01111xxx 0F0000h-0FFFFFh 78000h–7FFFFh Bank 1 SA16 10000xxx 100000h-10FFFFh 80000h–87FFFh SA17 10001xxx 110000h-11FFFFh 88000h–8FFFFh SA18 10010xxx 120000h-12FFFFh 90000h–97FFFh SA19 10011xxx 130000h-13FFFFh 98000h–9FFFFh SA20 10100xxx 140000h-14FFFFh A0000h–A7FFFh SA21 10101xxx 150000h-15FFFFh A8000h–AFFFFh SA22 10110xxx 160000h-16FFFFh B0000h–B7FFFh SA23 10111xxx 170000h-17FFFFh B8000h–BFFFFh Bank 1 SA24 11000xxx 180000h-18FFFFh C0000h–C7FFFh SA25 11001xxx 190000h-19FFFFh C8000h–CFFFFh SA26 11010xxx 1A0000h-1AFFFFh D0000h–D7FFFh SA27 11011xxx 1B0000h-1BFFFFh D8000h–DFFFFh Bank 1 SA28 11100xxx 1C0000h-1CFFFFh E0000h–E7FFFh SA29 11101xxx 1D0000h-1DFFFFh E8000h–EFFFFh SA30 11110xxx 1E0000h-1EFFFFh F0000h–F7FFFh Bank 1 SA31 11111000 1F0000h-1F1FFFh F8000h–F8FFFh SA32 11111001 1F2000h-1F3FFFh F9000h–F9FFFh SA33 11111010 1F4000h-1F5FFFh FA000h–FAFFFh SA34 11111011 1F6000h-1F7FFFh FB000h–FBFFFh SA35 11111100 1F8000h-1F9FFFh FC000h–FCFFFh SA36 11111101 1FA000h-1FBFFFh FD000h–FDFFFh SA37 11111110 1FC000h-1FDFFFh FE000h–FEFFFh SA38 11111111 1FE000h-1FFFFFh FF000h–FFFFFh Device Sector Address A19–A12 Sector Size (x8) Address Range (x16) Address Range Am29DL16xDT 11111XXX 1F0000h-1FFFFFh F8000h–FFFFFh

February 6, 2004 Table 6. Sector Addresses for Bottom Boot Sector Devices Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19–A15 for Am29DL161DB, A19–A17 for Am29DL162DB, A19 and A18 for Am29DL163DB, and A19 for Am29DL164DB. Table 7. SecSi™ Addresses for Bottom Boot Devices Am29DL164DB Am29DL163DB Am29DL162DB Am29DL161DB Sector Sector Address A19–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Bank 1 Bank 1 Bank 1 Bank 1 SA0 00000000 000000h-001FFFh 00000h-00FFFh SA1 00000001 002000h-003FFFh 01000h-01FFFh SA2 00000010 004000h-005FFFh 02000h-02FFFh SA3 00000011 006000h-007FFFh 03000h-03FFFh SA4 00000100 008000h-009FFFh 04000h-04FFFh SA5 00000101 00A000h-00BFFFh 05000h-05FFFh SA6 00000110 00C000h-00DFFFh 06000h-06FFFh SA7 00000111 00E000h-00FFFFh 07000h-07FFFh Bank 2 SA8 00001XXX 010000h-01FFFFh 08000h-0FFFFh SA9 00010XXX 020000h-02FFFFh 10000h-17FFFh SA10 00011XXX 030000h-03FFFFh 18000h-1FFFFh Bank 2 SA11 00100XXX 040000h-04FFFFh 20000h-27FFFh SA12 00101XXX 050000h-05FFFFh 28000h-2FFFFh SA13 00110XXX 060000h-06FFFFh 30000h-37FFFh SA14 00111XXX 070000h-07FFFFh 38000h-3FFFFh Bank 2 SA15 01000XXX 080000h-08FFFFh 40000h-47FFFh SA16 01001XXX 090000h-09FFFFh 48000h-4FFFFh SA17 01010XXX 0A0000h-0AFFFFh 50000h-57FFFh SA18 01011XXX 0B0000h-0BFFFFh 58000h-5FFFFh SA19 01100XXX 0C0000h-0CFFFFh 60000h-67FFFh SA20 01101XXX 0D0000h-0DFFFFh 68000h-6FFFFh SA21 01110XXX 0E0000h-0EFFFFh 70000h-77FFFh SA22 01111XXX 0F0000h-0FFFFFh 78000h-7FFFFh Bank 2 SA23 10000XXX 100000h-10FFFFh 80000h-87FFFh SA24 10001XXX 110000h-11FFFFh 88000h-8FFFFh SA25 10010XXX 120000h-12FFFFh 90000h-97FFFh SA26 10011XXX 130000h-13FFFFh 98000h-9FFFFh SA27 10100XXX 140000h-14FFFFh A0000h-A7FFFh SA28 10101XXX 150000h-15FFFFh A8000h-AFFFFh SA29 10110XXX 160000h-16FFFFh B0000h-B7FFFh SA30 10111XXX 170000h-17FFFFh B8000h-BFFFFh SA31 11000XXX 180000h-18FFFFh C0000h-C7FFFh SA32 11001XXX 190000h-19FFFFh C8000h-CFFFFh SA33 11010XXX 1A0000h-1AFFFFh D0000h-D7FFFh SA34 11011XXX 1B0000h-1BFFFFh D8000h-DFFFFh SA35 11100XXX 1C0000h-1CFFFFh E0000h-E7FFFh SA36 11101XXX 1D0000h-1DFFFFh E8000h-EFFFFh SA37 11110XXX 1E0000h-1EFFFFh F0000h-F7FFFh SA38 11111XXX 1F0000h-1FFFFFh F8000h-FFFFFh Device Sector Address A19–A12 Sector Size (x8) Address Range (x16) Address Range Am29DL16xDB 00000XXX 000000h-00FFFFh 00000h-07FFFh

February 6, 2004 Am42DL16x2D Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended to automatically match a device to be programmed with its corresponding pro- gramming algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 14. This method does not require VID. Refer to the Autoselect Com- mand Sequence section for more information. Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9). Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection and unprotection can be im- plemented as follows. Sector protection/unprotection requires VID on the RE- SET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 26 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previ- ously protected sectors must be individually re-protected. To change data in protected sectors effi- Sector / Sector Block A19–A12 Sector / Sector Block Size SA0 00000XXX

64 Kbytes

00001XXX, 00010XXX, 00011XXX 192 (3x64) Kbytes SA4-SA7 001XXXXX 256 (4x64) Kbytes SA8-SA11 010XXXXX 256 (4x64) Kbytes SA12-SA15 011XXXXX 256 (4x64) Kbytes SA16-SA19 100XXXXX 256 (4x64) Kbytes SA20-SA23 101XXXXX 256 (4x64) Kbytes SA24-SA27 110XXXXX 256 (4x64) Kbytes SA28-SA30 11100XXX, 11101XXX, 11110XXX 192 (3x64) Kbytes SA31 11111000

8 Kbytes

A19–A12 Sector / Sector Block Size SA38 11111XXX 11110XXX, 11101XXX, 11100XXX 192 (3x64) Kbytes SA34-SA31 110XXXXX 256 (4x64) Kbytes SA30-SA27 101XXXXX 256 (4x64) Kbytes SA26-SA23 100XXXXX 256 (4x64) Kbytes SA22-SA19 011XXXXX 256 (4x64) Kbytes SA18-SA15 010XXXXX 256 (4x64) Kbytes SA14-SA11 001XXXXX 256 (4x64) Kbytes SA10-SA8 00001XXX, 00010XXX, 00011XXX 192 (3x64) Kbytes SA7 00000111 A19–A12 Sector / Sector Block Size

February 6, 2004 The device is shipped with all sectors unprotected. It is possible to determine whether a sector is pro- tected or unprotected. See the Autoselect Mode section for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the de- vice disables program and erase functions in the two “outermost” 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a top-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the de- vice reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sec- tor/Sector Block Protection and Unprotection”. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9). This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin to VID (8.5 V – 12.5 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously pro- tected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timing diagrams, for this feature. START Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) RESET# = VID (Note 1) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation

February 6, 2004 Am42DL16x2D Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Set up sector address Wait 150 µs Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs First Write Cycle = 60h? Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Yes Yes No PLSCNT = 25? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Set up first sector address Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Read from sector address with A6 = 1, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs Data = 00h? Last sector verified? Remove VID from RESET# Write reset command Sector Unprotect complete Yes No PLSCNT = 1000? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No All sectors protected? Yes Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Set up next sector address No Yes No Yes No No Yes No Sector Protect Algorithm Sector Unprotect Algorithm First Write Cycle = 60h? Protect another sector? Reset PLSCNT = 1

February 6, 2004 SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 Kbytes in length, and uses a SecSi Sector Indicator Bit to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. Current version of this device has 64 Kbytes; future ver- sions will have only 256 bytes. This should be considered during system design. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the unprotected, allowing cus- tomers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with a random, se- cure ESN only In devices that have an ESN, the Top Boot device will have the 16-byte ESN, with the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses F8000h–F8007h in word mode (or 1F0000h–1F000Fh in byte mode). Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. Current version of this device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. The SecSi Sector can be read, programmed, and erased as often as required. Note that the accelerated program- ming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either VIH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection”. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subse- quent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

February 6, 2004 Am42DL16x2D Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle, CE#f and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to reading array data on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The sys- tem can read CFI information at the addresses given in Tables 10–13. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10–13. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/over- view/cfi.html. Alternatively, contact an AMD representative for copies of these documents. Table 10. CFI Query Identification String Addresses (Word Mode) Data

Description

Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists)

February 6, 2004 Table 11. System Interface String Table 12. Device Geometry Definition Addresses (Word Mode) Data VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0004h Typical timeout per single byte/word write 2N µs 20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0005h Max. timeout for byte/word write 2N times typical 24h 0000h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Addresses (Word Mode) Data Device Size = 2N byte 28h 29h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0002h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 003Eh 0000h 0000h 0001h Erase Block Region 2 Information 35h 36h 37h 38h 0000h 0000h 0000h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information

February 6, 2004 Am42DL16x2D Table 13. Primary Vendor-Specific Extended Query Note: The number of sectors in Bank 2 is device dependent. Am29DL161 = 1Fh Am29DL162 = 1Ch Am29DL163 = 18h Am29DL164 = 10h Addresses (Word Mode) Data Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII 45h 0001h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme 04 = 29LV800 mode 4Ah 00XXh (See Note) Simultaneous Operation 00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank) 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 000Xh Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device

February 6, 2004 COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Table 14 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 14 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: ■A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. ■A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. ■A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 4–5 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend).

February 6, 2004 Am42DL16x2D Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to nor- mal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm. Table 14 shows the ad- dress and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Note that a hardware reset (RESET#=VIL) will reset the de- vice to reading array data. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the CIOf pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cy- cles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. Table 14 shows the address and data requirements for the byteword program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 14 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The bank then returns to the reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Flash Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

February 6, 2004 Table 14. Command Definitions Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Notes: See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. Unless otherwise noted, address bits A19–A11 are don’t cares. No unlock or command cycles required when bank is in read mode. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information. The data is 80h for factory locked and 00h for not factory locked. 10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. Table 15. Autoselect Device ID Codes T = Top Boot Sector, B = Bottom Boot Sector Command Sequence (Note 1) Cycles Bus Cycles (Notes 2–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 6) RA RD Reset (Note 7) XXX Autoselect (Note 8) Manufacturer ID Word 555 AA 2AA (BA)555 (BA)X00 Device ID Word 555 AA 2AA (BA)555 (BA)X01 see Table SecSi Sector Factory Protect (Note 9) Word 555 AA 2AA (BA)555 (BA)X03 Sector Protect Verify (Note 10) Word 555 AA 2AA (BA)555 (SA)X02 Enter SecSi Sector Region Word 555 AA 2AA 555 Exit SecSi Sector Region Word 555 AA 2AA 555 XXX Program Word 555 AA 2AA 555 PA PD Unlock Bypass Word 555 AA 2AA 555 Unlock Bypass Program (Note 11) XXX PA PD Unlock Bypass Reset (Note 12) XXX XXX Chip Erase Word 555 AA 2AA 555 555 AA 2AA 555 Sector Erase Word 555 AA 2AA 555 555 AA 2AA SA Erase Suspend (Note 13) BA Erase Resume (Note 14) BA CFI Query (Note 15) Word Device Autoselect Device ID Am29DL161D 36h (T), 39h (B) Am29DL162D 2Dh (T), 2Eh (B) Am29DL163D 28h (T), 2Bh (B) Am29DL164D 33h (T), 35h (B)

February 6, 2004 Table 16. Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle N/A No toggle Embedded Erase Algorithm Toggle Toggle Erase Suspend Mode Erase-Suspend- Read Erase Suspended Sector No toggle N/A Toggle Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle N/A N/A

February 6, 2004 DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current VCC = VCC max; RESET# = 12.5 V µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current VCC = VCC max, WP#/ACC = VACC max µA ICC1f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Word Mode

5 MHz

1 MHz

Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL mA ICC3f Flash VCC Standby Current (Note 2) VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCCf ± 0.3 V 0.2 µA ICC4f Flash VCC Reset Current (Note 2) VCCf = VCC max, RESET# = VSS ± 0.3 V, WP#/ACC = VCCf ± 0.3 V 0.2 µA ICC5f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCCf = VCC max, VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 µA ICC6f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = VIL, OE# = VIH mA ICC7f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH mA ICC8f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = VIL, OE#f = VIH mA IACC ACC Accelerated Program Current CE#f = VIL, OE# = VIH ACC pin mA VCC pin mA ICC4s SRAM VCC Standby Current CE1#s ≥ VCCs – 0.2V, CE2s ≥ VCCs – 0.2V µA ICC5s SRAM VCC Standby Current CE2s ≤ 0.2V µA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 VCC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 8.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCCf = VCCs = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCCf = VCCs = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4

February 6, 2004 Am42DL16x2D Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC1s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V mA ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH mA VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = –1.0 mA 2.4 V ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –

0.2 V (CE1#s controlled) or 0 V ≤

CE2 ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC, Other input = 0 ~ VCC µA DC CHARACTERISTICS (Continued) CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit

February 6, 2004 Am42DL16x2D TEST CONDITIONS Table 17. Test Specifications KEY TO SWITCHING WAVEFORMS 2.7 kΩ CL 6.2 kΩ 3.3 V Device Under Test Note: Diodes are IN3064 or equivalent Figure 11. Test Setup Test Condition 70, 85 ns Unit Output Load

1 TTL gate

Output Load Capacitance, CL (including jig capacitance) pF Input Rise and Fall Times ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V KS000010-PAL WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 3.0 V 0.0 V 1.5 V 1.5 V Output Measurement Level Input Figure 12. Input Waveforms and Measurement Levels

February 6, 2004 AC CHARACTERISTICS SRAM CE#s Timing Figure 13. Timing Diagram for Alternating Between SRAM to Flash Parameter CE#s Recover Time Min ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS Flash Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 17 for test specifications. Parameter Read Cycle Time (Note 1) Min ns tAVQV tACC Address to Output Delay CE#f, OE# = VIL Max ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max ns tGLQV tOE Output Enable to Output Delay Max ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max ns tAXQX tOH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min ns tOEH Output Enable Hold Time (Note 1) Read Min ns Toggle and Data# Polling Min ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF Figure 14. Read Operation Timings

February 6, 2004 AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min ns tRPD RESET# Low to Standby Mode Min µs tRB RY/BY# Recovery Time Min ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#f, OE# tRH CE#f, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB Figure 15. Reset Timings

February 6, 2004 AC CHARACTERISTICS Flash Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options Unit JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time (WE# to Address) Min ns tASO Address Setup Time to OE# or CE#f low during toggle bit polling Min ns tWLAX tAH Address Hold Time (WE# to Address) Min ns tAHT Address Hold Time From CE#f or OE# high during toggle bit polling Min ns tDVWH tDS Data Setup Time Min ns tWHDX tDH Data Hold Time Min ns tOEH OE# Hold Time Read Min ns Toggle and Data# Polling Min ns tOEPH Output Enable High during toggle bit polling Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) Min ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min ns tELWL tCS CE#f Setup Time (WE# to CE#f) Min ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min ns tWHEH tCH CE#f Hold Time (CE#f to WE#) Min ns tWLWH tWP Write Pulse Width Min ns tELEH tCP CE#f Pulse Width Min ns tWHDL tWPH Write Pulse Width High Min ns tSR/W Latency Between Read and Write Operations Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCCf Setup Time (Note 1) Min µs tRB Write Recovery Time from RY/BY# Min ns tBUSY Program/Erase Valid to RY/BY# Delay Max ns

February 6, 2004 AC CHARACTERISTICS OE# CE#f Addresses VCCf WE# Data 2AAh SADD tGHWL tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH In Progress Complete tWHWH2 VA VA Erase Command Sequence (last two cycles) Read Status Data RY/BY# tRB tBUSY Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). 2. These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Note: Not 100% tested. Parameter All Speed Options Unit JEDEC Std VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector/Sector Block Unprotect Min µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector/Sector Block Unprotect Min µs RESET# tVIDR VID VSS, VIL, or VIH VID VSS, VIL, or VIH CE#f WE# RY/BY# tVIDR tRSP Program or Erase Command Sequence tRRB Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram

February 6, 2004 AC CHARACTERISTICS Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms 1 µs RESET# SADD, A6, A1, A0 Data CE#f WE# OE# 60h 60h 40h Valid* Valid* Valid* Status Sector/Sector Block Protect or Unprotect Verify VID VIH * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. SA = Sector Address Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time (WE# to Address) Min ns tASO Address Setup Time to CE#f Low During Toggle Bit Polling Min ns tELAX tAH Address Hold Time Min ns tAHT Address Hold time from CE#f or OE# High During Toggle Bit Polling Min ns tDVEH tDS Data Setup Time Min ns tEHDX tDH Data Hold Time Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time Min ns tEHWH tWH WE# Hold Time Min ns tELEH tCP CE#f Pulse Width Min ns tEHEL tCPH CE#f Pulse Width High Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

February 6, 2004 AC CHARACTERISTICS tGHEL tWS OE# CE#f WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# DOUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase tBUSY Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS SRAM Read Cycle Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 28. SRAM Read Cycle—Address Controlled Parameter Symbol tCO1, tCO2 Chip Enable to Output Max ns tOE Output Enable Access Time Max ns tBA LB#s, UB#s to Valid Output Max ns tLZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output Min ns tBLZ UB#, LB# Enable to Low-Z Output Min ns tOLZ Output Enable to Low-Z Output Min ns tHZ1, tHZ2 Chip disable to High-Z Output Min ns Max tBHZ UB#s, LB#s Disable to High-Z Output Min ns Max tOHZ Output Disable to High-Z Output Min ns Max tOH Output Data Hold from Address Change Min ns Address Data Out Previous Data Valid Data Valid tAA tRC tOH

February 6, 2004 AC CHARACTERISTICS Figure 29. SRAM Read Cycle Notes: 1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing. 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. Data Valid High-Z tRC CE#1s Address OE# Data Out tOH tAA tCO1 tOE tOLZ tBLZ tLZ tOHZ tHZ CE2s tCO2

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS SRAM Write Cycle Notes: 1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing. 1. tCW is measured from CE1#s going low to the end of write. 2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 3. tAS is measured from the address valid to the beginning of write. 4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 30. SRAM Write Cycle—WE# Control Parameter Symbol Chip Enable to End of Write Min ns tAS Address Setup Time Min ns tAW Address Valid to End of Write Min ns tBW UB#s, LB#s to End of Write Min ns tWP Write Pulse Time Min ns tWR Write Recovery Time Min ns tWHZ Write to Output High-Z Min ns Max tDW Data to Write Time Overlap Min ns tDH Data Hold from Write Time Min ns tOW End Write to Output Low-Z Min ns Address CE1#s Data Undefined UB#s, LB#s WE# Data In Data Out tWC tCW (See Note 2) tAW High-Z High-Z Data Valid CE2s tCW (See Note 2) tBW tWP (See Note 5) tAS (See Note 4) tWR (See Note 3) tWHZ tDW tDH tOW

February 6, 2004 AC CHARACTERISTICS Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing. 1. tCW is measured from CE1#s going low to the end of write. 2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 3. tAS is measured from the address valid to the beginning of write. 4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 31. SRAM Write Cycle—CE1#s Control Address Data Valid UB#s, LB#s WE# Data In Data Out High-Z High-Z tWC CE1#s CE2s tAW tAS (See Note 2 ) tBW tCW (See Note 3) tWR (See Note 4) tWP (See Note 5) tDW tDH

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS Notes: 1. UB#s and LB#s controlled, CIOs must be high. 1. tCW is measured from CE1#s going low to the end of write. 2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 3. tAS is measured from the address valid to the beginning of write. 4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 32. SRAM Write Cycle—UB#s and LB#s Control Address Data Valid UB#s, LB#s WE# Data In Data Out High-Z High-Z tWC CE1#s CE2s tAW tBW tDW tDH tWR (See Note 3) tAS (See Note 4) tCW (See Note 2) tCW (See Note 2) tWP (See Note 5)

February 6, 2004 FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most byteswords program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytewords are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. FLASH LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Note: 7.Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time sec Byte Program Time 150 µs Word Program Time 210 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 120 µs Byte Mode Chip Program Time (Note 3) Word Mode sec Input voltage with respect to VSS on all pins except I/O pins (including OE# and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol VIN = 0 pF COUT Output Capacitance VOUT = 0 pF CIN2 Control Pin Capacitance VIN = 0 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C Years 125°C Years

February 6, 2004 PHYSICAL DIMENSIONS FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm

8.00 BSC

1.40 (max) 0.20 (min) A B C D E F G H J K 0.80

7.20 BSC

0.80 (69x) Pin A1 Corner Index Mark

11.00 BSC

0.08 0.15 M B M C C A 0.40 DATUM A DATUM B B A 0.08 0.97 1.07 C 0.20 C 0.15 C (2x) 0.15 C (2x) C 0.40 0.25 0.35

February 6, 2004 Am42DL16x2D REVISION SUMMARY Revision A (October 24, 2001) Initial release. Revision A+1 (March 4, 2002) Changed package marking for Am42DL1642D (4 part numbers). Figure 30, SRAM Write Cycle—WE# Control In Data Out waveform, corrected tBW to tWHZ. Revision A+2 (February 6, 2004) Command Definitions The result of writing incorrect address and data values changed to reflect that doing so places the device in an unknown state. Unlock Bypass Command Sequence Deleted statements regarding what the first and sec- ond cycles must contain to exit the unlock bypass mode. Table 14. Command Definitions Reset command sequence changed from BA to XXX.

February 6, 2004 Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

February 6, 2004 Am42DL16x2D

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 25561 Rev: A Amendment/+2 Issue Date: February 6, 2004 Refer to AMD’s Website (www.amd.com) for the latest information. Am42DL16x2D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance Access time as fast as 70 ns Package 69-Ball FBGA Operating Temperature –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations Data can be continuously read from one bank while executing erase/program functions in other bank Zero latency between read and write operations Secured Silicon (SecSi) Sector: Extra 64 KByte sector Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed Zero Power Operation Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero Top or bottom boot block Manufactured on 0.23 µm process technology Compatible with JEDEC standards Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance 70 ns access time Program time: 4 µs/word typical utilizing Accelerate function Ultra low power consumption (typical values) 2 mA active read current at 1 MHz 10 mA active read current at 5 MHz 200 nA in standby or automatic sleep mode Minimum 1 million write cycles guaranteed per sector Reliable operation for the life of the system SOFTWARE FEATURES Data Management Software (DMS) AMD-supplied software manages data programming and erasing, enabling EEPROM emulation Eases sector erase limitations Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume Suspends erase operations to allow programming in same bank Data# Polling and Toggle Bits Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) Hardware method of resetting the internal state machine to reading array data WP#/ACC input pin Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status Acceleration (ACC) function accelerates program timing Sector protection Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector Temporary Sector Unprotect allows changing data in protected sectors in-system SRAM Features Power dissipation Operating: 20 mA maximum Standby: 10 µA maximum CE1#s and CE2s Chip Select Power down features using CE1#s and CE2s Data retention supply voltage: 1.5 to 3.3 volt Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)

February 6, 2004 GENERAL DESCRIPTION Am29DL16xD Features The Am29DL16xD family is a 16 megabit, 3.0 volt-only flash memory device, organized as 1,048,576 words of 16 bits or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data ap- pears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with access times of 70 ns or 85 ns. The device is offered in a 69-ball FBGA pack- age. Standard control pins—chip enable (CE#f), write enable (WE#), and output enable (OE#)—control nor- mal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. The Am29DL16xD devices uses multiple bank archi- tectures to provide flexibility for different applications. Four devices are available with the following bank sizes: The Secured Silicon (SecSi) Sector is an extra 64 Kbit sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number). Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Device Bank 1 Bank 2 DL161 0.5 Mb 15.5 Mb DL162 2 Mb 14 Mb DL163 4 Mb 12 Mb DL164 8 Mb 8 Mb

February 6, 2004 Am42DL16x2D PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am42DL16x2D Speed Options Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM Max Access Time (ns) CE# Access (ns) OE# Access (ns) VSS/VSSQ VCCs/VCCQ RESET# WE# CE#f OE# CE1#s VSS VCCf RY/BY# LB#s UB#s CIOf WP#/ACC CE2s DQ15 to DQ0/A–1 DQ15 to DQ0/A–1 DQ0 to DQ15/A–1 A19 to A0 A0 to A19 A0 to A19 A–1 A16 to A0

February 6, 2004 FLASH MEMORY BLOCK DIAGRAM VCC VSS Upper Bank Address A0–A20 RESET# WE# CE# BYTE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ0–DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address Status Control A0–A20 A0–A20 A0–A20 A0–A20 DQ0–DQ15 DQ0–DQ15 Mux Mux Mux

February 6, 2004 Am42DL16x2D CONNECTION DIAGRAM Special Handling Instructions for FBGA Package Special handling is required for Flash Memory prod- ucts in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. NC NC NC NC NC DQ8 DQ14 CE1#s LB#s WP#/ACC WE# A11 UB#s RESET# CE2s A19 A12 A15 A18 RY/BY# NC A13 NC A17 A10 A14 NC E10 VSS DQ1 DQ6 NC A16 F10 CE#f DQ0 OE# DQ9 DQ3 DQ4 DQ13 DQ15/A-1 CIOf DQ10 VCCf VCCs DQ12 DQ7 VSS DQ2 DQ11 NC DQ5 NC NC NC NC A10 NC NC NC NC K10 SRAM only Shared Flash only 69-Ball FBGA Top View

February 6, 2004 PIN DESCRIPTION A0–A16 = 17 Address Inputs (Common) A–1, A19–A17 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL DQ15–DQ0 A16–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC A–1, A19–A17 LB#s CIOf CE1#s CE2s

February 6, 2004 Am42DL16x2D The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Am42DL16x D T I T TAPE AND REEL T 7 inches S 13 inches TEMPERATURE RANGE I Industrial (–40°C to +85°C) FLASH SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T Top Sector B Bottom Sector FLASH PROCESS TECHNOLOGY D 0.23 µm, CS49S SRAM DEVICE DENSITY AMD DEVICE NUMBER/DESCRIPTION Am42DL16x2D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM Valid Combinations Order Number Package Marking Am42DL1612DT70I Am42DL1612DB70I T, S M42000000I M42000000J Am42DL1612DT85I Am42DL1612DB85I M42000000K M42000000L Am42DL1622DT70I Am42DL1622DB70I M42000000M M42000000N Am42DL1622DT85I Am42DL1622DB85I M42000000O M42000000P Am42DL1632DT70I Am42DL1632DB70I M42000000Q M42000000R Am42DL1632DT85I Am42DL1632DB85I M42000000S M42000000T Am42DL1642DT70I Am42DL1642DB70I M420000004 M420000005 Am42DL1642DT85I Am42DL1642DB85I M420000006 M420000007

February 6, 2004 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. The following subsections describe each of these operations in further detail.

February 6, 2004 Am42DL16x2D Table 1. Device Bus Operations—Flash Word Mode (CIOf = VIH), SRAM Word Mode (CIOs = VCC) Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# Addr. LB#s UB#s RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ0 Read from Flash L H X L H AIN X X H L/H DOUT DOUT X L Write to Flash L H X H L AIN X X H (Note 4) DIN DIN X L Standby VCC ± 0.3 V H X X X X X X VCC ± 0.3 V H High-Z High-Z X L Output Disable L L H H H X L X H L/H High-Z High-Z X L Flash Hardware Reset X H X X X X X X L L/H High-Z High-Z X L H X Sector Protect (Note 5) L X L H L SA, A6 = L, A1 = H, A0 = L X X VID L/H DIN X H X Sector Unprotect (Note 5) L X L H L SA, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X Temporary Sector Unprotect X H X X X AIN X X VID (Note 6) DIN High-Z X L Read from SRAM H L H L H AIN L L H X DOUT DOUT H L High-Z DOUT L H DOUT High-Z Write to SRAM H L H X L AIN L L H X DIN DIN H L High-Z DIN L H DIN High-Z

February 6, 2004 Table 2. Device Bus Operations—Flash Byte Mode (CIOf = VSS), SRAM Word Mode (CIOs = VCC) Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In (for Flash Byte Mode, DQ15 = A-1), DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# Addr. LB#s (Note 3) UB#s (Note 3) RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ0 Read from Flash L H X L H AIN X X H L/H DOUT High-Z X L Write to Flash L H X H L AIN X X H (Note 3) DIN High-Z X L Standby VCC ± 0.3 V H X X X X X X VCC ± 0.3 V H High-Z High-Z X L Output Disable L L H H H X L X H L/H High-Z High-Z H X X X L Flash Hardware Reset X H X X X X X X L L/H High-Z High-Z X L Sector Protect (Note 5) L H X H L SA, A6 = L, A1 = H, A0 = L X X VID L/H DIN X X L Sector Unprotect (Note 5) L H X H L SA, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X X L Temporary Sector Unprotect X H X X X AIN X X VID (Note 6) DIN High-Z X L Read from SRAM H L H L H AIN L L H X DOUT DOUT H L High-Z DOUT L H DOUT High-Z Write to SRAM H L H X L AIN L L H X DIN DIN H L High-Z DIN L H DIN High-Z

February 6, 2004 Am42DL16x2D Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ0–DQ15 are active and controlled by CE# and OE#. If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to VIL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at VIH. The CIOf pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Flash Read-Only Opera- tions table for timing specifications and to Figure 14 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to VIL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 4–5 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively.

February 6, 2004 Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE#f and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de- vice requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard ad- dress access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ± 0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo- rithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 3. Device Bank Division Device Part Number Bank 1 Bank 2 Megabits Sector Sizes Megabits Sector Sizes Am29DL161D Eight 8 Kbyte/4 Kword, three 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, seven 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, fifteen 64 Kbyte/32 Kword

February 6, 2004 Am42DL16x2D Table 4. Sector Addresses for Top Boot Sector Devices Note: The address range is A19:A-1 in byte mode (CIOf=VIL) or A19:A0 in word mode (CIOf=VIH). The bank address bits are A19–A15 for Am29DL161DT, A19–A17 for Am29DL162DT, A19 and A18 for Am29DL163DT, and A19 for Am29DL164DT Table 5. SecSi Sector Addresses for Top Boot Devices Am29DL164DT Am29DL163DT Am29DL162DT Am29DL161DT Sector Sector Address A19–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Bank 2 Bank 2 Bank 2 Bank 2 SA0 00000xxx 000000h-00FFFFh 00000h–07FFFh SA1 00001xxx 010000h-01FFFFh 08000h–0FFFFh SA2 00010xxx 020000h-02FFFFh 10000h–17FFFh SA3 00011xxx 030000h-03FFFFh 18000h–1FFFFh SA4 00100xxx 040000h-04FFFFh 20000h–27FFFh SA5 00101xxx 050000h-05FFFFh 28000h–2FFFFh SA6 00110xxx 060000h-06FFFFh 30000h–37FFFh SA7 00111xxx 070000h-07FFFFh 38000h–3FFFFh SA8 01000xxx 080000h-08FFFFh 40000h–47FFFh SA9 01001xxx 090000h-09FFFFh 48000h–4FFFFh SA10 01010xxx 0A0000h-0AFFFFh 50000h–57FFFh SA11 01011xxx 0B0000h-0BFFFFh 58000h–5FFFFh SA12 01100xxx 0C0000h-0CFFFFh 60000h–67FFFh SA13 01101xxx 0D0000h-0DFFFFh 68000h–6FFFFh SA14 01110xxx 0E0000h-0EFFFFh 70000h–77FFFh SA15 01111xxx 0F0000h-0FFFFFh 78000h–7FFFFh Bank 1 SA16 10000xxx 100000h-10FFFFh 80000h–87FFFh SA17 10001xxx 110000h-11FFFFh 88000h–8FFFFh SA18 10010xxx 120000h-12FFFFh 90000h–97FFFh SA19 10011xxx 130000h-13FFFFh 98000h–9FFFFh SA20 10100xxx 140000h-14FFFFh A0000h–A7FFFh SA21 10101xxx 150000h-15FFFFh A8000h–AFFFFh SA22 10110xxx 160000h-16FFFFh B0000h–B7FFFh SA23 10111xxx 170000h-17FFFFh B8000h–BFFFFh Bank 1 SA24 11000xxx 180000h-18FFFFh C0000h–C7FFFh SA25 11001xxx 190000h-19FFFFh C8000h–CFFFFh SA26 11010xxx 1A0000h-1AFFFFh D0000h–D7FFFh SA27 11011xxx 1B0000h-1BFFFFh D8000h–DFFFFh Bank 1 SA28 11100xxx 1C0000h-1CFFFFh E0000h–E7FFFh SA29 11101xxx 1D0000h-1DFFFFh E8000h–EFFFFh SA30 11110xxx 1E0000h-1EFFFFh F0000h–F7FFFh Bank 1 SA31 11111000 1F0000h-1F1FFFh F8000h–F8FFFh SA32 11111001 1F2000h-1F3FFFh F9000h–F9FFFh SA33 11111010 1F4000h-1F5FFFh FA000h–FAFFFh SA34 11111011 1F6000h-1F7FFFh FB000h–FBFFFh SA35 11111100 1F8000h-1F9FFFh FC000h–FCFFFh SA36 11111101 1FA000h-1FBFFFh FD000h–FDFFFh SA37 11111110 1FC000h-1FDFFFh FE000h–FEFFFh SA38 11111111 1FE000h-1FFFFFh FF000h–FFFFFh Device Sector Address A19–A12 Sector Size (x8) Address Range (x16) Address Range Am29DL16xDT 11111XXX 1F0000h-1FFFFFh F8000h–FFFFFh

February 6, 2004 Table 6. Sector Addresses for Bottom Boot Sector Devices Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19–A15 for Am29DL161DB, A19–A17 for Am29DL162DB, A19 and A18 for Am29DL163DB, and A19 for Am29DL164DB. Table 7. SecSi™ Addresses for Bottom Boot Devices Am29DL164DB Am29DL163DB Am29DL162DB Am29DL161DB Sector Sector Address A19–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range Bank 1 Bank 1 Bank 1 Bank 1 SA0 00000000 000000h-001FFFh 00000h-00FFFh SA1 00000001 002000h-003FFFh 01000h-01FFFh SA2 00000010 004000h-005FFFh 02000h-02FFFh SA3 00000011 006000h-007FFFh 03000h-03FFFh SA4 00000100 008000h-009FFFh 04000h-04FFFh SA5 00000101 00A000h-00BFFFh 05000h-05FFFh SA6 00000110 00C000h-00DFFFh 06000h-06FFFh SA7 00000111 00E000h-00FFFFh 07000h-07FFFh Bank 2 SA8 00001XXX 010000h-01FFFFh 08000h-0FFFFh SA9 00010XXX 020000h-02FFFFh 10000h-17FFFh SA10 00011XXX 030000h-03FFFFh 18000h-1FFFFh Bank 2 SA11 00100XXX 040000h-04FFFFh 20000h-27FFFh SA12 00101XXX 050000h-05FFFFh 28000h-2FFFFh SA13 00110XXX 060000h-06FFFFh 30000h-37FFFh SA14 00111XXX 070000h-07FFFFh 38000h-3FFFFh Bank 2 SA15 01000XXX 080000h-08FFFFh 40000h-47FFFh SA16 01001XXX 090000h-09FFFFh 48000h-4FFFFh SA17 01010XXX 0A0000h-0AFFFFh 50000h-57FFFh SA18 01011XXX 0B0000h-0BFFFFh 58000h-5FFFFh SA19 01100XXX 0C0000h-0CFFFFh 60000h-67FFFh SA20 01101XXX 0D0000h-0DFFFFh 68000h-6FFFFh SA21 01110XXX 0E0000h-0EFFFFh 70000h-77FFFh SA22 01111XXX 0F0000h-0FFFFFh 78000h-7FFFFh Bank 2 SA23 10000XXX 100000h-10FFFFh 80000h-87FFFh SA24 10001XXX 110000h-11FFFFh 88000h-8FFFFh SA25 10010XXX 120000h-12FFFFh 90000h-97FFFh SA26 10011XXX 130000h-13FFFFh 98000h-9FFFFh SA27 10100XXX 140000h-14FFFFh A0000h-A7FFFh SA28 10101XXX 150000h-15FFFFh A8000h-AFFFFh SA29 10110XXX 160000h-16FFFFh B0000h-B7FFFh SA30 10111XXX 170000h-17FFFFh B8000h-BFFFFh SA31 11000XXX 180000h-18FFFFh C0000h-C7FFFh SA32 11001XXX 190000h-19FFFFh C8000h-CFFFFh SA33 11010XXX 1A0000h-1AFFFFh D0000h-D7FFFh SA34 11011XXX 1B0000h-1BFFFFh D8000h-DFFFFh SA35 11100XXX 1C0000h-1CFFFFh E0000h-E7FFFh SA36 11101XXX 1D0000h-1DFFFFh E8000h-EFFFFh SA37 11110XXX 1E0000h-1EFFFFh F0000h-F7FFFh SA38 11111XXX 1F0000h-1FFFFFh F8000h-FFFFFh Device Sector Address A19–A12 Sector Size (x8) Address Range (x16) Address Range Am29DL16xDB 00000XXX 000000h-00FFFFh 00000h-07FFFh

February 6, 2004 Am42DL16x2D Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended to automatically match a device to be programmed with its corresponding pro- gramming algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 14. This method does not require VID. Refer to the Autoselect Com- mand Sequence section for more information. Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9). Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection and unprotection can be im- plemented as follows. Sector protection/unprotection requires VID on the RE- SET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 26 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previ- ously protected sectors must be individually re-protected. To change data in protected sectors effi- Sector / Sector Block A19–A12 Sector / Sector Block Size SA0 00000XXX 00001XXX, 00010XXX, 00011XXX 192 (3x64) Kbytes SA4-SA7 001XXXXX 256 (4x64) Kbytes SA8-SA11 010XXXXX 256 (4x64) Kbytes SA12-SA15 011XXXXX 256 (4x64) Kbytes SA16-SA19 100XXXXX 256 (4x64) Kbytes SA20-SA23 101XXXXX 256 (4x64) Kbytes SA24-SA27 110XXXXX 256 (4x64) Kbytes SA28-SA30 11100XXX, 11101XXX, 11110XXX 192 (3x64) Kbytes SA31 11111000 A19–A12 Sector / Sector Block Size SA38 11111XXX 11110XXX, 11101XXX, 11100XXX 192 (3x64) Kbytes SA34-SA31 110XXXXX 256 (4x64) Kbytes SA30-SA27 101XXXXX 256 (4x64) Kbytes SA26-SA23 100XXXXX 256 (4x64) Kbytes SA22-SA19 011XXXXX 256 (4x64) Kbytes SA18-SA15 010XXXXX 256 (4x64) Kbytes SA14-SA11 001XXXXX 256 (4x64) Kbytes SA10-SA8 00001XXX, 00010XXX, 00011XXX 192 (3x64) Kbytes SA7 00000111 A19–A12 Sector / Sector Block Size

February 6, 2004 The device is shipped with all sectors unprotected. It is possible to determine whether a sector is pro- tected or unprotected. See the Autoselect Mode section for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the de- vice disables program and erase functions in the two “outermost” 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a top-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the de- vice reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sec- tor/Sector Block Protection and Unprotection”. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9). This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin to VID (8.5 V – 12.5 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously pro- tected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timing diagrams, for this feature. START Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) RESET# = VID (Note 1) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation

February 6, 2004 Am42DL16x2D Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Set up sector address Wait 150 µs Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs First Write Cycle = 60h? Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Yes Yes No PLSCNT = 25? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Set up first sector address Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Read from sector address with A6 = 1, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 µs Data = 00h? Last sector verified? Remove VID from RESET# Write reset command Sector Unprotect complete Yes No PLSCNT = 1000? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No All sectors protected? Yes Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Set up next sector address No Yes No Yes No No Yes No Sector Protect Algorithm Sector Unprotect Algorithm First Write Cycle = 60h? Protect another sector? Reset PLSCNT = 1

February 6, 2004 SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 Kbytes in length, and uses a SecSi Sector Indicator Bit to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. Current version of this device has 64 Kbytes; future ver- sions will have only 256 bytes. This should be considered during system design. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the unprotected, allowing cus- tomers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with a random, se- cure ESN only In devices that have an ESN, the Top Boot device will have the 16-byte ESN, with the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses F8000h–F8007h in word mode (or 1F0000h–1F000Fh in byte mode). Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. Current version of this device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. The SecSi Sector can be read, programmed, and erased as often as required. Note that the accelerated program- ming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either VIH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection”. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subse- quent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

February 6, 2004 Am42DL16x2D Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle, CE#f and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to reading array data on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The sys- tem can read CFI information at the addresses given in Tables 10–13. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10–13. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/over- view/cfi.html. Alternatively, contact an AMD representative for copies of these documents. Table 10. CFI Query Identification String Addresses (Word Mode) Data Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists)

February 6, 2004 Table 11. System Interface String Table 12. Device Geometry Definition Addresses (Word Mode) Data VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0004h Typical timeout per single byte/word write 2N µs 20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0005h Max. timeout for byte/word write 2N times typical 24h 0000h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Addresses (Word Mode) Data Device Size = 2N byte 28h 29h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0002h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 003Eh 0000h 0000h 0001h Erase Block Region 2 Information 35h 36h 37h 38h 0000h 0000h 0000h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information

February 6, 2004 Am42DL16x2D Table 13. Primary Vendor-Specific Extended Query Note: The number of sectors in Bank 2 is device dependent. Am29DL161 = 1Fh Am29DL162 = 1Ch Am29DL163 = 18h Am29DL164 = 10h Addresses (Word Mode) Data Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII 45h 0001h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme 04 = 29LV800 mode 4Ah 00XXh (See Note) Simultaneous Operation 00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank) 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 000Xh Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device

February 6, 2004 COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Table 14 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 14 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: ■A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. ■A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. ■A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 4–5 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend).

February 6, 2004 Am42DL16x2D Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to nor- mal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm. Table 14 shows the ad- dress and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Note that a hardware reset (RESET#=VIL) will reset the de- vice to reading array data. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the CIOf pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cy- cles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. Table 14 shows the address and data requirements for the byteword program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 14 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The bank then returns to the reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Flash Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

February 6, 2004 Table 14. Command Definitions Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE#f pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE#f pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Notes: See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. Unless otherwise noted, address bits A19–A11 are don’t cares. No unlock or command cycles required when bank is in read mode. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information. The data is 80h for factory locked and 00h for not factory locked. 10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. Table 15. Autoselect Device ID Codes T = Top Boot Sector, B = Bottom Boot Sector Command Sequence (Note 1) Cycles Bus Cycles (Notes 2–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 6) RA RD Reset (Note 7) XXX Autoselect (Note 8) Manufacturer ID Word 555 AA 2AA (BA)555 (BA)X00 Device ID Word 555 AA 2AA (BA)555 (BA)X01 see Table SecSi Sector Factory Protect (Note 9) Word 555 AA 2AA (BA)555 (BA)X03 Sector Protect Verify (Note 10) Word 555 AA 2AA (BA)555 (SA)X02 Enter SecSi Sector Region Word 555 AA 2AA 555 Exit SecSi Sector Region Word 555 AA 2AA 555 XXX Program Word 555 AA 2AA 555 PA PD Unlock Bypass Word 555 AA 2AA 555 Unlock Bypass Program (Note 11) XXX PA PD Unlock Bypass Reset (Note 12) XXX XXX Chip Erase Word 555 AA 2AA 555 555 AA 2AA 555 Sector Erase Word 555 AA 2AA 555 555 AA 2AA SA Erase Suspend (Note 13) BA Erase Resume (Note 14) BA CFI Query (Note 15) Word Device Autoselect Device ID Am29DL161D 36h (T), 39h (B) Am29DL162D 2Dh (T), 2Eh (B) Am29DL163D 28h (T), 2Bh (B) Am29DL164D 33h (T), 35h (B)

February 6, 2004 Table 16. Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle N/A No toggle Embedded Erase Algorithm Toggle Toggle Erase Suspend Mode Erase-Suspend- Read Erase Suspended Sector No toggle N/A Toggle Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle N/A N/A

February 6, 2004 DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current VCC = VCC max; RESET# = 12.5 V µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current VCC = VCC max, WP#/ACC = VACC max µA ICC1f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Word Mode Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL mA ICC3f Flash VCC Standby Current (Note 2) VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCCf ± 0.3 V 0.2 µA ICC4f Flash VCC Reset Current (Note 2) VCCf = VCC max, RESET# = VSS ± 0.3 V, WP#/ACC = VCCf ± 0.3 V 0.2 µA ICC5f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCCf = VCC max, VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 µA ICC6f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = VIL, OE# = VIH mA ICC7f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH mA ICC8f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = VIL, OE#f = VIH mA IACC ACC Accelerated Program Current CE#f = VIL, OE# = VIH ACC pin mA VCC pin mA ICC4s SRAM VCC Standby Current CE1#s ≥ VCCs – 0.2V, CE2s ≥ VCCs – 0.2V µA ICC5s SRAM VCC Standby Current CE2s ≤ 0.2V µA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 VCC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 8.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCCf = VCCs = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCCf = VCCs = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4

February 6, 2004 Am42DL16x2D Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC1s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V mA ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH mA VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = –1.0 mA 2.4 V ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC – CE2 ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC, Other input = 0 ~ VCC µA DC CHARACTERISTICS (Continued) CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit

February 6, 2004 Am42DL16x2D TEST CONDITIONS Table 17. Test Specifications KEY TO SWITCHING WAVEFORMS 2.7 kΩ CL 6.2 kΩ 3.3 V Device Under Test Note: Diodes are IN3064 or equivalent Figure 11. Test Setup Test Condition 70, 85 ns Unit Output Load Output Load Capacitance, CL (including jig capacitance) pF Input Rise and Fall Times ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V KS000010-PAL WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 3.0 V 0.0 V 1.5 V 1.5 V Output Measurement Level Input Figure 12. Input Waveforms and Measurement Levels

February 6, 2004 AC CHARACTERISTICS SRAM CE#s Timing Figure 13. Timing Diagram for Alternating Between SRAM to Flash Parameter CE#s Recover Time Min ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS Flash Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 17 for test specifications. Parameter Read Cycle Time (Note 1) Min ns tAVQV tACC Address to Output Delay CE#f, OE# = VIL Max ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max ns tGLQV tOE Output Enable to Output Delay Max ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max ns tAXQX tOH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min ns tOEH Output Enable Hold Time (Note 1) Read Min ns Toggle and Data# Polling Min ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF Figure 14. Read Operation Timings

February 6, 2004 AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min ns tRPD RESET# Low to Standby Mode Min µs tRB RY/BY# Recovery Time Min ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#f, OE# tRH CE#f, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB Figure 15. Reset Timings

February 6, 2004 AC CHARACTERISTICS Flash Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options Unit JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time (WE# to Address) Min ns tASO Address Setup Time to OE# or CE#f low during toggle bit polling Min ns tWLAX tAH Address Hold Time (WE# to Address) Min ns tAHT Address Hold Time From CE#f or OE# high during toggle bit polling Min ns tDVWH tDS Data Setup Time Min ns tWHDX tDH Data Hold Time Min ns tOEH OE# Hold Time Read Min ns Toggle and Data# Polling Min ns tOEPH Output Enable High during toggle bit polling Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) Min ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min ns tELWL tCS CE#f Setup Time (WE# to CE#f) Min ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min ns tWHEH tCH CE#f Hold Time (CE#f to WE#) Min ns tWLWH tWP Write Pulse Width Min ns tELEH tCP CE#f Pulse Width Min ns tWHDL tWPH Write Pulse Width High Min ns tSR/W Latency Between Read and Write Operations Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCCf Setup Time (Note 1) Min µs tRB Write Recovery Time from RY/BY# Min ns tBUSY Program/Erase Valid to RY/BY# Delay Max ns

February 6, 2004 AC CHARACTERISTICS OE# CE#f Addresses VCCf WE# Data 2AAh SADD tGHWL tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH In Progress Complete tWHWH2 VA VA Erase Command Sequence (last two cycles) Read Status Data RY/BY# tRB tBUSY Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). 2. These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Note: Not 100% tested. Parameter All Speed Options Unit JEDEC Std VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector/Sector Block Unprotect Min µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector/Sector Block Unprotect Min µs RESET# tVIDR VID VSS, VIL, or VIH VID VSS, VIL, or VIH CE#f WE# RY/BY# tVIDR tRSP Program or Erase Command Sequence tRRB Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram

February 6, 2004 AC CHARACTERISTICS Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms 1 µs RESET# SADD, A6, A1, A0 Data CE#f WE# OE# 60h 60h 40h Valid* Valid* Valid* Status Sector/Sector Block Protect or Unprotect Verify VID VIH * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. SA = Sector Address Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time (WE# to Address) Min ns tASO Address Setup Time to CE#f Low During Toggle Bit Polling Min ns tELAX tAH Address Hold Time Min ns tAHT Address Hold time from CE#f or OE# High During Toggle Bit Polling Min ns tDVEH tDS Data Setup Time Min ns tEHDX tDH Data Hold Time Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time Min ns tEHWH tWH WE# Hold Time Min ns tELEH tCP CE#f Pulse Width Min ns tEHEL tCPH CE#f Pulse Width High Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

February 6, 2004 AC CHARACTERISTICS tGHEL tWS OE# CE#f WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# DOUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase tBUSY Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS SRAM Read Cycle Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 28. SRAM Read Cycle—Address Controlled Parameter Symbol tCO1, tCO2 Chip Enable to Output Max ns tOE Output Enable Access Time Max ns tBA LB#s, UB#s to Valid Output Max ns tLZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output Min ns tBLZ UB#, LB# Enable to Low-Z Output Min ns tOLZ Output Enable to Low-Z Output Min ns tHZ1, tHZ2 Chip disable to High-Z Output Min ns Max tBHZ UB#s, LB#s Disable to High-Z Output Min ns Max tOHZ Output Disable to High-Z Output Min ns Max tOH Output Data Hold from Address Change Min ns Address Data Out Previous Data Valid Data Valid tAA tRC tOH

February 6, 2004 AC CHARACTERISTICS Figure 29. SRAM Read Cycle Notes: 1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing. 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. Data Valid High-Z tRC CE#1s Address OE# Data Out tOH tAA tCO1 tOE tOLZ tBLZ tLZ tOHZ tHZ CE2s tCO2

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS SRAM Write Cycle Notes: 1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing. 1. tCW is measured from CE1#s going low to the end of write. 2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 3. tAS is measured from the address valid to the beginning of write. 4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 30. SRAM Write Cycle—WE# Control Parameter Symbol Chip Enable to End of Write Min ns tAS Address Setup Time Min ns tAW Address Valid to End of Write Min ns tBW UB#s, LB#s to End of Write Min ns tWP Write Pulse Time Min ns tWR Write Recovery Time Min ns tWHZ Write to Output High-Z Min ns Max tDW Data to Write Time Overlap Min ns tDH Data Hold from Write Time Min ns tOW End Write to Output Low-Z Min ns Address CE1#s Data Undefined UB#s, LB#s WE# Data In Data Out tWC tCW (See Note 2) tAW High-Z High-Z Data Valid CE2s tCW (See Note 2) tBW tWP (See Note 5) tAS (See Note 4) tWR (See Note 3) tWHZ tDW tDH tOW

February 6, 2004 AC CHARACTERISTICS Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing. 1. tCW is measured from CE1#s going low to the end of write. 2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 3. tAS is measured from the address valid to the beginning of write. 4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 31. SRAM Write Cycle—CE1#s Control Address Data Valid UB#s, LB#s WE# Data In Data Out High-Z High-Z tWC CE1#s CE2s tAW tAS (See Note 2 ) tBW tCW (See Note 3) tWR (See Note 4) tWP (See Note 5) tDW tDH

February 6, 2004 Am42DL16x2D AC CHARACTERISTICS Notes: 1. UB#s and LB#s controlled, CIOs must be high. 1. tCW is measured from CE1#s going low to the end of write. 2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 3. tAS is measured from the address valid to the beginning of write. 4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. Figure 32. SRAM Write Cycle—UB#s and LB#s Control Address Data Valid UB#s, LB#s WE# Data In Data Out High-Z High-Z tWC CE1#s CE2s tAW tBW tDW tDH tWR (See Note 3) tAS (See Note 4) tCW (See Note 2) tCW (See Note 2) tWP (See Note 5)

February 6, 2004 FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most byteswords program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytewords are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. FLASH LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Note: 7.Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time sec Byte Program Time 150 µs Word Program Time 210 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 120 µs Byte Mode Chip Program Time (Note 3) Word Mode sec Input voltage with respect to VSS on all pins except I/O pins (including OE# and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol VIN = 0 pF COUT Output Capacitance VOUT = 0 pF CIN2 Control Pin Capacitance VIN = 0 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C Years 125°C Years

February 6, 2004 PHYSICAL DIMENSIONS FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm 1.40 (max) 0.20 (min) A B C D E F G H J K 0.80 0.80 (69x) Pin A1 Corner Index Mark 0.08 0.15 M B M C C A 0.40 DATUM A DATUM B B A 0.08 0.97 1.07 C 0.20 C 0.15 C (2x) 0.15 C (2x) C 0.40 0.25 0.35

February 6, 2004 Am42DL16x2D REVISION SUMMARY Revision A (October 24, 2001) Initial release. Revision A+1 (March 4, 2002) Changed package marking for Am42DL1642D (4 part numbers). Figure 30, SRAM Write Cycle—WE# Control In Data Out waveform, corrected tBW to tWHZ. Revision A+2 (February 6, 2004) Command Definitions The result of writing incorrect address and data values changed to reflect that doing so places the device in an unknown state. Unlock Bypass Command Sequence Deleted statements regarding what the first and sec- ond cycles must contain to exit the unlock bypass mode. Reset command sequence changed from BA to XXX.

February 6, 2004 Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

February 6, 2004 Am42DL16x2D