AM42BDS640AG AMD | Alldatasheet

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/G45/G88/G79/G92/G3/G21/G19/G19/G22 /G55/G75/G72/G3/G73/G82/G79/G79/G82/G90/G76/G81/G74/G3/G71/G82/G70/G88/G80/G72/G81/G87/G3/G86/G83/G72/G70/G76/G73/G76/G72/G86/G3/G54/G83/G68/G81/G86/G76/G82/G81/G3/G80/G72/G80/G82/G85/G92/G3/G83/G85/G82/G71/G88/G70/G87/G86/G3/G87/G75/G68/G87/G3/G68/G85/G72/G3/G81/G82/G90/G3/G82/G73/G73/G72/G85/G72/G71/G3/G69/G92/G3/G69/G82/G87/G75/G3/G36/G71/G89/G68/G81/G70/G72/G71 /G48/G76/G70/G85/G82/G3/G39/G72/G89/G76/G70/G72/G86/G3/G68/G81/G71/G3/G41/G88/G77/G76/G87/G86/G88/G17/G3/G36/G79/G87/G75/G82/G88/G74/G75/G3/G87/G75/G72/G3/G71/G82/G70/G88/G80/G72/G81/G87/G3/G76/G86/G3/G80/G68/G85/G78/G72/G71/G3/G90/G76/G87/G75/G3/G87/G75/G72/G3/G81/G68/G80/G72/G3/G82/G73/G3/G87/G75/G72/G3/G70/G82/G80/G83/G68/G81/G92/G3/G87/G75/G68/G87/G3/G82/G85/G76/G74/G16 /G76/G81/G68/G79/G79/G92/G3/G71/G72/G89/G72/G79/G82/G83/G72/G71/G3/G87/G75/G72/G3/G86/G83/G72/G70/G76/G73/G76/G70/G68/G87/G76/G82/G81/G15/G3/G87/G75/G72/G86/G72/G3/G83/G85/G82/G71/G88/G70/G87/G86/G3/G90/G76/G79/G79/G3/G69/G72/G3/G82/G73/G73/G72/G85/G72/G71/G3/G87/G82/G3/G70/G88/G86/G87/G82/G80/G72/G85/G86/G3/G82/G73/G3/G69/G82/G87/G75/G3/G36/G48/G39/G3/G68/G81/G71 /G41/G88/G77/G76/G87/G86/G88/G17 Continuity of Specifications /G55/G75/G72/G85/G72/G3/G76/G86/G3/G81/G82/G3/G70/G75/G68/G81/G74/G72/G3/G87/G82/G3/G87/G75/G76/G86/G3/G71/G68/G87/G68/G86/G75/G72/G72/G87/G3/G68/G86/G3/G68/G3/G85/G72/G86/G88/G79/G87/G3/G82/G73/G3/G82/G73/G73/G72/G85/G76/G81/G74/G3/G87/G75/G72/G3/G71/G72/G89/G76/G70/G72/G3/G68/G86/G3/G68/G3/G54/G83/G68/G81/G86/G76/G82/G81/G3/G83/G85/G82/G71/G88/G70/G87/G17/G3/G3/G36/G81/G92 /G70/G75/G68/G81/G74/G72/G86/G3/G87/G75/G68/G87/G3/G75/G68/G89/G72/G3/G69/G72/G72/G81/G3/G80/G68/G71/G72/G3/G68/G85/G72/G3/G87/G75/G72/G3/G85/G72/G86/G88/G79/G87/G3/G82/G73/G3/G81/G82/G85/G80/G68/G79/G3/G71/G68/G87/G68/G86/G75/G72/G72/G87/G3/G76/G80/G83/G85/G82/G89/G72/G80/G72/G81/G87/G3/G68/G81/G71/G3/G68/G85/G72/G3/G81/G82/G87/G72/G71/G3/G76/G81/G3/G87/G75/G72 /G71/G82/G70/G88/G80/G72/G81/G87/G3/G85/G72/G89/G76/G86/G76/G82/G81/G3/G86/G88/G80/G80/G68/G85/G92/G15/G3/G90/G75/G72/G85/G72/G3/G86/G88/G83/G83/G82/G85/G87/G72/G71/G17/G3/G3/G41/G88/G87/G88/G85/G72/G3/G85/G82/G88/G87/G76/G81/G72/G3/G85/G72/G89/G76/G86/G76/G82/G81/G86/G3/G90/G76/G79/G79/G3/G82/G70/G70/G88/G85/G3/G90/G75/G72/G81/G3/G68/G83/G83/G85/G82/G83/G85/G76/G68/G87/G72/G15 /G68/G81/G71/G3/G70/G75/G68/G81/G74/G72/G86/G3/G90/G76/G79/G79/G3/G69/G72/G3/G81/G82/G87/G72/G71/G3/G76/G81/G3/G68/G3/G85/G72/G89/G76/G86/G76/G82/G81/G3/G86/G88/G80/G80/G68/G85/G92/G17 Continuity of Ordering Part Numbers /G36/G48/G39/G3/G68/G81/G71/G3/G41/G88/G77/G76/G87/G86/G88/G3/G70/G82/G81/G87/G76/G81/G88/G72/G3/G87/G82/G3/G86/G88/G83/G83/G82/G85/G87/G3/G72/G91/G76/G86/G87/G76/G81/G74/G3/G83/G68/G85/G87/G3/G81/G88/G80/G69/G72/G85/G86/G3/G69/G72/G74/G76/G81/G81/G76/G81/G74/G3/G90/G76/G87/G75/G3/G179/G36/G80/G180/G3/G68/G81/G71/G3/G179/G48/G37/G48/G180/G17/G3/G55/G82/G3/G82/G85/G71/G72/G85 /G87/G75/G72/G86/G72/G3/G83/G85/G82/G71/G88/G70/G87/G86/G15/G3/G83/G79/G72/G68/G86/G72/G3/G88/G86/G72/G3/G82/G81/G79/G92/G3/G87/G75/G72/G3/G50/G85/G71/G72/G85/G76/G81/G74/G3/G51/G68/G85/G87/G3/G49/G88/G80/G69/G72/G85/G86/G3/G79/G76/G86/G87/G72/G71/G3/G76/G81/G3/G87/G75/G76/G86/G3/G71/G82/G70/G88/G80/G72/G81/G87/G17 For More Information /G51/G79/G72/G68/G86/G72/G3/G70/G82/G81/G87/G68/G70/G87/G3/G92/G82/G88/G85/G3/G79/G82/G70/G68/G79/G3/G36/G48/G39/G3/G82/G85/G3/G41/G88/G77/G76/G87/G86/G88/G3/G86/G68/G79/G72/G86/G3/G82/G73/G73/G76/G70/G72/G3/G73/G82/G85/G3/G68/G71/G71/G76/G87/G76/G82/G81/G68/G79/G3/G76/G81/G73/G82/G85/G80/G68/G87/G76/G82/G81/G3/G68/G69/G82/G88/G87/G3/G54/G83/G68/G81/G86/G76/G82/G81 /G80/G72/G80/G82/G85/G92/G3/G86/G82/G79/G88/G87/G76/G82/G81/G86/G17 Am42BDS640AG Data Sheet Publication Number 26445 Revision B Amendment 0 Issue Date November 1, 2002

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26445 Rev: B Amendment/0 Issue Date: November 1, 2002 Refer to AMD’s Website (www.amd.com) for the latest information. Am42BDS640AG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features ■ Power supply voltage of 1.65 to 1.95 volt ■ High performance — Access time as fast as 70 ns ■ Package — 93-Ball FBGA ■ Operating Temperature — –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES ■ Single 1.8 volt read, program and erase (1.65 to 1.95 volt) ■ Manufactured on 0.17 µm process technology ■ Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations — Four bank architecture: 16Mb/16Mb/16Mb/16Mb ■ Programmable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 8, 16, and 32 words with wrap-around — Continuous Sequential Burst ■ Sector Architecture — Eight 8 Kword sectors and one hundred twenty-six 32 Kword sectors — Banks A and D each contain four 8 Kword sectors and thirty-one 32 Kword sectors; Banks B and C each contain thirty-two 32 Kword sectors — Eight 8 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range ■ Minimum 1 million erase cycle guarantee per sector ■ 20-year data retention at 125°C PERFORMANCE CHARCTERISTICS ■ Read access times at 54/40 MHz — Burst access times of 13.5/20 ns @ 30 pF at industrial temperature range — Asynchronous random access times of 70 ns (at 30 pF) — Synchronous latency of 87.5/95 ns ■ Power dissipation (typical values, CL = 30 pF) — Burst Mode Read: 10 mA — Simultaneous Operation: 25 mA — Program/Erase: 15 mA — Standby mode: 0.2 µA HARDWARE FEATURES ■ Software command sector locking ■ Handshaking: host monitors operations via RDY output ■ Hardware reset input (RESET#) ■ WP# input — Write protect (WP#) function protects sectors 0, 1 (bottom boot) or sectors 132 and 133 (top boot), regardless of sector protect status ■ ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL ■ CMOS compatible inputs, CMOS compatible outputs ■ Low V CC write inhibit SOFTWARE FEATURES ■ Supports Common Flash Memory Interface (CFI) ■ Software command set compatible with JEDEC 42.4 standards ■ Data# Polling and toggle bits ■ Erase Suspend/Resume — Suspends or resumes an erase operation in one sector to read data from, or program data to, other sectors ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences SRAM Features ■ Power dissipation — Operating: 3 mA maximum — Standby: 15 µA maximum ■ CE1s# and CE2s Chip Select ■ Power down features using CE1s# and CE2s ■ Data retention supply voltage: 1.0 to 2.2 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

2 Am42BDS640AG November 1, 2002

The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simulta- neous Read/Write, Burst Mode Flash memory device, orga- nized as 4,194,304 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-volt VID may be used for faster pro- gram performance if desired. The device can also be pro- grammed in standard EPROM programmers. At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the de- vice provides a burst access of 20 ns at 30 pF with a latency of 95 ns at 30 pF. The device operates within the industrial temperature range of -40°C to +85°C. The device is offered in a 93-ball FBGA package. The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from wait- ing for the completion of program or erase operations. The device is divided as shown in the following table: The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst opera- tions, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/micro- controllers for high performance read operations. The burst read mode feature gives system designers flexibil- ity in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The ac- tive clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firm- ware from the Flash memory device. The host system can detect whether a program or erase op- eration is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. The sector lock/unlock com- mand sequence disables or re-enables both program and erase operations in any sector. When at VIL, WP# locks sec- tors 0 and 1 (bottom boot device) or sectors 132 and 133 (top boot device). The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power con- sumption is greatly reduced in both modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. Bank Quantity Size A 4 8 Kwords 31 32 Kwords B 32 32 Kwords C 32 32 Kwords D 31 32 Kwords 4 8 Kwords

4 Am42BDS640AG November 1, 2002

Figure 27. Data# Polling Timings (During Embedded Algorithm) ... 57 Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings . 58 Figure 31. Latency with Boundary Crossing Figure 32. Example of Wait States Insertion (Standard

November 1, 2002 Am42BDS640AG 5 PRELIMINARY PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am42BDS640AG Burst Frequency 54 MHz 40 MHz Speed Option VCC, VIO = 1.65 – 1.95 V D8, D9 C8, C9 Flash Max Initial Synchronous Access Time, ns (tIACC ) Reduced Wait-state Handshaking: Even Address 87.5 95 Max Initial Synchronous Access Time, ns (tIACC ) Reduced Wait-state Handshaking: Odd Address; or Standard Handshaking 106 120 Max Burst Access Time, ns (tBACC )1 3 . 5 2 0 Max Asynchronous Access Time, ns (tACC ) 70 85 Max CE# Access, ns (tCE ) Max OE# Access, ns (tOE )1 3 . 5 2 0 SRAM Max Access Time, ns (tACC ) 70 85 Max CE# Access, ns (tCE ) Max OE# Access, ns (tOE )3 5 4 0 VSSVCC s RESET# WE# CE#f OE# CE1#s VSSVCC f/VIOf RDY LB#s UB#s WP# CE2s

16 M Bit

64 M Bit

AVD# CLK A19 to A0 A21 to A0

6 Am42BDS640AG November 1, 2002

FLASH MEMORY BLOCK DIAGRAM Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS VSSIO VIO WE# RESET# WP# ACC CE# OE# DQ15 –DQ0 Data Latch Y-Gating Cell Matrix Address Latch A21–A0 RDY Buffer RDY Burst State Control Burst Address Counter AVD# CLK

November 1, 2002 Am42BDS640AG 7 PRELIMINARY FLASH MEMORY SIMULTANEOUS OPERATION DIAGRAM VSS VCC VIO VSSIO Bank B Address RESET# ACC WE# CE# AVD# RDY DQ15–DQ0 WP# STATE CONTROL COMMAND REGISTER Bank B X-Decoder Y-Decoder Latches and Control Logic Bank A X-Decoder Y-Decoder Latches and Control Logic DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Bank C Y-Decoder X-Decoder Latches and Control Logic Bank D Y-Decoder X-Decoder Latches and Control Logic OE# Status Control A21–A0 A21–A0 A21–A0 A21–A0 A21–A0 Bank C Address Bank D Address Bank A Address

8 Am42BDS640AG November 1, 2002

Note:VIOf must be tied to VCC f. Special Package Handling Instructions Special handling is required for Flash Memory prod- ucts in molded packages (TSOP , BGA, PLCC, PDIP , SSOP). The package and/or data integrity may be compromised if the package body is exposed to tem- peratures above 150°C for prolonged periods of time. NC F10 L10 G10 NC NC NC NC NC AVD# NC VSS DQ8 UB# CLK A18 A17 DQ1 DQ2 NC RESET# RDY DQ11 NC CE2s A20 NC NC NC NC NC A19 NC A10 DQ6 DQ5 A12 A13 A14 NC DQ14 A21 NC B8 B9 NC NC A15 A16 CE#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 NC NC NC NC V SS VIOfN C N C N C CE#1s DQ0 DQ10 V CCfV CCs DQ12 DQ7 V SS K2 K3 K4 K5 K6 K7 K8 K9 NC NC M10 NC NC A10 B10 NC NC C3 C4 C5 C6 C7 C8 WP# LB# ACC WE# A8 A11 NC C9C1 NC NC NC SRAM only Shared Flash only 93-Ball FBGA Top View

November 1, 2002 Am42BDS640AG 9 PRELIMINARY PIN DESCRIPTION A19–A0 = 20 Address Inputs (Common) A21–A20 = 2 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (SRAM) CE2s = Chip Enable 2 (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) RESET# = Hardware Reset Pin, Active Low V CC f = Flash 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage sup- ply tolerances) V IOf = Input & Output Buffer Power Supply must be tied to VCC f. VCC s = SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally RDY = Ready output; indicates the status of the Burst read. Low = data not valid at expected time. High = data valid. CLK = CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. AVD# = Address Valid input. Indicates to de- vice that the valid address is present on the address inputs (A21–A0). Low = for asynchronous mode, indi- cates valid address; for burst mode, causes starting address to be latched. High = device ignores address in- puts WP# = Hardware write protect input. At V IL, disables program and erase func- tions in the two outermost sectors. Should be at V IH for all other condi- tions. ACC = At V ID, accelerates programming; automatically places device in un- lock bypass mode. At V IL, locks all sectors. Should be at VIH for all other conditions. LOGIC SYMBOL DQ15–DQ0 A19–A0 CE#f OE# WE# RESET# UB#s RDY WP# A21–A20 LB#s ACC CE1#s CE2s AVD# CLK

10 Am42BDS640AG November 1, 2002

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Am42BDS640 A G T D 8 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) VIO AND HANDSHAKING FEATURES 8 = 1.8 V V IO, reduced wait-state handshaking 9 = 1.8 V V IO, standard handshaking CLOCK RATE/ASYNCHRONOUS SPEED/SRAM SPEED D = 54 MHz/70 ns/70 ns C = 40 MHz/85 ns/85 ns BOOT SECTOR T = Top Boot Sector B = Bottom Boot Sector PROCESS TECHNOLOGY G = 0.17 µm SRAM DEVICE DENSITY A= 1 6 M b i t s AMD DEVICE NUMBER/DESCRIPTION Am42BDS640AG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM 93-Ball Fine-pitch Ball Grid Array Package, 8.0 x 11.6 mm, 0.8 mm ball pitch (FSC093) Valid Combinations Order Number Package Marking Burst Frequency (MHz) VIO Range Am42BDS640AGTD8I Am42BDS640AGBD8I T, S M42000004Y M42000004Z 1.65 – 1.95 V Am42BDS640AGTD9I Am42BDS640AGBD9I M420000050 M420000051 Am42BDS640AGTC8I Am42BDS640AGBC8I M420000052 M420000053 Am42BDS640AGTC9I Am42BDS640AGBC9I M420000054 M420000055

November 1, 2002 Am42BDS640AG 11 PRELIMINARY MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the re- sulting output. The following subsections describe each of these operations in further detail.

12 Am42BDS640AG November 1, 2002

Table 1. Device Bus Operations

  1. Other operations except for those indicated in this column are
  2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same
  3. Either CE1#s = VIH or CE2s = VIL will disable the SRAM. If one of

these conditions is true, the other CE input is don’t care.

  1. X = Don’t care or open LB#s or UB#s.
  2. Default edge of CLK is the rising edge.
  3. The sector protect and sector unprotect functions may also be

Lock/Unlock Command Sequence”section.

  1. If ACC = VHH , all sectors will be protected.
  2. If WP# = VIL, sectors 0,1 (bottom boot) or sectors 132, 133 (top

edge of OE# to valid data at the output. content occurs during the power transition. operation and linear burst operation of a preset length. burst mode configuration register command sequence. enabled for synchronous reads only. multiple thereof). See Table 10. (or 64 multiple) will not occur. Table 1, “Device Bus Operations,” on page 12. indicates the length of the latency by pulsing low. Table 2. Burst Address Groups

14 Am42BDS640AG November 1, 2002

39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the initial access). The RDY pin indicates when data is valid on the bus. The devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). Burst Mode Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Reduced Wait-State Handshaking Option The device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the RDY signal from the device to deter- mine when the initial word of burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. The presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. See “Autoselect Command Sequence” for details. For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. See “Set Burst Mode Configuration Register Command Sequence” section on page 23 section for more infor- mation. The device will automatically delay RDY and data by one additional clock cycle when the starting address is odd. The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Command Sequence” section for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 33, “Back-to-Back Read/Write Cycle Timings,” on page 62 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asyn- chronous or synchronous write operation. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to V IL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to V IL and OE# to VIH when providing an address, command, and data. The asynchronous and synchronous pro- graming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Reg- ister. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 8, “Programmable Wait State Settings,” on page 24 indicates the address space that each sector occupies. The device address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 8 Kword boot sectors in addition to 32 Kword sec- tors. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts V ID on this input, the device auto- matically enters the aforementioned Unlock Bypass

November 1, 2002 Am42BDS640AG 15 PRELIMINARY mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V ID from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to V ID. Note that the ACC pin must not be at VID for operations other than accelerated pro- gramming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at V IL, ACC locks all sectors. ACC should be at VIH for all other conditions. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Autoselect mode may only be entered and used when in the asynchronous read mode. Refer to the “Autoselect Command Sequence” section on page 26 section for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at V CC ± 0.2 V. The device requires standard access time (tCE ) for read access, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the opera- tion is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for t ACC + 60 ns. The auto- matic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always avail- able to the system. While in synchronous mode, the device automatically enables this mode when either the first active CLK edge occurs after t ACC or the CLK runs slower than 5MHz. Note that a new burst opera- tion is required to provide new data. I CC4 in the “Flash DC Characteristics” section on page 36 represents the automatic sleep mode current spec- ification. RESET#: Hardwa re Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ± 0.2 V, the device draws CMOS standby current (ICC4 ). If RESET# is held at VIL but not within VSS ± 0.2 V, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase oper- ation, the device requires a time of t READY (during Embedded Algorithms) before the device is ready to read data again. If RESET# is asserted when a program or erase operation is not executing, the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after RESET# returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 20, “Reset Timings,” on page 49 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high imped- ance state. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14, “Com- mand Definitions,” on page 30 for command defini- tions). The device offers two types of data protection at the sector level: ■ The sector lock/unlock command sequence dis- ables or re-enables both program and erase opera- tions in any sector.

16 Am42BDS640AG November 1, 2002

or sectors 132 and 133 (top boot) are locked. ■ When ACC is at VIL, all sectors are locked. tions, or from system noise. method of protecting data without using VID. 1 (bottom boot) or sectors 132 and 133 (top boot). sectors were last set to be protected or unprotected. WE# do not initiate a write cycle. automatically reset to the read mode on power-up. ward-compatible for the specified flash device families. for long-term compatibility. CFI data, the system must write the reset command. device to the autoselect mode. Table 3. CFI Query Identification String

Table 4. System Interface String Table 5. Device Geometry Definition

18 Am42BDS640AG November 1, 2002

Table 6. Primary Vendor-Specific Extended Query

Table 7. Sector Address Table

20 Am42BDS640AG November 1, 2002

Table 7. Sector Address Table (Continued)

22 Am42BDS640AG November 1, 2002

device to reading array data. Embedded Program or Embedded Erase algorithm. on page 28 section for more information. (Burst) Read Operation” sections for more information. 11, 13, and 18 show the timings. device will enter burst mode. tions (program, erase, or sector lock). Figure 1. Synchronous/Asynchronous State asynchronous mode, “0” for synchronous mode. after AVD# is driven active before data will be available. related to the clock frequency.

24 Am42BDS640AG November 1, 2002

Table 8. Programmable Wait State Settings

  1. Upon power-up or hardware reset, the default setting is
  2. RDY will default to being active with data when the Wait

State Setting is set to a total initial access cycle of 2. system/device to execute at maximum speed. (wait states) for various conditions. Table 9. Initial Access Codes which are multiples of 3Fh). Command Sequence” section for more information. depending on the clock frequency. Table 10. Wait States for Standard Handshaking which are multiples of 3Fh).

40 MHz

54 MHz

Table 11. Burst Read Mode Settings ting; “1” for rising active, “0” for falling active. OH whenever there is valid data on the outputs. RDY active one clock cycle before valid data. Table 12. Burst Mode Configuration Register Note:Device will be in the default state upon power-up or hardware reset. must write the sector lock/unlock command sequence. writing F0h (reset command). locked by taking the WP# signal to VIL.

26 Am42BDS640AG November 1, 2002

until the operation is complete. before programming begins (prior to the third cycle). until the operation is complete. sequence cycles in an autoselect command sequence. and determine whether or not a sector is protected. sector address. The device ID is read in three cycles. bank was previously in Erase Suspend). mode, to ensure data integrity. Table 13. Device IDs

28 Am42BDS640AG November 1, 2002

Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. The command sequence is two cycles cycles in length instead of six cycles. See Table 14 for details on the unlock bypass command sequences. Figure 2 illustrates the algorithm for the erase opera- tion. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 14 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 35 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sec- tors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any addi- tional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3: Sector Erase Timer” section on page 34.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Flash Write Operation Status” section on page 31 section for infor- mation on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. Figure 2 illustrates the algorithm for the erase opera- tion. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters and timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits.

section for more information. written after the chip has resumed erasing. Figure 3. Program Operation Note:See Table 14 for program command sequence.

30 Am42BDS640AG November 1, 2002

Table 14. Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. latch on the rising edge of the AVD# pulse. erased. Address bits A21–A14 uniquely select any sector. autoselect mode, is in bypass mode, or is being erased. either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19–A12.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

  1. Data bits DQ15–DQ8 are don’t care in command sequences,
  2. Unless otherwise noted, address bits A21–A12 are don’t cares.
  3. No unlock or command cycles required when bank is reading
  4. The Reset command is required to return to reading array data
  5. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

  1. The data in the fifth cycle is 2204h for top boot, 2224h for bottom
  2. The data is 0000h for an unlocked sector and 0001h for a locked
  3. The data is 0043h for reduced wait-state handshaking and 0042h
  4. The Unlock Bypass command sequence is required prior to this
  5. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

  1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

  1. See “Set Burst Mode Configuration Register Command
  2. Command is valid when device is ready to read array data or

when device is in autoselect mode.

32 Am42BDS640AG November 1, 2002

clock cycle before expecting the next word of data. should wait 2 clock cycles before expecting valid data. RDY functions only while reading data in burst mode. Program algorithm is complete. Figure 5. Toggle Bit Algorithm

Table 15, “DQ6 and DQ2 Indications,” on page 33. Table 15. DQ6 and DQ2 Indications determine the status of the operation (top of Figure 4). the erase-suspend-program mode). programming, at any address, toggles, does not toggle. selected for erasure, toggles, also toggles. selected for erasure, toggles, does not toggle. selected for erasure, does not toggle, toggles. from any sector not selected for erasure. erase suspend at any address, toggles, is not applicable.

34 Am42BDS640AG November 1, 2002

applies after each additional sector erase command. be less than 50 µs, the system need not monitor DQ3. device will accept additional sector erase commands. last command might not have been accepted. Table 16. Write Operation Status

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

  1. The system may read either asynchronously or synchronously (burst) while in erase suspend. RDY will function exactly as in

36 Am42BDS640AG November 1, 2002

Note: 1. Maximum ICC specifications are tested with VCC = VCC max. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3 . 5. Total current during accelerated programming is the sum of VACC and VCC currents. Parameter Description Test Conditions (Note 1) Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC , VCC = VCC max ±1 µA ILO Output Leakage Current V OUT = VSS to VCC , VCC = VCC max ±1 µA ICCB VCC Active Burst Read Current CE# = VIL, OE# = VIL, WE# = VIH 10 20 mA IIO1 VIO Active Read Current VIO = 1.8 V, CE# = VIL, OE# = VIL, WE# = VIH 15 30 mA IIO2 VIO Non-active Output V IO = 1.8 V, OE# = VIH 0.2 10 µA ICC1 VCC Active Asynchronous Read Current (Note 2) CE# = VIL, OE# = VIH, WE# = VIH

5 MHz 12 16 mA

1 MHz 3.5 5 mA ICC2 VCC Active Write Current (Note 3) CE# = VIL, OE# = VIH, VPP = VIH 15 40 mA ICC3 VCC Standby Current (Note 4) CE# = RESET# = V CC ± 0.2 V 0.2 10 µA ICC4 VCC Reset Current RESET# = V IL, CLK = VIL 0.2 10 µA ICC5 VCC Active Current (Read While Write) CE# = VIL, OE# = VIH 25 60 mA IACC Accelerated Program Current (Note 5) CE# = VIL, OE# = VIH, VACC = 12.0 ± 0.5 V VACC 71 5 m A VCC 51 0 m A VIL Input Low Voltage V IO = 1.8 V –0.5 0.2 V VIH Input High Voltage V IO = 1.8 V V IO – 0.2 V IO + 0.2 V VOL Output Low Voltage IOL = 100 µA, VCC = VCC min, VIO = VIO min 0.1 V VOH Output High Voltage IOH = –100 µA, VCC = VCC min, VIO = VIO min VIO – 0.1 V VID Voltage for Accelerated Program 11.5 12.5 V VLKO Low VCC Lock-out Voltage 1.0 1.4 V

November 1, 2002 Am42BDS640AG 37 PRELIMINARY Notes: 1. Typical values measured at VCC = 2.0 V, TA = 25°C. Not 100% tested. 2. Undershoot is –1.0 V when pulse width ≤ 20 ns. 3. Overshoot is VCC + 1.0 V when pulse width ≤ 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested. SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V IN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC Operating Power Supply Current IIO = 0 mA, CE1#s = VIL, CE2s = WE# = VIH, VIN = VIH or VIL 5m A ICC1 s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 13 m A ICC2 s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH 82 5 m A VOL Output Low Voltage I OL = 0.1 mA 0.2 V VOH Output High Voltage I OH = –0.1 mA 1.4 V ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –

0.2 V (CE1#s controlled) or CE2 ≤

0.2 V (CE2s controlled), CIOs =

V SS or VCC , Other input = 0 ~ VCC 15 µA VIL Input Low Voltage –0.2 (Note 2) 0.4 V VIH Input High Voltage 1.4 VCC +0.2 (Note 3) V

38 Am42BDS640AG November 1, 2002

Table 17. Test Specifications Figure 8. Test Setup Figure 9. Input Waveforms and Measurement Levels

November 1, 2002 Am42BDS640AG 39 PRELIMINARY AC CHARACTERISTICS SRAM CE#s Timing Figure 10. Timing Diagram for Alternating

Description

Test Setup All Speeds Unit JEDEC Std —t CCR CE#s Recover Time — Min 0 ns C E#f tCCR tCCR C E1#s C E2s tCCR tCCR

40 Am42BDS640AG November 1, 2002

Note: 1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. Parameter (54 MHz) (40 MHz) UnitJEDEC Standard tIACC Latency (Even Address in Reduced Wait-State Handshaking Mode) Max 87.5 95 ns Parameter D8, D9 (54 MHz) C8, C9 (40 MHz) UnitJEDEC Standard tIACC Latency—(Odd Address in Handshaking mode or Standard Handshaking) Max 106 120 ns tBACC Burst Access Time Valid Clock to Output Delay Max 13.5 20 ns tACS Address Setup Time to CLK (Note 1) Min 5 ns tACH Address Hold Time from CLK (Note 1) Min 7 ns tBDH Data Hold Time from Next Clock Cycle Max 4 ns tOE Output Enable to Output Valid Max 13.5 20 ns tCEZ Chip Enable to High Z Max 10 ns tOEZ Output Enable to High Z Max 10 ns tCES CE# Setup Time to CLK Min 5 ns tRDYS RDY Setup Time to CLK Min 5 ns tRACC Ready Access Time from CLK Max 13.5 20 ns tAAS Address Setup Time to AVD# (Note 1) Min 5 ns tAAH Address Hold Time to AVD# (Note 1) Min 7 ns tCAS CE# Setup Time to AVD# Min 0 ns tAVC AVD# Low to CLK Min 5 ns tAVD AVD# Pulse Min 12 ns tACC Access Time Max 70 ns

  1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
  2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
  3. The device is in synchronous mode.

Figure 11. CLK Synchronous Burst Mode Read 7 cycles for initial access shown.

42 Am42BDS640AG November 1, 2002

  1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active falling edge.

  1. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
  2. The device is in synchronous mode.

Figure 12. CLK Synchronous Burst Mode Read 4 cycles for initial access shown.

44 Am42BDS640AG November 1, 2002

command sequence has been written with A18=0; device will output RDY one cycle before valid data. Figure 15. Burst with RDY Set One Cycle Before Data 6 wait cycles for initial access shown.

  1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active rising edge.

  1. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
  2. The device is in synchronous mode.
  3. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under

a CLK synchronous burst mode. Figure 16. Reduced Wait-State Handshaking Burst Mode Read 7 cycles for initial access shown.

46 Am42BDS640AG November 1, 2002

Figure 17. Reduced Wait-State Handshaking Burst Mode Read

  1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active rising edge.

  1. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
  2. The device is in synchronous mode.
  3. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under

a CLK synchronous burst mode. 7 cycles for initial access shown.

November 1, 2002 Am42BDS640AG 47 PRELIMINARY AC CHARACTERISTICS Asynchronous Read Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested. Note:RA = Read Address, RD = Read Data. Figure 18. Asynchronous Mode Read with Latched Addresses D8, D9 (54 MHz) C8, C9 (40 MHz) UnitJEDEC Standard tCE Access Time from CE# Low Max 70 85 ns tACC Asynchronous Access Time (Note 1) Max 70 85 ns tAVDP AVD# Low Time Min 12 ns tAAVDS Address Setup Time to Rising Edge of AVD Min 5 ns tAAVDH Address Hold Time from Rising Edge of AVD Min 7 ns tOE Output Enable to Output Valid Max 13.5 20 ns tOEH Output Enable Hold Time Read Min 0 ns Toggle and Data# Polling Min 10 ns tOEZ Output Enable to High Z (Note 2) Max 10 10.5 ns tCAS CE# Setup Time to AVD# Min 0 ns tCEWE# A21-A0 CE#f OE# Valid RD tACC tOEH tOE D Q15 -DQ0 tOEZ tAAVDH tAVDP tAAVDS AVD# RA tCAS

48 Am42BDS640AG November 1, 2002

Note:RA = Read Address, RD = Read Data. Figure 19. Asynchronous Mode Read

November 1, 2002 Am42BDS640AG 49 PRELIMINARY AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 35 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 200 ns tRPD RESET# Low to Standby Mode Min 20 µs RESET# tRP tReadyw Reset Timings NOT during Embedded Algorithms tReady CE#f, OE# tRH CE#f, OE# Reset Timings during Embedded Algorithms RESET# tRP Figure 20. Reset Timings

50 Am42BDS640AG November 1, 2002

Notes: 1. Not 100% tested. 2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 3. See the “Flash Erase And Programming Performance” section for more information. 4. Does not include the preprogramming time. Parameter Options UnitJEDEC Standard tAVAV tWC Write Cycle Time (Note 1) Min 80 ns tAVWL tAS Address Setup Time (Note 2) Synchronous Min ns Asynchronous 0 tWLAX tAH Address Hold Time (Note 2) Synchronous Min ns Asynchronous 45 tACS Address Setup Time to CLK (Note 2) Min 5 ns tACH Address Hold Time to CLK (Note 2) Min 7 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 ns tCAS CE# Setup Time to AVD# Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 50 ns tWHWL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 3) Typ 8 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 3) Typ 2.5 µs tWHWH2 tWHWH2 Sector Erase Operation (Notes 3, 4) Typ 0.2 sec Chip Erase Operation (Notes 3, 4) 26.8 tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tCSW1 Clock Setup Time to WE# (Asynchronous) Min 5 ns tCSW2 Clock Setup Time to WE# (Synchronous) Min 1 ns tCHW Clock Hold Time from WE# Min 1 ns tELWL tCS CE# Setup Time to WE# Min 0 ns tAVSW AVD# Setup Time to WE# Min 5 ns tAVHW AVD# Hold Time to WE# Min 5 ns tAVHC AVD# Hold Time to CLK Min 5 ns tAVDP AVD# Low Time Min 12 ns

  1. PA = Program Address, PD = Program Data, VA = Valid

Address for reading status bits.

  1. “In progress” and “complete” refer to status of program
  2. A21–A12 are don’t care during command sequence
  3. CLK can be either VIL or VIH.
  4. The Asynchronous programming operation is

Mode Configuration Register.

  1. AVD# must toggle during command sequence if CLK is at

Figure 21. Asynchronous Program Operation Timings

52 Am42BDS640AG November 1, 2002

  1. PA = Program Address, PD = Program Data, VA = Valid

Address for reading status bits.

  1. “In progress” and “complete” refer to status of program
  2. A21–A12 are don’t care during command sequence
  3. CLK can be either VIL or VIH.
  4. The Asynchronous programming operation is

Mode Configuration Register.

  1. AVD# must toggle during command sequence if CLK is at

Figure 22. Alternate Asynchronous Program Operation Timings

  1. PA = Program Address, PD = Program Data, VA = Valid

Address for reading status bits.

  1. “In progress” and “complete” refer to status of program
  2. A21–A12 are don’t care during command sequence
  3. Addresses are latched on the first of either the rising edge

of AVD# or the active edge of CLK.

  1. Either CS# or AVD# is required to go from low to high in

between programming command sequences.

  1. The Synchronous programming operation is independent
  2. CLK must not have an active edge while WE# is at V
  3. AVD# must toggle during command sequence unlock cy-

Figure 23. Synchronous Program Operation Timings

54 Am42BDS640AG November 1, 2002

  1. PA = Program Address, PD = Program Data, VA = Valid

Address for reading status bits.

  1. “In progress” and “complete” refer to status of program
  2. A21–A12 are don’t care during command sequence
  3. Addresses are latched on the first of either the rising edge

of AVD# or the active edge of CLK.

  1. Either CS# or AVD# is required to go from low to high in

between programming command sequences.

  1. The Synchronous programming operation is independent
  2. AVD# must toggle during command sequence unlock cy-
  3. CLK must not have an active edge while WE# is at VIL.

Figure 24. Alternate Synchronous Program Operation Timings

Figure 25. Chip/Sector Erase Command Sequence

  1. SA is the sector address for Sector Erase.
  2. Address bits A21–A12 are don’t cares during unlock cycles in the command sequence.

56 Am42BDS640AG November 1, 2002

Note:Use setup and hold times from conventional program operation. Figure 26. Accelerated Unlock Bypass Programming Timing

58 Am42BDS640AG November 1, 2002

  1. The timings are similar to synchronous read timings.
  2. VA = Valid Address. Two read cycles are required to

operation is complete, the toggle bits will stop toggling.

  1. RDY is active with data (A18 = 0 in the Burst Mode
  2. AVD# must toggle between data reads.

Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings

  1. RDY active with data (A18 = 0 in the Burst Mode Configuration Register).
  2. RDY active one clock cycle before data (A18 = 1 in the Burst Mode Configuration Register).
  3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing

a bank in the process of performing an erase or program. Figure 30. Latency with Boundary Crossing 00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing.

60 Am42BDS640AG November 1, 2002

  1. RDY active with data (A18 = 0 in the Burst Mode Configuration Register).
  2. RDY active one clock cycle before data (A18 = 1 in the Burst Mode Configuration Register).
  3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a

bank in the process of performing an erase or program.

Note:Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”. Figure 32. Example of Wait States Insertion (Standard Handshaking Device)

62 Am42BDS640AG November 1, 2002

the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information. Figure 33. Back-to-Back Read/Write Cycle Timings

Figure 34. SRAM Read Cycle—Address Controlled

64 Am42BDS640AG November 1, 2002

Figure 35. SRAM Read Cycle

  1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
  2. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device
  1. tCW is measured from CE1#s going low to the end of write.
  2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  3. tAS is measured from the address valid to the beginning of write.
  4. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 36. SRAM Write Cycle—WE# Control

66 Am42BDS640AG November 1, 2002

  1. tCW is measured from CE1#s going low to the end of write.
  2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  3. tAS is measured from the address valid to the beginning of write.
  4. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 37. SRAM Write Cycle—CE1#s Control

  1. UB#s and LB#s controlled.
  2. tCW is measured from CE1#s going low to the end of write.
  3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  4. tAS is measured from the address valid to the beginning of write.
  5. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 38. SRAM Write Cycle—UB#s and LB#s Control

68 Am42BDS640AG November 1, 2002

FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC , 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. FLASH LATCHUP CHARACTERISTICS Note:Includes all pins except VCC . Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Note:Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time (32 Kword or 8 Kword) 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 54 sec Word Program Time 11.5 210 µs Excludes system level overhead (Note 5) Accelerated Word Program Time 4 120 µs Chip Program Time (Note 3) 48 144 sec Accelerated Chip Program Time 16 48 sec Description Min Max Input voltage with respect to V SS on all pins except I/O pins (including OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 11 14 pF C OUT Output Capacitance V OUT = 0 12 16 pF C IN2 Control Pin Capacitance V IN = 0 14 16 pF C IN3 WP#/ACC Pin Capacitance V IN = 0 17 20 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

70 Am42BDS640AG November 1, 2002

FSC093—93-Ball Fine-Pitch Grid Array 8 x 11.6 mm 3187\\38.14A N/A 8.00 mm x 11.60 mm PACKAGE FSC 093 NOM. --- --- --- 1.40 --- 1.10 MAX. 8.00 BSC. 11.60 BSC. --- MIN. 1.00 0.25 8.80 BSC. 7.20 BSC. 0.35 0.40

0.40 BSC

A2,A3,A4,A5,A6,A7,A8,A9 C10,D1,D10,E1,E10,H1,H10 J1,J10,K1,K10 M2,M3,M4,M5,M6,M7,M8,M9 0.30

0.80 BSC

D JEDEC PACKAGE SYMBOL A MD E n NOTE DEPOPULATED SOLDER BALL MATRIX SIZE E DIRECTION MATRIX FOOTPRINT BALL PITCH

0.80 BSC BALL PITCH

NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTION OR OTHER MEANS. bO 93X b 0.20 C CC SIDE VIEW A 0.08

0.15 M C

0.08 INDEX MARK C0.15 (2X) (2X) C0.15 B AD E PIN A1 TOP VIEW CORNER LM eD CORNER 7SE ABDCEFHG JK eE SD BOTTOM VIEW PIN A17

November 1, 2002 Am42BDS640AG 71 PRELIMINARY REVISION SUMMARY Revision A (May 20, 2002) Initial release. Revision B (November 1, 2002) Global Renamed Non-Handshaking to Standard Handshaking. Renamed Handshaking Enabled to Reduced Wait-state Handshaking. Product Selector Guide Revised with renamed speed options and added Syn- chronous Access Time with Reduced Wait-state Handshaking. Added Asynchronous Access Time Revised with global changes Revised Valid Combinations with updated ordering information. Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.