AM386SX

AM386SX AMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 30

Technical content

Publication# 21020 Rev: A Amendment/0 Issue Date: April 1997 DISTINCTIVE CHARACTERISTICS ■ Member of the E86™ CPU series – 16-bit data bus – 24-bit address bus – 16-Mbyte address range – Long-term stable supply from AMD ■ 40-, 33- and 25-MHz operating speeds ■ Ideal for embedded applications – True Static design for low-power applications – 3–5 V operation (at 25 MHz) – Ideal for cost-sensitive designs – True DC (0 MHz) operation ■ Industry Standard Architecture – Supports world’s largest software base for x86 architectures – Wide range of chipsets and BIOS available – Fully compatible with all 386SX systems and software ■ System Management Mode (SMM) for system and power management (Am386SXLV only) – System Management Interrupt (SMI) for power management independent of processor operating mode and operating system – SMI coupled with I/O instruction break feature provides transparent power off and auto resume of peripherals which may not be “power aware” – SMI is non-maskable and has higher priority than Non-Maskable Interrupt (NMI) – Automatic save and restore of the microprocessor state ■ 100-lead Plastic Quad Flat Pack (PQFP) package ■ Extended temperature version available GENERAL DESCRIPTION The Am386®SX/SXL/SXLV microprocessors are low- cost, high-performance CPUs for embedded applica- tions. Embedded customers benefit from using the Am386 microprocessor in a number of ways. The Am386SX/SXL/SXLV microprocessors provide embedded customers access to very inexpensive pro- cessors and the highest performance of any 386SX available anywhere. The 16-bit data path allows for in- expensive memory design. Full static operation, cou- pled with 3-V supplies, benefit customers who desire low-power designs. Standby Mode allows the Am386SXL/SXLV microprocessors to be clocked down to 0 MHz (DC) and retain full register contents. A float pin places all outputs in a three-state mode to fa- cilitate board test and debug. Additionally, the Am386SXLV microprocessor comes with System Management Mode (SMM) for system and power management. SMI (System Management Inter- rupt) is a non-maskable, higher priority interrupt than NMI and has its own code space (1 Mbyte in Real Mode and 16 Mbyte in Protected Mode). SMI can be coupled with the I/O instruction break feature to imple- ment transparent power management of peripherals. SMM can be used by system designers to implement system and power management code independent of the operating system or the processor mode. Since the Am386SX/SXL/SXLV microprocessors are supported as an embedded product in the E86 family, customers can rely on long-term supply of product, and extended temperature products. In addition, customers have access to the largest se- lection of inexpensive development tools, compilers, and chipsets. A large number of PC operating systems and Real Time Operating Systems (RTOS) support the Am386SX/SXL/SXLV microprocessors. This means cheaper development costs, and improved time to mar- ket. The Am386SX/SXL/SXLV microprocessor is available in a small footprint 100-pin Plastic Quad Flat Pack (PQFP) package. Am386 ® SX/SXL/SXLV High-Performance, Low-Power, Embedded Microprocessors

2 Am386SX/SXL/SXLV Microprocessors Data Sheet

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. NG SX SPEED OPTION PROCESSOR TYPE SX = SX Processor SXL = SX Processor with Static Clock Implementation SXLV = SXL Processor with Low-Voltage and SMI TEMPERATURE RANGE NG=100-Lead Plastic Quad Flat Pack (PQB-100) PROCESSOR FAMILY PACKAGE TYPE Am386 Family –40 = 40 MHz –33 = 33 MHz –25 = 25 MHz 80386 Blank = Commercial (TCASE = 0°C to +100°C) I = Industrial (TCASE = –40°C to +100°C) I –40 Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations NG80386 SX –25 –33 –40 SXL –25 –33 SXLV –25 ING80386 SX –25

Am386SX/SXL/SXLV Microprocessors Data Sheet 3 BLOCK DIAGRAM FUNCTIONAL DESCRIPTION True Static Operation (Am386SXL/SXLV Only) The Am386SXL/SXLV microprocessor incorporates a true static design. Unlike dynamic circuit design, the Am386SXL/SXLV device eliminates the minimum op- erating frequency restriction. It may be clocked from its maximum speed all the way down to 0 MHz (DC). Sys- tem designers can use this feature to design portable applications with long battery life. Standby Mode (Am386SXL/SXLV Only) The true static design of the Am386SXL/SXLV micro- processor allows for a Standby Mode. At any operating speed, the microprocessor will retain its state (i.e., the contents of all its registers). By shutting off the clock completely, the device enters Standby Mode. Since power consumption is proportional to clock frequency, operating power consumption is reduced as the fre- quency is lowered. In Standby Mode, typical current draw is reduced to less than 20 microamps at DC. Not only does this feature save battery life, but it also sim- plifies the design of power-conscious portable applica- tions in the following ways. ■ Eliminates the need for software in BIOS to save and restore the contents of registers. ■ Allows simpler circuitry to control stopping of the clock since the system does not need to know the state of the processor. Lower Operating Icc (Am386SXL/SXLV Only) True static design also allows lower operating Icc when operating at any speed. Performance on Demand (Am386SXL/SXLV Only) The Am386SXL/SXLV microprocessor retains its state at any speed from 0 MHz (DC) to its maximum operat- ing speed. With this feature, system designers may vary the operating speed of the system to extend the battery life in portable systems. Pipeline/ Bus Size Control Effective Address Bus Effective Address Bus Dedicated ALU Bus Barrel Shifter, Adder Multiply/ Divide Register File Decode and Sequencing Control ROM Instruction Decoder 3-Decoded Instruction Queue Prefetcher/ Limit Checker Limit and Attribute PLA Descriptor Registers 3-Input Adder Page Cache Adder Request Prioritizer Address Driver Protection Test Unit ALU Control ALU Control Instruction Instruction Code Stream Segmentation Unit Paging Unit Bus Control HOLD, INTR, NMI, ERROR , BUSY , RESET, HLDA, FLT, SMI*, IIBEN* BHE , BLE, A23-A1 M/IO, D/C, W/R , LOCK, ADS , NA, READY , SMIADS *, SMIRDY * D15-D0 * – On Am386SXLV only

32 Bit

Code Fetch/Page Table Fetch Linear Address Bus Internal Control Bus

4 Am386SX/SXL/SXLV Microprocessors Data Sheet

es battery life while achieving optimal performance. and/or smaller batteries for portable applications. designs facilitate a reduction in the form factor. provides a less hostile environment for board design. Management Interrupt (SMI) and I/O instruction break. Protected, or Virtual 8086 modes). Figure 1. SMM Flow

Am386SX/SXL/SXLV Microprocessors Data Sheet 5 Description of SMM Operation (Am386SXLV Only) The execution of a System Management Interrupt has four distinct phases: the initiation of the interrupt via SMI , a processor state save, execution of the SMM in- terrupt code, and a processor state restore (to resume normal operation). Interrupt Initiation A System Management Interrupt is initiated by the driv- ing of a synchronous, active Low pulse on the SMI pin until the first SMIADS is asserted. This pulse period will ensure recognition of the interrupt. The CPU drives the SMI pin active after the completion of the current oper- ation (active bus cycle, instruction execution, or both). The active drive of the pin by the CPU is released at the end of the interrupt routine following the last register read of the saved state. The CPU drives SMI High for two CLK2 cycles prior to releasing the drive of SMI. An SMI cannot be masked off by the CPU, and it will al- ways be recognized by the CPU, regardless of operat- ing modes. This includes the Real, Protected, and Vir- tual-8086 modes of the processor. While the CPU is in SMM, a bus hold request via the HOLD pin is granted. The HLDA pin goes active after bus release and the SMIADS pin floats along with the other pins that normally float during a bus hold cycle. SMI does not float during a Bus Hold cycle. Processor State Save The first set of SMM bus transfer cycles after the CPU’s recognition of an active SMI is the processor saving its state to an external RAM array in a separate address space from main system memory. This is accom- plished by using the SMIADS and SMIRDY pins for ini- tiation and termination of bus cycles, instead of the ADS and READY pins. The 24-bit addresses to which the CPU saves its state are 60000h–600CBh and 60100h–60127h. These are fixed address locations for each register saved. To ensure valid operation, pipelining must be disabled while the processor is in SMM. There are 114 data transfer cycles. SMI Code Execution After the processor state is saved to the separate SMM memory space, the execution of the SMM interrupt rou- tine code begins. The processor enters Real mode, sets most of the register values to “reset” values (those values normally seen after a CPU reset), and begins fetching code from address FFFFF0h in the separate SMM memory space. Normally, the first thing the inter- rupt routine code does is a FAR JUMP to the Real mode entry point for the SMM interrupt routine, which is also in SMM memory space. Both INTR and NMI are disabled upon entry into SMM. The SMM code can be located anywhere within the 1-Mbyte Real mode address space, except for where the processor state is saved. I/O cycles, as a result of the IN, OUT, INS, and OUTS instructions, will go to the normal address space, utilizing the normal ADS and READY bus interface signals. This facilitates power management code manipulating system hardware reg- isters as needed through the standard I/O subsystem; a separate I/O space is not implemented. Processor State Restore (Resuming Normal Execution) Returning to normal code execution in the main system memory, including restoring the processor operating mode, is accomplished by executing a special code se- quence. This code invokes a restore CPU state opera- tion that reloads the CPU registers from the saved data in the RAM controlled by SMIADS and SMIRDY. The ES:EDI register pair must point to the physical ad- dress of the processor save state (6000h). In Real mode the address is calculated as ES•16 + EDI offset. The saved state should not cross a 64K boundary. The RES3 instruction (0F 07) should be executed to start the restore state operation. After completion of the re- store state operation, the SMI pin will be deactivated by the CPU and normal code execution will continue at the point where it left off before the SMI occurred. There are 114 data transfer cycles in the restore operation. Software Features (Am386SXLV Only) Several features of the SMI function provide support for special operations during the execution of the system’s software. These features involve the execution of re- served opcodes to induce specific SMI-related opera- tions. Software SMI Generation Besides hardware initiation of the SMI via the SMI pin, there is also a software-induced SMI mechanism. Gen- erating a soft SMI involves setting a control bit (Bit 12) in the Debug Control Register (DR7) and executing an SMI instruction (opcode F1h). The functional sequence of the software-based SMI is identical to the hardware-based SMI with the exception that the SMI pin is not initially driven active by an exter- nal source. Upon execution of a soft SMI opcode, the SMI pin is driven active (Low) by the processor before the save state operation begins. Memory Transfers to Main System Memory While executing an SMI routine, the interrupt code can initiate memory data reads and writes to the main sys- tem memory using the normal ADS and READY pins. This initiation is accomplished by using reserved op- codes that are special forms of the MOV instruction (called UMOV). The UMOV opcodes can move byte,

6 Am386SX/SXL/SXLV Microprocessors Data Sheet

word, or double word register operands to or from main system memory. Multiple data transfers using the nor- mal ADS and READY pins will occur if the operands are misaligned relative to the effective address used. The UMOV opcodes are 0F 10h, 0F 11h, 0F 12h, and 0F 13h. The UMOV instruction can use any of the 386 addressing modes, as specified in the ModR/M byte of the opcode. Note that the 16- and 32-bit versions are the same opcodes with the exception of the 66h oper- and size prefix. I/O Instruction Break (Am386SXLV Only) The Am386SXLV microprocessor has an I/O instruc- tion break feature that allows the system logic to imple- ment I/O trapping for peripheral devices. To enable the I/O Instruction break feature, IIBEN must first be as- serted active Low. On detecting an I/O instruction, the processor prevents the execution unit from executing further instructions until READY is driven active Low by the system. Once READY is driven active, the execu- tion unit either immediately responds to any active in- terrupt request or continues executing instructions fol- lowing the I/O instruction that caused the break. The I/O instruction break feature can be used to allow system logic to implement I/O trapping for peripheral devices. On sensing an I/O instruction, the system drives the SMI pin active before driving READY active. This ensures that the interrupt service routine is exe- cuted immediately following the I/O instruction that caused the break. (If the I/O instruction break feature is not enabled via IIBEN , several instructions could exe- cute before the SMI service routine is executed.) The SMI service routine can access the peripheral for which SMI was asserted and modify its state.The SMI service routine normally returns to the instruction fol- lowing the I/O instruction that caused the break. By modifying the saved state instruction pointer, the rou- tine can choose to return to the I/O instruction that caused the break and re-execute that instruction. The default is to return to the following instruction (except for REP I/O string instruction). To re-execute the I/O in- struction that caused the break, the SMI service routine must copy the I/O instruction pointer over the default pointer. This feature is particularly useful when an ap- plication program requests an access to a peripheral that has been powered down. The SMI service routine can restore power to the peripheral and initiate a re-ex- ecution sequence transparent to the application pro- gram. This re-execution feature should only be used if the SMI is in response to an I/O trap with IIBEN active. Note that the I/O instruction break feature is not en- abled for memory mapped I/O devices or for coproces- sor bus cycles even if IIBEN is active. I/O Instruction Break Timing The I/O Instruction Break feature requires that SMI be sampled active (Low) by the processor at least three CLK2 edges before the CLK2 edge that ends the I/O cycle with an active READY signal. This timing applies for both pipelined and non-pipelined cycles. If this tim- ing constraint is not met, additional instructions may be executed by the internal execution unit prior to entering SMM. Depending on the state of the prefetch queue at the time the SMI is asserted, instruction fetch cycles may occur on the normal ADS interface before the SMM save state process begins with the assertion of SMIADS . However, this fetched code will not be exe- cuted.

Am386SX/SXL/SXLV Microprocessors Data Sheet 7 CONNECTION DIAGRAM 100-Lead Plastic Quad Flat Pack (PQFP) Package—Top Side View ADS 16

74 A19

75 A20

73 A18

72 A17

71 V CC

70 A16

69 VCC

68 VSS

67 VSS

66 A15

65 A14

64 A13

63 VSS

62 A12

61 A11

60 A10

57 V CC

*IIBEN 29 *SMIRDY 30 *SMIADS 31 RESET 33 BUSY 34 ERROR 36 PEREQ 37 NMI 38 INTR 40 *SMI 43 NC 44 NC 45 NC 46 NC 47 D1100 D299 D396 D495 D594 D693 D792 D890 D989 D1088 D1187 D1286 D1383 D1482 D1581 A2380 A2279 A2176 Notes: Pin 1 is marked for orientation NC = Not connected; connection of an NC pin may cause a malfunction or incompatibility with future shippings of the Am386SX/SXL/SXLV microprocessors * = On Am386SXLV only; NC on Am386SX/SXL VCC VCC VCC VCC VSS VSS VSS VSS VSS VCC VCC VCC VSS VSS VSS Top Side View

8 Am386SX/SXL/SXLV Microprocessors Data Sheet

100-Lead Plastic Quad Flat Pack (PQFP) Package—Pin Side View 13 63 100 NC LOCK FLT IIBEN* SMIRDY * SMIADS * RESET BUSY ERROR PEREQ NMI INTR SMI NC NC NC NC VCC VCC VCC VCC VSS VSS VSS VSS ADS VSS HLDA HOLD VSS NA READY VCC VCC VCC VSS VSS VSS VSS CLK2 BLE BHE NC VCC VSS M/IO D/C W/R D10 D11 D12 D13 D14 D15 A23 A22 A21 V SS VCC VCC VCC VSS VSS VSS A19 A20 A18 A17 VCC A16 VCC VSS VSS A15 A14 A13 VSS A12 A11 A10 VCC Notes: Pin 1 is marked for orientation NC = Not connected; connection of an NC pin may cause a malfunction or incompatibility with future shippings of the Am386SX/SXL/SXLV microprocessors * = On Am386SXLV only; NC on Am386SX/SXL Pin Side View

Am386SX/SXL/SXLV Microprocessors Data Sheet 9 PIN DESIGNATION TABLE (Sorted by Functional Grouping) PIN DESIGNATION TABLE (Sorted by Pin Number) Address Data Control NC VCC VSS A10 A11 A12 A13 A14 A15 A16 A17 A18A18 A20 A21 A22 A23 D10 D11 D12 D13 D14 D15 100 ADS BHE BLE BUSY CLK2 ERROR HLDA HOLD INTR LOCK NA NMI PEREQ READY RESET D/C M/IO FLT SMI* SMIADS * SMIRDY * IIBEN*2 9 W/R * On Am386SXLV only; NC on Am386SX/SXL A19 74 D01 Pin No. Pin Name Pin No. Pin Name HLDA HOLD NA READY CLK2 ADS BLE BHE NC LOCK NC IIBEN* SMIRDY * SMIADS * RESET BUSY ERROR PEREQ NMI INTR Pin No. Pin Name SMI* NC NC NC NC A10 Pin No. Pin Name A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 Pin No. Pin Name D15 100 D14 D13 D12 D11 D10 VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VCC M/IO D/C W/R VSS VCC VCC VSS VSS VCC VSS VSS VCC VSS VSS VSS VCC VCC VCC VSS VCC VSS FLT * On Am386SXLV only; NC on Am386SX/SXL

10 Am386SX/SXL/SXLV Microprocessors Data Sheet

A23–A1 Address Bus (Outputs) Outputs physical memory or port I/O addresses. ADS Address Status (Active Low; Output) Indicates that a valid bus cycle definition and address (W/R, D/C, M/IO, BHE, BLE, and A23–A1) are being driven at the Am386SX/SXL/SXLV microprocessor pins. Bus cycles initiated by ADS must be terminated by READY . BHE , BLE Byte Enables (Active Low; Outputs) Indicate which data bytes of the data bus take part in a bus cycle. BUSY Busy (Active Low; Input) Signals a busy condition from a processor extension. BUSY has an internal pull-up resistor. CLK2 CLK2 (Input) Provides the fundamental timing for the Am386SX/ SXL/SXLV microprocessor. D15–D0 Data Bus (Inputs/Outputs) Inputs data during memory, I/O, and interrupt acknowl- edge read cycles; outputs data during memory and I/O write cycles. D/C Data/Control (Output) A bus cycle definition pin that distinguishes data cy- cles, either memory or I/O, from control cycles which are interrupt acknowledge, halt, and code fetch. ERROR Error (Active Low; Input) Signals an error condition from a processor extension. ERROR has an internal pull-up resistor. FLT Float (Active Low; Input) An input which forces all bidirectional and output sig- nals, including HLDA, to the three-state condition. FLT has an internal pull-up resistor. The pin, if not used, should be disconnected. HLDA Bus Hold Acknowledge (Active High; Output) Output indicates that the Am386SX/SXL/SXLV micro- processor has surrendered control of its logical bus to another bus master. HOLD Bus Hold Request (Active High; Input) Input allows another bus master to request control of the local bus. IIBEN (Am386SXLV Only) I/O Instruction Break Enable (Active Low; Input) Enables the I/O instruction break feature. IIBEN has a dynamic internal pull-up resistor. The IIBEN pull-up is active during RESET and whenever the signal is not driven active Low by the system. INTR Interrupt Request (Active High; Input) A maskable input that signals the Am386SX/SXL/ SXLV microprocessor to suspend execution of the cur- rent program and execute an interrupt acknowledge function. LOCK Bus Lock (Active Low; Output) A bus cycle definition pin that indicates that other sys- tem bus masters are not to gain control of the system bus while it is active. M/IO Memory/IO (Output) A bus cycle definition pin that distinguishes memory cy- cles from input/output cycles. NA Next Address (Active Low; Input) Used to request address pipelining. NC No Connect Should always be left unconnected. Connection of an NC pin may cause the processor to malfunction or be incompatible with future steppings of the Am386SX/ SXL/SXLV microprocessor. NMI Non-Maskable Interrupt Request (Active High; Input) A non-maskable input that signals to the Am386SX/ SXL/SXLV microprocessor to suspend execution of the current program and execute an interrupt acknowledge function. PEREQ Processor Extension Request (Active High; Input) Indicates that the processor has data to be transferred by the Am386SX/SXL/SXLV microprocessor. PEREQ has an internal pull-down resistor.

Am386SX/SXL/SXLV Microprocessors Data Sheet 11 READY Bus Ready (Active Low; Input) Terminates the bus cycle initiated by ADS. RESET Reset (Active High; Input) Suspends any operation in progress and places the Am386SX/SXL/SXLV microprocessor in a known reset state. SMI (Am386SXLV Only) System Management Interrupt (Active Low; I/O) A non-maskable interrupt pin that signals to the Am386SXLV microprocessor to suspend execution and enter System Management Mode. SMI has an in- ternal pull-up resistor. SMI has a dynamic internal pull-up resistor that is disabled when the processor is in SMM. SMI is not three-stated during Hold Acknowl- edge bus cycles. SMIADS (Am386SXLV Only) SMI Address Status (Active Low; Output) When active, this pin indicates that a valid bus cycle definition and address (W/R, D/C, M/IO, BHE, BLE, and A23–A1) are being driven at the Am386SXLV mi- croprocessor pins while in the System Management mode. Bus cycles initiated by SMIADS must be termi- nated by SMIRDY. SMIRDY (Am386SXLV Only) SMI Ready (Active Low; Input) This input terminates the current bus cycle to the SMM mode address space in the same manner the READY pin does for the normal mode address space. SMIRDY has an internal pull-up resistor. READY and SMIRDY must not be tied together. VCC System Power (Input) Provides the 5 V nominal DC supply input. VSS System Ground (Input) Provides the 0-V connection from which all inputs and outputs are measured. W/R Write/Read (Output) A bus cycle definition pin that distinguishes write cycles from read cycles. LOGIC SYMBOL HOLD HLDA ERROR NMI LOCK NA INTR PEREQ READY RESET ADS CLK2 D/C D15–D0 BLE , BHE A23–A1 M/IO Bus Arbitration Control W/R BUSY Data Bus Interrupt Control Math Coprocessor Control Bus Cycle Definition Bus Cycle Control Address Bus 2X Clock 16305C–003 FLT Float SMIRDY System Management Control* Mode SMIADS SMI IIBEN Am386SXLV Microprocessor *On Am386SXLV only

12 Am386SX/SXL/SXLV Microprocessors Data Sheet

Ambient Temperature Under Bias .... –65°C to +125°C Stresses above those listed may cause permanent damage to the device. Functionality at or above these limits is not implied. Exposure to ABSOLUTE MAXI- MUM RATING conditions for extended periods may af- fect device reliability. OPERATING RANGES Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges for 25 MHz Am386SXLV Vcc=3.0 V to 3.6 V; TCASE =0°C to +100°C VIH Input High Voltage 2.0 V CC +0.3 V VIL Input Low Voltage (Note 1) –0.3 +0.8 V C CLK CLK2 Capacitance F C = 1 MHz (Note 4) 20 pF C OUT Output Capacitance F C = 1 MHz (Note 4) 12 pF C IN Input or I/O Capacitance F C = 1 MHz (Note 4) 10 pF ICCSB Standby Current (Note 8) I CCSB Typ = 10µA1 5 0 µA VOH Output High Voltage IOH = 0.1 mA:A23–A1, D15–D0 (Note 5) V CC –0.2 V I OH = 0.1 mA: BHE, BLE, W/R, D/C, SMIADS, (Note 6) V CC –0.2 V LOCK , ADS, M/IO, HLDA, SMI IOH = 0.5 mA: A23–A1, D15–D0 V CC –0.45 V IOH = 0.5 mA: BHE, BLE, W/R, D/C, SMIADS,V CC –0.45 V LOCK , ADS, M/IO, HLDA, SMI ILI Input Leakage Current (All pins except 0 V ≤ VIN ≤ VCC PEREQ, BUSY, ERROR , SMI, SMIRDY, (Note 7) ±10 µA FLT, IIBEN) VOL Output Low Voltage IOL = 0.5 mA:A23–A1, D15–D0 (Note 5) 0.2 V IOL = 0.5 mA: BHE, BLE, W/R, D/C, SMIADS,0 . 2 V M/IO, LOCK, ADS, HLDA, SMI IOL = 2 mA: A23–A1, D15–D0 0.45 V IOL = 2.5 mA: BHE, BLE, W/R, D/C, SMIADS,0 . 4 5 V LOCK , ADS, M/IO, HLDA, SMI Symbol Parameter Description Notes Min Max Unit VILC CLK2 Input Low Voltage (Note 1) –0.3 +0.8 V VIHC CLK2 Input High Voltage 2.4 V CC +0.3 V IIH Input Leakage Current V IH = VCC –0.1 V 300 µA (PEREQ pin) V IH = 2.4 V (Note 2) 200 µA IIL Input Leakage Current V IL = 0.1 V –300 µA (BUSY, ERROR , SMI, SMIRDY, FLT, IIBEN) V IL = 0.45 V (Note 3) –200 µA ILO Output Leakage Current 0.1 V ≤ VOUT ≤ VCC +15 µA ICC Supply Current (Note 8) V CC = 3.3 V V CC = 3.6 V CLK2 = 50 MHz: Oper. Freq. 25 MHz I CC Typ = 95 115 mA Final Notes: 1. The Min value, –0.3, is not 100% tested. 2. PEREQ input has an internal pull-down resistor. 3. BUSY , ERROR , FLT, SMI, IIBEN, and SMIRDY inputs each have an internal pull-up resistor. 4. Not 100% tested. 5. Outputs are CMOS and will pull rail-to-rail if the load is not resistive. 6. V OH SMI only valid on SMI output when exiting SMM for two CLK2 periods. 7. SMI and IIBEN leakage Low will be ILI when pull-up is inactive and IIL when pull-up is active. 8. Inputs at rails (VCC or VSS ).

Am386SX/SXL/SXLV Microprocessors Data Sheet 13 ABSOLUTE MAXIMUM RATINGS Ambient Temperature under Bias .... –65°C to +125°C Stresses above those listed may cause permanent damage to the device. Functionality at or above these limits is not implied. Exposure to ABSOLUTE MAXI- MUM RATING conditions for extended periods may af- fect device reliability. OPERATING RANGES Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges 25 and 33 MHz: Vcc = 5 V ± 10%; TCASE = 0°C to +100°C (commercial); TCASE = –40°C to +100°C (industrial)

40 MHz: Vcc = 5 V ± 5%; TCASE = 0°C to +100°C

ICC Supply Current (Note 8) V CC Typ = 5.0 V V CC = 5.5 V CLK2 = 50 MHz: Oper. Freq. 25 MHz I CC Typ = 160 190 mA CLK2 = 66 MHz: Oper. Freq. 33 MHz ICC Typ = 210 245 mA CLK2 = 80 MHz: Oper. Freq. 40 MHz ICC Typ = 255 295 mA C IN Input or I/O Capacitance F C = 1 MHz (Note 4) 10 pF C CLK CLK2 Capacitance F C = 1 MHz (Note 4) 20 pF C OUT Output or I/O Capacitance F C = 1 MHz (Note 4) 12 pF ILI Input Leakage Current (All pins except 0 V ≤ VIN ≤ VCC PEREQ, BUSY, ERROR , SMI*, SMIRDY*, (Note 7) ±15 µA FLT, and IIBEN*) VOL Output Low Voltage IOL = 4 mA: A23 –A1, D15–D0 (Note 5) 0.45 V IOL = 5 mA: BHE , BLE,W/R, D/C, SMIADS*, 0.45 V M/IO, LOCK, ADS, HLDA, SMI* VIL Input Low Voltage (Note 1) –0.3 +0.8 V Symbol Parameter Description Notes Min Max Unit VIH Input High Voltage 2.0 V CC +0.3 V VILC CLK2 Input Low Voltage (Note 1) –0.3 +0.8 V VIHC CLK2 Input High Voltage 2.7 V CC +0.3 V IIH Input Leakage Current (PEREQ pin) V IH = 2.4 V (Note 2) 200 µA IIL Input Leakage Current (BUSY , ERROR , SMI*, SMIRDY*, FLT, IIBEN*) VIL = 0.45 V (Note 3) –400 µA ILO Output Leakage Current: Am386SX/SXL 0.1 V ≤ VOUT ≤ VCC ±15 µA Am386SXLV 0.45 V ≤ VOUT ≤ VCC ±15 µA ICCSB Standby Current (Note 8) I CCSB Typ = 20 µA 1 5 0 µA Notes: * On Am386SXLV only 1. The Min value, –0.3, is not 100% tested. 2. PEREQ input has an internal pull-down resistor. 3. BUSY , ERROR , FLT, SMI*, IIBEN*, and SMIRDY* inputs each have an internal pull-up resistor. 4. Not 100% tested. 5. Outputs are CMOS and will pull rail-to-rail if the load is not resistive. 6. V OH SMI only valid on SMI output when exiting SMM for two CLK2 periods (on Am386SXLV only). 7. SMI and IIBEN leakage Low will be ILI when pull-up is inactive and IIL when pull-up is active (on Am386SXLV only). 8. Inputs at rails (VCC or VSS ), outputs unloaded, PEREQ Low, ERROR High, BUSY High, and FLT High. Final VOH Output High Voltage IOH = 1.0 mA: A23–A1, D15–D0 (Note 5) 2.4 V IOH = 0.2 mA: A23–A1, D15–D0 V CC –0.5 V I OH = 0.9 mA: BHE , BLE, W/R, D/C, SMIADS*, (Note 6*) 2.4 V LOCK , ADS, M/IO, HLDA, SMI* IOH = 0.18 mA: BHE, BLE, W/R, D/C, SMIADS*, V CC –0.5 V LOCK , ADS, M/IO, HLDA, SMI*

14 Am386SX/SXL/SXLV Microprocessors Data Sheet

the CLK2 rising edge crossing the 2.0-V level. Figure 2. Inputs must be driven to the voltage levels in- input signal must be stable for correct operation. Figure 2. Drive Levels and Measurement Points for Switching Characteristics

2 VCLK2

Am386SX/SXL/SXLV Microprocessors Data Sheet 15 SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges at 25 MHz VCC = 5.0 V ± 10%; TCASE = 0°C to +100°C (Commercial); TCASE = –40°C to +100°C (Industrial) VCC = 3.0 V–5.5 V; TCASE = 0°C to +100°C (Am386SXLV only) Symbol Parameter Description Notes Ref. Figures Final UnitMin Max Operating Frequency: Am386SX CPU Am386SXL/SXLV CPU Half CLK2 freq. Half CLK2 freq.

25 MHz

1 CLK2 Period 3, 4 20 ns

2 CLK2 High Time: Am386SXLV CPU at V IHC 34 n s

2a CLK2 High Time: Am386SX/SXL CPU at 2 V 4 7 ns 2b CLK2 High Time: Am386SX/SXL CPU at (V CC –0.8 V) 4 4 ns 3 CLK2 Low Time: Am386SXLV CPU at 0.8 V 3 5 ns 3a CLK2 Low Time: Am386SX/SXL CPU at 2 V 4 7 ns 3b CLK2 Low Time: Am386SX/SXL CPU at 0.8 V 4 5 ns

4 CLK2 Fall Time: Am386SX/SXL CPU

(VCC –0.8 V) to 0.8 V (Note 3) 2.4 V to 0.8 V (Note 3) 3 7n s

5 CLK2 Rise Time: Am386SX/SXL CPU

0.8 V to 2.4 V (Note 3) 0.8 V to (VCC –0.8 V) (Note 3) 3 7n s

6 A23–A1 Valid Delay C L = 50 pF 8 4 17 ns

7 A23–A1 Float Delay (Note 1) 15 4 30 ns

, BLE, LOCK Valid Delay C L = 50 pF 8 4 17 ns 9B H E , BLE, LOCK Float Delay (Note 1) 15 4 30 ns

10 M/IO , D/C, W/R, ADS Valid Delay C L = 50 pF 8 4 17 ns

10s SMIADS Valid Delay C L = 50 pF (Note 5) 8 4 25 ns

11 W/R , M/IO, D/C, ADS Float Delay (Note 1) 15, 18 4 30 ns

11s SMIADS Float Delay (Notes 1, 5) 15 4 30 ns

12 D15–D0 Write Data Valid Delay C L = 50 pF 8, 9 7 23 ns

12a D15–D0 Write Data Hold Time C L = 50 pF 10 2 ns

13 D15–D0 Write Data Float Delay (Note 1) 15 4 22 ns

14 HLDA Valid Delay C

L = 50 pF 8 4 22 ns 14f HLDA Float Delay: Am386SX/SXL Am386SXLV (Notes 1, 4) 15, 16 4 30 ns

15 NA Setup Time 75 n s

16 NA Hold Time 73 n s

19 READY Setup Time 7 9 ns

19s SMIRDY Setup Time (Note 5) 7 9 ns

20 READY Hold Time 7 4 ns

20s SMIRDY Hold Time (Note 5) 7 4 ns

21 D15–D0 Read Data Setup Time 7 7 ns

22 D15–D0 Read Data Hold Time 7 5 ns

23 HOLD Setup Time 7 9 ns

24 HOLD Hold Time 7 3 ns

25 RESET Setup Time 17 8 ns

26 RESET Hold Time 17 3 ns

27 NMI, INTR Setup Time (Note 2) 7 6 ns

Setup Time (Note 5) 7 6 ns

28 NMI, INTR Hold Time (Note 2) 7 6 ns

28s SMI Hold Time (Note 5) 7 4 ns

29 PEREQ, ERROR , BUSY, FLT, IIBEN5 Setup Time (Note 2) 7 6 ns

30 PEREQ, ERROR , BUSY, FLT, IIBEN5 Hold Time (Note 2) 7 5 ns

31 SMI Valid Delay (Note 5) 8, 15 4 22 ns

32 SMI Float Delay (Notes 1, 4, 5) 16 4 30 ns

Notes: 1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested. 2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period. 3. Rise and Fall times are not tested. They are guaranteed by design characterization. 4. Only during FLT assertion. 5. On Am386SXLV only.

16 Am386SX/SXL/SXLV Microprocessors Data Sheet

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 33 MHz VCC = 5.0 V ± 10%; TCASE = 0°C to +100°C Symbol Parameter Description Notes Ref. Figures Final UnitMin Max Operating Frequency: Am386SX CPU Am386SXL CPU Half CLK2 freq. Half CLK2 freq.

33 MHz

1 CLK2 Period 41 5 n s

2a CLK2 High Time at 2 V 4 6.25 ns 2b CLK2 High Time at 3.7 V 4 4 ns 3a CLK2 Low Time at 2 V 4 6.25 ns 3b CLK2 Low Time at 0.8 V 4 4.5 ns 4 CLK2 Fall Time 3.7 V to 0.8 V (Note 3) 4 4 ns 5 CLK2 Rise Time 0.8 V to 3.7 V (Note 3) 4 4 ns

6 A23–A1 Valid Delay C

L = 50 pF 8 4 15 ns

7 A23–A1 Float Delay (Note 1) 15 4 20 ns

8B H E , BLE, LOCK Valid Delay C L = 50 pF 8 4 15 ns 9B H E , BLE, LOCK Float Delay (Note 1) 15 4 20 ns

10 M/IO , D/C, W/R, ADS Valid Delay C L = 50 pF 8 4 15 ns

11 W/R , M/IO, D/C, ADS Float Delay (Note 1) 15 4 20 ns

12 D15–D0 Write Data Valid Delay C L = 50 pF 8 7 23 ns

12a D15–D0 Write Data Hold Time C L = 50 pF 10 2 ns

13 D15–D0 Write Data Float Delay (Note 1) 15 4 17 ns

L = 50 pF 8 4 20 ns 14f HLDA Float Delay 15 4 20 ns

16 NA Hold Time 72 n s

19 READY Setup Time 7 7 ns

21 D15–D0 Read Data Setup Time 7 5 ns

22 D15–D0 Read Data Hold Time 7 3 ns

24 HOLD Hold Time 7 2 ns

25 RESET Setup Time 17 5 ns

26 RESET Hold Time 17 2 ns

27 NMI, INTR Setup Time (Note 2) 7 5 ns

28 NMI, INTR Hold Time (Note 2) 7 5 ns

29 PEREQ, ERROR

, BUSY Setup Time (Note 2) 7 5 ns

30 PEREQ, ERROR , BUSY Hold Time (Note 2) 7 4 ns

Notes: 1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested. 2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period. 3. Rise and Fall times are not tested. They are guaranteed by design characterization. 4. Min time is not 100% tested.

Am386SX/SXL/SXLV Microprocessors Data Sheet 17 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 40 MHz VCC = 5.0 V ± 5%; TCASE = 0°C to +100°C (Am386SX only) Symbol Parameter Description Notes Ref. Figures Final UnitMin Max Operating Frequency Half CLK2 frequency 2 40 MHz 1 CLK2 Period 5 12.5 250 ns 2 CLK2 High Time at 2.7 V 5 4.5 ns 3 CLK2 Low Time at 0.8 V 5 4.5 ns 4 CLK2 Fall Time 2.7 V to 0.8 V (Note 3) 5 4 ns 5 CLK2 Rise Time 0.8 V to 2.7 V (Note 3) 5 4 ns L = 50 pF 8 4 13 ns , BLE, LOCK Valid Delay C L = 50 pF 8 4 13 ns 9B H E , BLE, LOCK Float Delay (Note 1) 15 4 20 ns

10 M/IO , D/C, W/R, ADS Valid Delay C L = 50 pF 8 4 13 ns

12 D15–D0 Write Data Valid Delay C L = 50 pF (Note 4) 8 7 18 ns

12a D15–D0 Write Data Hold Time C L = 50 pF 10 2 ns L = 50 pF 15 4 17 ns 14f HLDA Float Delay 15 4 17 ns

21 D15–D0 Read Data Setup Time 7 4 ns

23 HOLD Setup Time 7 4 ns

25 RESET Setup Time 17 4 ns

, BUSY, FLT Setup Time (Note 2) 7 5 ns

30 PEREQ, ERROR , BUSY, FLT Hold Time (Note 2) 7 4 ns

Notes: 1. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested. 2. These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period. 3. Rise and Fall times are not tested. They are guaranteed by design characterization. 4. Min time is not 100% tested.

18 Am386SX/SXL/SXLV Microprocessors Data Sheet

Figure 3. CLK2 Timing (Am386SXLV 25 MHz) Figure 4. CLK2 Timing (Am386SX/SXL 25 and 33 MHz) Figure 5. CLK2 Timing (Am386SX 40 MHz) Figure 6. AC Test Circuit

Figure 7. Input Setup and Hold Timing

20 Am386SX/SXL/SXLV Microprocessors Data Sheet

Figure 8. Output Valid Delay Timing

22 Am386SX/SXL/SXLV Microprocessors Data Sheet

1. BUSY should be held stable for eight CLK2 periods before and after the CLK2 period in which the RESET falling edge
2. If self-test is requested, the Am386SXLV microprocessor outputs remain in their reset state as shown here.

Figure 11. Bus Activity from Reset Until First Code Fetch (Am386SXLV Only)

24 Am386SX/SXL/SXLV Microprocessors Data Sheet

**Figure 15. Output Float Delay and HLDA and SMI* Valid Delay Timing**

26 Am386SX/SXL/SXLV Microprocessors Data Sheet

This graph will not be linear outside the CL range shown. Figure 18. Typical Output Valid Delay Versus Load Capacitance Figure 19. Typical Output Valid Delay Versus Load Capacitance This graph will not be linear outside the CL range shown.

28 Am386SX/SXL/SXLV Microprocessors Data Sheet

DIFFERENCES BETWEEN THE Am386SX/SXL/SXLV AND Am386DX/DXL CPU The following are the major differences between the Am386SX/SXL/SXLV and the Am386DX/DXL CPU. For brevity, throughout this section the Am386SX/SXL/ SXLV CPU is referred to as the SX CPU, and the Am386DX/DXL CPU is referred to as the DX CPU. ■ The SX CPU generates byte selects on BHE and BLE (like the 8086 and 80286) to distinguish the upper and lower bytes on its 16-bit data bus. The DX CPU uses four byte selects, BE3 –BE0 , to distin- guish between the different bytes on its 32-bit bus. ■ The SX CPU has no bus sizing option. The DX CPU can select between either a 32-bit bus or a 16-bit bus by use of the BS16 input. The SX CPU has a 16-bit bus size. ■ The NA pin operation in the SX CPU is identical to that of the NA pin on the DX CPU with one excep- tion: the DX CPU NA pin cannot be activated on 16- bit bus cycles (where BS16 is Low in the DX CPU case), whereas NA can be activated on any SX CPU bus cycle. ■ The contents of all SX CPU registers at reset are identical to the contents of the DX CPU registers at reset, except for the DX register. The DX register contains a component-stepping identifier at reset, that is: – In the DX CPU, after reset: DH = 3 indicates DX CPU DI = revision number – In the SX CPU, after reset: DH = 23H indicates SX CPU DL = revision number ■ The DX CPU uses A31 and M/IO as selects for the math coprocessor. The SX CPU uses A23 and M/IO as selects. ■ The DX CPU prefetch unit fetches code in four-byte units. The SX CPU prefetch unit reads two bytes as one unit (like the 80286). In BS16 mode, the DX CPU takes two consecutive bus cycles to complete a prefetch request. If there is a data read or write re- quest after the prefetch starts, the DX CPU will fetch all four bytes before addressing the new request. ■ Both the DX CPU and SX CPU have the same log- ical address space. The only difference is that the DX CPU has a 32-bit physical address space and the SX CPU has a 24-bit physical address space. The SX CPU has a physical memory address space of up to 16 Mbyte instead of the 4 Gbyte available to the DX CPU. Therefore, in SX CPU systems, the operating system must be aware of this physical memory limit and should allocate memory for appli- cations programs within this limit. If a DX CPU sys- tem uses only the lower 16 Mbyte of physical address, then there will be no extra effort required to migrate DX CPU software to the SX CPU. Any application which uses more than 16 Mbyte of memory can run on the SX CPU, if the operating system utilizes the SX CPU’s paging mechanism. In spite of this difference in physical address space, the SX CPU and the DX CPU can run the same op- erating systems and applications within their re- spective physical memory constraints. ■ The SX CPU has an input called FLT , which three- states all bi-directional and output pins, including HLDA, when asserted. It is used with ON-Circuit Emulation (ONCE).

In the 100-lead PQFP package, θJA=45.0 and θJC=11.0.

18 VSS pins separately feed functional units of the

the system (or temporarily removed from its socket).

40 INTR

38 NMI

through a pull-up in the range of 20 Kohms to VCC . Table 1. Recommended Resistor Pull-Ups to VCC

16 ADS 20 Kohms ± 10% Lightly pull ADS inactive during Am386SX/SXL/SXLV

CPU Hold Acknowledge states.

26 LOCK 20 Kohms ± 10% Lightly pull LOCK inactive during Am386SX/SXL/

SXLV CPU Hold Acknowledge states.

30 Am386SX/SXL/SXLV Microprocessors Data Sheet

PQB 100 (Plastic Quad Flat Pack, Trimmed and Formed) Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 is a registered trademark; and E86 is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Pin 100 Pin 75 Pin 50 Pin 1 I.D. 16-038-PQB PQB100 DB90 3-6-97 lv TOP VIEW 0.897 0.903 0.747 0.753 0.875 0.885 0.897 0.903 0.008 0.012 Pin 25 0.875 0.885 0.747 0.753

0.025 BASIC

0.160 0.180

0.60 REF

0.130 0.150 0.020 0.040 SEATING PLANE END VIEW 0°≤0≤8° GAGE PLANE

0.065 REF

7° TYP. 0° MIN

0.045 X45° CHAMFER

0.015 0.008 R

0.010 MIN

0.036 0.046 7° TYP. 0.010