AM29114 AMD | Alldatasheet
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Real-Time Interrupt Controller ADVANCE INFORMATION DISTINCTIVE CHARACTERISTICS. 3 © Real-Time Interrupt Servicing © Vector Outputs = ‘Supports interrupts at microinstruction boundaries, mak- Output is binary code for the highest priority un-masked | & ing interrupt responses virtually instantaneous. interrupt request. © Expandable © On-Chip Prioritization Cascadable to accept any number of interrupt inputs Only interrupts having higher priority than the highest © Accepts 8 Interrupt Inputs interrupt in service are allowed. Interrupt request signals may be levels or pulses © 8.Bit Mask Register Allows particular interrupt inputs to be temporarily dis- abled, GENERAL DESCRIPTION The Am29114 is a high-performance 8-bit vectored priority The Am29114 is designed to operate in 10 MHz micropro- > interrupt controller intended for use in very high-speed grammed systems. microprogrammed machines. Its architecture and instruc- tion set are optimized to take full advantage of the real-time The Am29114 features 16 microinstructions which allow interrupt capabilites of state-of-the-art sequencers such a8 designers to read from and write to key registers tor | OD the Am29112, maximum control flexibility bao } BLOCK DIAGRAM 8 “ -| ° [=| 4 Y fo) bos O T pos Ce ae al. f>—2- 1 vecron om a OEE iy =| ” poy on poe o> a &y | c | eee! £ a oO aooorr | mt ton 004694 / pop you ovata tan produe AMO re 7 Order #051908 G Yb1Y 1 Aud
RELATED PRODUCTS CONNECTION DIAGRAM [Part No, [Description uch 7B 8-Bit High-Performance Microprogram reser 2 3B ‘Sequencer og: ap ‘Am29116 16-Bit Bipolar Microprocessor mann § sae ‘am29117 Two-Port Am29116 vas ab, ‘Am29118 8-Bit Bidirectional 1/O Port/Accumulator voeio seo ‘Am29PL141 | Fuse-Programmable Controller anne 2ho, : ‘onoi3 2B ‘Am2950A/ | 8-Bit Bidirectional 1/0 Port casom Sf" oae BIA/52A/53A Sasoure Eis ate wr Ei casins Am2925 ‘System Clock Generator and Driver way 2B cosine wh 5 wr, | Status and Shift Control Unit mete 2B ie wre FAINT, Am2940 DMA Address Generator = ape Am2942 Programmable Timer/Counter/DMA ©D006010 LOGIC SYMBOL 6 dnt. ve 7 3 gin i ir: . 3S nr ve ° Fi int: 2 mt. ven p> ‘ bo qin MINTR > 12 a % eB ns EA & Fe 8 Ei 8 PY Bh magia eH 3 a= 8 ES o Bs te 2 ‘ Ft ‘ ” bs x6 den 2 cs x san aso ‘ B neser ‘ o L.so01680
ORDERING INFORMATION
[AMD products are available in several packages and operating ranges. The order number is formed by a combination of the following: Device number, speed option (if applicable), package type, operating range and screening option it desired). ‘Am20114 2 ¢ i Valid Combinations Optional Processing Blank = Standard Processing B= Burnin Temperature Range ‘C= Commercial (0 to +70°C) Package Valid Combinations = 40-Pin Sidebrazed Hermetéa DIP (50-040) Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released valid combinations, ‘AMD Device Type and to obtain additional data on AMD's standard Real-Time interrupt Controlter military grade products.
PIN DESCRIPTION | Do-D7 Data Input/Output Lines. VEN Vector Enable. Used to transter information between the system data bus and Qutput of vector-enable fip-lop. The vector-enable flip-flop is the mask, interrupt and in-service registers of the Am29114. cleared (VEN high) on the next active clock edge. when INTo- INT; Interrupt Inputs. CASIN2 is high. When CASIN2 is low, the vector-enable flip- oT pt Inpa flop is set (VEN low) on each active clock edge if an Accept requests as active-low levels or pulses, depending on unmasked interrupt is waiting in the interrupt register, other- the voltage level at the IM pin, wise it is cleared, ™M Input Mode Select, CASIN1 Cascade-in 1. When IM is low, INT>-INT7 detect asynchronous pulse inputs, When IM is high, INTo-INT7 detect level inputs. High level forces MINTR high and causes the CHSR and CCIR instructions to have no effect. lo-1g Instruction Inputs. TEN instruction Enable. CASIN2 Cascade-in 2. The instruction on lo-Ig is ignored it TEN is high, High level forces MINTA high and clears the vector-onable flip-flop on the next active clock edge. CS Chip Select. Instructions 4 - 15 (those which use the D-bus) are ignored it CASOUT1 Cascade-out 1, CS is high. Forced high if any bit in the in-sorvice register is set or if WINTR Maskable interrupt. CASIN1 fs high. Low level indicates that an unmasked interrupt request which CASOUT2 Cascade-out 2. has a priority higher than the request currently being serviced | is in the interrupt register waiting for service. MINTR is forced ‘Forced high if there is an unmasked interrupt request in the high when either MINTA is low or CASIN1 or CASIN2 are high. _—terrupt register or if CASIN2 is high. MINTE has an open collector output. RESET Master Reset. MINTA Maskable Interrupt Acknowledge. High level causes the interrupt latches, interrupt register, in- Active-low signal causes the interrupting request vector in the service register and mask register to be cleared on the next vector output register to be enabled onto the vector output active clock edge. Pins (Vo- Ve). It also causes the bit corresponding to the interrupting request to be cleared in the interrupt register and PD Post-Delay Mode. setin me pposindiea ad 1 To permit ae ese Hard-wire high when operating with the Am29112 in post- enable tip-iop i seb. reat ee delay mode. High level causes CASIN1 input and prioritized ip-flop is sel output of in-service register to be delayed by one clock cycle. Vo-V2 int ve ° ~V2 Interrupt Vector. on? m CP Clock Pulse. Tristate Vo - Va lines are output enabled with the interrupting vector when the MINTA input is low and the VEN output is low All state changes occur on the low-to-high transition of the (.e., vector-enable flip-flop is set.) clock. FUNCTIONAL DESCRIPTION The Am29114 is controlled by a 4-bit instruction field which allows the three above-mentioned registers to be read or The Am29114 receives interrupt requests on 8 interrupt input _-Oalfied under microprogram control. lines (INTo ~ INT7). A LOW level is a request. An internal latch may be used to catch pulses on these lines, or the latch may Architecture Of The Am29114 Pe rmpassed $0 eens nes crive eae tiouered The Am29114 is a high-performance priority interrupt control- nan ¥. nask reg ler. As shown in the Block Diagram, the device contains four mask individual intorupts. Requests inthe iterupt register (07s anew ihe Brack Diagram. the de Negiaten the In are ANDed withthe corrasponding bits in the mask register OUSTS"S_ he Interrupt Resistor. Ouipat Rogier” and the result is sent to a priority encoder, which produces a 3- legister, legister. bit encoded vector representing the highest numbered input which is not masked. This encoded vector will be held in the _-«(Mterrupt Latch/Register vector output register. The B-bit Interrupt Register stores pending interrupt requests in clocked D flip-flops. A bit in the register is automatically An 8.bit in-sorvice register holds a bit for each interrupt cleared when the corresponding interrupt request is acknow!. request that is currently being serviced, If a new interrupt has a edged by the system sequencer. Interrupt requests can be higher priority than the one in process, an interrupt request accepted via 8 S-R latches in either of two modes depending output will occur and this signal will be sent to the sequencer. upon the level of the IM input. ‘Subsequently, an acknowledge signal from the sequencer is. used to enable the vector outputs and to set the correspond- Asynchronous Pulse Mode: Low-going pulses on the INT ing bit in the in-service register to prevent the interrupt routine inputs set the latches. The outputs of the latches cause the from being interrupted by a lower priority interrupt. When the respective flip-flops to be set on the next active clock edge. ‘service routine is complete, an instruction clearing the in- ‘The outputs of the flip-flops are then used to clear the latches. service register bit allows system operation to continue as Requests remain stored in the ragister unti their interrupts aro before. acknowledged.
‘ow 7 forms a binary coded interrupt vector. The B-bit In-Service Register keeps track of which interrupt Output Register (after an interrupt acknowledge is received). bit in the In-Service Register is set, a microinstruction mustbe enable and cascade signals. TABLE 1. INSTRUCTION SET
- CHSR may be used at the end of an interrupt service routine to restore the previous priority level. in post-delay mode CHSA clears the bit that had the
- Cain cloars the interrupt register bit corresponding to the highest bit set inthe in-service register. In post-delay mode COIR clears the bitin the interrupt
‘8. Sots those register bits that have corresponding O-Bus bits equal to one. Other register bits are not affected. 4% Clears those register bits that have corresponding D-Bus bit equal to one. Other register bits are not affected.
- Overides the effect of an interupt request or an interrupt acknowledge on bits beng modiied i received during the samo clock cycle,
- An interrupt acknowledge recerved during the same clock cyclo will override this instruction where they affect the same bit
‘Am29112 is used to enable the vector output onto the Y-bus. Figure 1. The tri-state vector outputs are connected to three
microinstruction pipeline register, and the D-bus is connected —_ together or left separate if the width of the system bus allows. a single Am29114, the CASIN1 and CASIN2 are hardwired particular chip for D-bus operations. clock lines. The D-bus pins of each chip may either be tied directly as the fourth bit of the interrupt vector (Figure 4). Figure 1. Connection of Am29114 to Am29112
4 Mo~ Ve
Figure 2. Cascading the Am29114-Method 1
b PT cs casoun—_casoure Pr . Figure 3. Cascading the Am29114-Method 2
Figure 4. Cascading the Am29114 -16-Bit Configuration
| PHYSICAL DIMENSIONS | SD 040 {TT Sb pe ee am
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