AM29117

AM29116 AMD | Alldatasheet

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High-Performance 16-Bit Bipolar Microprocessors DISTINCTIVE CHARACTERISTICS 8 © Optimized for High-Performance Controllers © Powerful Field Insertion/Extraction and z Excellent solution for applications requiring speed Bit-Manipulation Instructions Ss and bit-manipulation power. Rotate and Merge, Rotate and Compare and bit- z © Fast manipulation instructions provided for complex bit 8 The Am29116 supports 100-ns microcycie time/10-MHz_ control. c data rate for all instructions. ‘© Immediate instruction Capability Fy © Speed-Enhanced Version May be used for storing constants in microcode or z The Am29116A is 25% faster than the Am29116. for configuring a second data port. z © Low-Power Version © 16-Bit Barrel Shifter 8 The Am29L116A is the same speed as the © 32-Working Registers s Am29116 and dissipates 25% less power. o GENERAL DESCRIPTION > The Am29116 is a microprogrammable 16-bit bipolar micro- Multiplier (65-ns worst-case 16 x 16 multiply). In addition to processor whose architecture and instruction set is opti- its compiete arithmetic and logic instruction set, the mized for high-performance peripheral controllers, like | Am29116 instruction set contains functions particularly Q graphics controllers, disk controllers, communications con- useful in controller applications; bit set, bit reset, bit test, Ss trollers, front-end concentrators and modems. The device rotate and merge, rotate and compare, and cyclic-redun- also performs well in microprogrammed processor applica. dancy-check (CRC) generation. a tions, especially when combined with the Am29517, 16 x 16 ry) BLOCK DIAGRAM Q aor, = yes fe) [z= L= | Le] ro) v 3 io) 80001962 Publication # Rev. Amendment 002438 {Issue Date: October 1986

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RELATED PRODUCTS

Tmaeit? | gh Perornance &-it Sice Uiroprogram Sequencer | aaticrie | ow0s verson of be anaine | GMOS Varsion of the Am23t17 ~ Lanarre —[ ear amgorre V0 Super CONNECTION DIAGRAMS Top View < sere sree rete wh abe “a “Be eeenearneicded= Dede Esi= Ee ae 2B. Sea me [Bs «ioe as se! [Bs «bos aD «qq apn wo Oe «ae ‘a cBe aw Bn Ot oe tas cB Oe aD vor oes SB ve Bin i <a: “Bre vee ats “ee “By «oe tds ‘a: MShe ve On otes ea: "Bee oo OD cr we] >Bu oo ov bel Toa gah sBe ww Ee OD am acs “Be erTerrr eT TTT was 2Be AAAAAAARARAAA ag: 2Bie me reseeeer gee gs TE 7pt c0os183 004191 Note: Pin 1 is marked for orientation. *On the current bipolar devices, pin 12 is not connected (INC) internally. Historically, this pin was: connected. CMOS options of the ‘Am29116 currently use this pin for an internal Voc connection. LOGIC SYMBOL 7 > fo-ws iN You KO > SRE oe \\ oe, wa > OE, or or Lsoazas2 GND = Ground Voc = Power Supply

Voc AND GROUND PIN CONNECTIONS ToP VIEW o se 32 sie 33 se wen ca es Be in Voc Plane 36 ve o7 ie os se 35 tee op e10 oe ka @ = Through Hole en ae ti = Voc Plane Connection eis te x Cy=Cg= 01 uF oi se tt Cp=Ca= 10 uF ois ee oH se 3% a7 6° oie Be ois ue 220 ase ear 32° e22 ne ©23 30° ela 20° O25 2e 026 ae 0010201 The Am29116 Family of microprocessors consists of high-performance devices that operate in an environment of fast signal To (Mee an substantial switching curents. Attention must be paid to layout and decoupling to avoid undesired ctfects trom the envronment. The following suggestions may bo of boneft in developing the layout scheme: 1. A muit-layer PC board with separate powor, ground, and signal planes roqured for Schottky performance-lovel systoms 2 Tee the four ground pins Immediately to the ground plane. 2 ushered Relation ext should be mado in the Voe, plane between pins 12 and 13 and pins 40 and 41. This isolation ut cetabishes a low-pass notwork that will provide sufficient inducive isolation between pin 40 (which supplies the TTL Suiper aewors) and plat (which supplies the internal ECL) 80 that Waneiant currents will have no etfect on the intemal operation 4, Parad must be tied directly to the Vcc plane and decoupled with a buk capacitor (10 uF) and a high-frequency capacitor (0.1 4F corm) 5, bin 41 must be led direct to the Voc plane and decoupled with 0.1 uF and 10 uF capacitors 8: The decoupling cepactors must be placed physically as close as possible to pin 40 and pin 41 respectively. METALLIZATION AND PAD LAYOUTS Am20116 Am20116A/Am29L116A : A \\ 3 ] — — fs . eg ae “~ — . CANON BTS ‘— — te ae ; ey t= | = ien te 1 _— 4 — = noo? 20,0 — SRE hal nel fee) De, eee te 4 ba . hy = od a j Is a fot se = > eo - 15 n Cec oor EyULUL Yo . = " Mi ||| === Gio 35411) | SF ll —— Fe Lo ———— al . Die Size: 0.251” x 0.311" Die Size: 0.205" x 0.250” Gate Count: 2500 Equivalent Gates Gate Count: 2500 Equivalent Gates

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by @ combination of: A. Device Number B. Speed Option (it applicable) ~ C. Package Type ~ D. Temperature Range E. Optional Processing -AM29116A, 2 & & Lo OPTIONAL PROCESSING B= Burnin 1D. TEMPERATURE RANGE C= Commercial (0 to + 70°C) ©, PACKAGE TYPE D = 52-Pin Topbrazed Ceramic DIP TD 052 = DIP with Heat Sink ‘TDX052 = DIP without Heat Sink (Note 1) L=52-Pin Ceramic Leadless Chip Carrier (CL 1052) x=Dico B. SPEED OPTION Not Applicable A. DEVICE NUMBER/DESCRIPTION Amea1 16 po reales [Vata Combinations | AnaotieA Valid Combinations High-Speed, High-Performance 16-Bit MPU "AM25116, Am2SL1168 AMZ0116A be, 0c, {ow-Power, High-Performance 16-Bit MPU AMOLII6A UC) xc (Note 1) Notes: 1. 52:pin DIP without heat sink (TDX052) is available only for the Am29L116A Low-Power, High-Performance MPU. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combina- _ tions, to check on newly released valid combinations, and to obtain additional data on AMD's standard military grade products.

AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. CPL (Controlled Products List) products are processed in accordance with MIL-STD-8836, but are inherently non-compliant because of package, solderability, or surface treatment exceptions to those specifications. The order number (Valid Combination) is formed by a combination of: APL Products: A. Device Number CPL Products: A. Device Number B. Speed Option (it applicable) B. Speed Option (if applicable) C. Device Class C. Package Type D. Package Type D. Temparature Range E. Lead Finish E. CPL Status APL Products nT Be — E. LEAD FINISH ‘A= Hot Solder OIP D. PACKAGE TYPE U=52-Pin Coramic Leadiess Chip Carrier (cLT052) ©. DEVICE CLASS 78 = Cass 8 B. SPEED OPTION Not Applicable A. DEVICE NUMBER/DESCRIPTION am2ait6 High-Performance 16-8it MPU CPL Products Auzo116. ny M © Lo CPL STATUS C= CPL Certified D. TEMPERATURE RANGE M= Military (-55 to + 125°C) C. PACKAGE TYPE 10 = 52-Pin Topbrazed Ceramic DIP (TD 052) B. SPEED OPTION Not Applicable A. DEVICE NUMBER/DESCRIPTION Am29i16 tHigh-Peciormance 16-8it MPU Valid Combinations Valid Combinations A Valid Combinations list configurations planned to be P|) AM29116 /BUA supported in volume for this device. Consult the local AMD L sales office to contirm availability of specific valid c combinations or to check for newly released valid Pp AM29116 /DMC combinations. L Group A Tests Group A Tests consists of Subgroups:

When OEy is HIGH, Yo-Y 1s are used as external data inputs TEN HIGH will inhibit the Status Register from changing. during a LOW-HIGH transition of the clock. TEN HIGH, the conditional test output, CT, is disabled as a enabled (HIGH or LOW). updated at the end of all instructions with the exception of LOW indicates a failed condition. The following diagram (Figure 1) is a summary of devices within the Am29116 Family showing performance vorsus power.

4 Amao116A 0 Amagnt6

Figure 1. Am29116 Family

= ff = = fee

ARCHITECTURE OF THE Am29116 ‘The Am29116 is a high-performance, microprogrammable 16- executing in the byte or word mode. The Z (zero) flag, bit bipolar microprocessor. although not generated by the ALU, detects zero at both the d level. AAs shown in the Block Diagram, the device consists of the s*® 4” word lov following elements interconnected with 16-bit data paths. The cary input to the ALU is generated by the Carry Multiplexer which can select an input of zero, one, or the © 32:Word by 16-Bit RAM stored carry bit from the Status Register, QC. Using QC as the © Accumulator carry input allows execution of multiprecision addition and © Data Latch subtractions. © Barrel Shifter © AW Priority Encoder © Priority Encoder The Priority Encoder produces a binary-weighted code to © Status Register indicate the locations of the highest order ONE at its input. ‘© Condition-Code Generator/Multiplexer The input to the Priority Encoder is generated by the ALU © Three-State Output Butters which performs an AND operation on the operand to be © Instruction Latch and Decoder prioritized and a mask. The mask determines which bit . locations to eliminate from prioritization. In the word mode, if 32-Word by 16-Bit RAM no bit is HIGH, the output is a binary zero. f bit 15 is HIGH, the ‘The 32-Word by 16-Bit RAMis a single-port RAM with a 16-bit output is a binary one. Bit 14 produces a binary two, etc, latch at its output. The latches are transparent when the clock Finally, if only bit 0 is HIGH, a binary 16 is produced. input (CP) is HIGH and latched when the clock input is LOW. . Data is written into the RAM while the clock is LOW if the TEN In ee byte one be 8 thea 15 do not paricpate 1 mone of inputs also LOW and if the instruction being executed defines Bits 7 thru 9 are |, the output is a binary zero. b HIGH a binary one is produced. Bit 6 produces a binary two, the RAM as the destination of the operation. For byte tea. y only BO is HIGH, a binary 8 is produced. instructions, only the lower eight RAM bits are written into; fort: Finally. if only s a binary 8 is prom word instructions, all 16 bits are written into. With the use ofan Status Register external multiplexer on five of the instruction inputs, it is . possible to select separate read and write addresses for the The Status Register holds the 6-bit status word. With the ‘Same instruction. This two-address operation is not allowed for __Status-Register Enable, (GRE) input LOW and the TEN input immediate instructions. LOW, the Status Register is updated at the end of all instructions except NO-OP, Save-Status and Test-Status in- Accumulator structions. SRE going HIGH or TEN going HIGH inhibits the The 16-bit Accumulator is an edgo-tiggored register. The Status Register from changing. ‘Accumulator accepts data on the LOW-to-HIGH transition of The lower four bits of the Status Register contain the ALU the clock input if the TEN input is LOW and if the instruction status bits of Zero (Z), Carry, (C) Negative (N), and Overflow being executed defines the Accumulator as the destination of (QV). The upper four bits contain a Link bit and three user- the operation. For byte instructions, only the lower eight bits of | definable status bits (Flag 1, Flag 2, Flag 3). the Accumulator are written into; for word instructions, all 16 <a or bite are written into. With SRE LOW and TEN LOW, the lower four status bits are updated after each instruction except those mentioned above, Data Latch NO-OP, Save Status, Status Test and the Status Set/Reset for the upper four bits. Under the same conditions, ‘The 16-bit Data Latch holds the data input to the Am29116 on instruction thedcdrectonal ¥ bus The atchis transparent when the DLE PE per four staus bis fe, changed ory eatog. ie it GH . input is HIGH and latched when the DLE input is LOW Load instructions in the word mode. The Link-Status bit is also Barrel Shifter updated after each shift instruction. ‘A 16-bit Barrel Shifter is used as one of the ALU inputs. This The Status Register can be loaded from the internal Y-bus, permits rotating data from either the RAM, the Accumulator or _and can also be selected as a source for the internal Y-bus. the Data Latch up to 15 positions. in the word mode, the Barrel When the Status Ragister is loaded in the word mode, all 8- Shitter rotates a 16-bit word; in the byte mode, it rotates only _bits are updated; in the byte mode, only the lower 4 bits (Z, C, the lower eight bits N, OVR) are updated. Arithmetic Logic Unit When the Status Register is selected as a source in the word mode, all eight bits are loaded into the lower byte of the ane ace bre mine a tebe ALY wih mea, lookahead destination; the upper byte ofthe destination is toaded with all aes es hero ae net ese operand Scapa zeros. In the byte mode, the Status Register again loads into of operating on either one, two or three operands, depending the lower byte of the destination, but the upper byte remains upon the instruction pad oro It has the ability to Unchanged. This Store and Load combination allows saving groove ae ae ere corplonanh creraion the restoring the Status Register for interrupt and subroutine 2 . . | processing. The four lower status bits (Z, C, N, OVR) can be Ae baie oon arena wotuctone, such as read directly via the bidirectional T bus. These four bits are abl puts on the T Poiate and merge, and rotate and compare with mask. All ALU Puayable a8 Outputs on the 1-4 outputs whenever OEr is operations can be performed on either a word or byte basis, 7 byte operations being performed on the lower eight bits only. Condition-Code Generator/Multiplexer ‘The ALU produces three status outputs, C (carry), N (negative) The Condition-Code Generator/Multiplexer contains the logic and OVR (overflow), The appropriate tlags are generated at necessary to develop the 12 condition-code test signals. The the byte or word level, depending upon whether the device is multiplexer portion can select one of these test signals and

place it on the CT output for use by the microprogram bits (Z, C, N, OVR) externally. A LOW Er input forces the T Eoquence, The multiplexer may be addressed in two different outputs into the high-impedance state. External devices can ways, One way is through the Test Instruction. Ths instruction _then drive the T bus to select a test condition for the CT specifies the test condition to be placed in the CT output, but output. does not allow an ALU operation at the same time. The 10 erat cag the brtrecional T bus as an input. Ths ‘(atruction Latch and Decoder requires extra bits in the microword, but provides the abilty to The 16-bit Instruction Latch is normally transparent to allow simultaneously test and execute. The test instruction lines, decoding of the Instruction Inputs by the Instruction Decoder Ip.4, have priority over T}.4, for testing status. into the internal control signals for the Am29116. All instruc Three-State Output Buffers te eet Immediate Instructions are executed in a single There aro two sets of Three-State Output Buffers in the immediate instructions require two clock cycles for execution. ‘Am29116, One set controls the bidirectional, 16-bit Y bus. uring the first clock cycle, the Instruction Decoder recognizes These outputs are enabled by placing @ LOW onthe OE input. that an Immediate Instruction is being specified and captures ‘A HIGH puts the Y outputs in the high-impedance state, the data on the Instruction Inputs in the Instruction Latch. allowing data to be input to the Data latch from an external i ‘on source. During the second clock cycle, the data on the Instruction

7 Inputs is used as one of the operands for the function

The second set of Three-State Output Butfers controls the specified during the first clock cycle. At the end of the second bidirectional 4-bit T bus and is enabled by placing a HIGH on clock cycle, the Instruction Latch is returned to its transparent ‘the OEr input. This allows storing the four internal ALU status state. INSTRUCTION SET The instruction set of the Am29116 is very powerful. In The Am29116 Instruction Set can be divided into eleven addition to the single and two operand logical and arithmetic _—types of instructions. These are: instructions, the Am29116 instruction set contains functions particularly useful in controller applications: bit set, bit reset, @ Single Operand @ Rotate and Compare bit test, rotate and merge, rotate and compare, and cyclic- @ Two Operand © Prioritize redundancy-check (CRC) generation. Complex’ instructions © Single Bit Shift © Cyclic-Redundancy-Chock like rotate and merge, rotate and compare, and prioritize are @ Rotate and Merge © Status executed in a single microcycte. © Bit Oriented © No-Op @ Rotate by n Bits Three data types are supported by the Am29116. @ Bit Each instruction type is arbitrarily divided into quadrants, Two © Byte ‘of the sixteen instruction lines decode to four quadrants © Word (16-bit) labelled from 0 to 3. The quadrants were defined mainly for convenience in classification of the instruction set and ad- In the byte mode data is written into the lower half of the word dressing modes and can be used together with the: oP and the upper half is unchanged. The special case is when the CODES to distinguish the instructions. ‘statu: ster is ified as tination. In the aa rere me cate regeterisupsaed anein The folowing pages describe each ofthe instucton yPos in the word mods all eight bits ofthe status register are updated. 2248. Throughout the description OEY is assumed to be LOW ‘The status register does not change for save status and test SNOWING ALU outputs on the Y-bus. status instructions. In the test status instructions the CT output Table 1 illustrates operand source-destination combinations has the result and the Y-bus is undefined. for each instruction type.

TABLE 1. OPERAND SOURCE DESTINATION COMBINATIONS

1. In the SINGLE OPERAND INSTRUCTION, RAM cannot be used when both ACC and
2. In the PRIORITIZE INSTRUCTION, OPERAND and MASK must be different sources.

SINGLE OPERAND INSTRUCTIONS The Single Operand instructions contain four indicators: byte _B-bit to 16-bit conversion is needed, the Am29116 is capable ‘or word mode, opcode, source and destination. They are _of extending sign bit (D(SE)) or binary zero (D(0E)) over 16-bits further subdivided into two types. The first type uses RAM as a__in the word mode. The least significant four bits of the Status source or destination or both, and the second type does not —_—Register (OVA, N, C, Z) are affected by the function performed use RAM as a source or destination. Both types have different _in this category. The most significant bits of status register instruction formats as shown below. Under the control of (FLAG1, FLAG2, FLAGS, LINK) are not affected. The only instruction inputs, the desired function is performed on the _ limitation in this type is that the RAM cannot be used as a source and the result is eithor stored in the specified destina-. source when both ACC and the Status Register are specified tion or placed on the Y-bus or both. For a special case where as a destination. SINGLE OPERAND FIELD DEFINITIONS 1514 13 12 98 54 0 son [Baw] cues | opcode | SAC Den | RAM Adios sonn [p/w] ava T Opodo | sac [dest SINGLE OPERAND INSTRUCTION bu 2 8 a5 40 [ instruction’ [erw?[aued'] opcode | R/S* Deer’ [RAM Address ___|

7100 MOVE SAC—Dest 0000 SORA RAM AGG [00000 R00 —--RAM Reg 00

4101 COMP SAC_Dest 0010 SORY RAM YBus | os - oe

TH0 INC. SAC+1-Dest | 0011 SORS RAM Status [11111 31 RAM Reg 31

4111 NEG SAC+1—Dest | 0100 SOAR ACC RAM

0110 SODR D-RAM

1000 SOZR_ 0 RAM

1001 SOZER DOE) RAM

4010 SOSER DISE) RAM

1011 _SORR RAM _RAM [Cinsrvcion [ee [awa] opeoue [mst «| Coats

1100 WOVE SAC—Dest 0100 SOA AOC 00000 NAY Y Bus

1101 COMP SAE_Dest 110 SOD 00001 NRA = ACC

3410 INC) SAC41.Dest | 0111 SO! 1 00100 NAS Status

1111 NEG SRC+1-Dest | 1000 SOZ 0 00101 NRAS — ACC, Status®

1001 SOZE DIE)

1010_SOSE_DISE) Notes: 1. The instruction mnemone, designates diferent instruction formats used in the Amz9116. They are useful in assembly microcode with the System 29 AMDASM'™ mota assembler. 2, B= Byte Mode, W= Word Mode. 3. See Instruction Set description. 4, Fl= Source; S = Source; Dest = Destination. 5. When status is destination, Status i - Yi i=0 to 3 (Byte mode) i= 0 t0 7 (Word mode) Y BUS AND STATUS - SINGLE OPERAND INSTRUCTIONS [_ instruction [ Opcode [Description | 6/w] ¥ — Bue [Flag | Fiag2 [Flags | unx [ova] n [c [2 | con | __wove —[onG=ben J o-e[v- smo ne [ no | wo [no] 0 [ufelu] SONA [comp [SRC dest jy= eRe [ne [no [no [nc | o [ufoTtu | [inc [src +1 Dest [y= saces [nc | no [ne [nc [uv Tututu | [Neg |SRC +1—Dost_ fy eaces nc [nc [one | no Tu Tututy | SRC = Source = Rosot U= Update. 1= Set NC = No Change i= 0 to 15 when not specitiod

The Two Operand Instructions contain five indicators: byte or ‘specified destination or placed on the Y-bus or both. The least word mode, opcode, R source, S source, and destination. significant four bits of the status register (OVR, N, C, Z) are They are further subdivided into two types. The first type uses affected by the arithmetic functions performed and ‘only the N RAM as the source and/or destination and the second type and Z bits are affected by the logical functions performed. The does not use RAM as source or destination. The first type has OVR and C bits of the status register are forced to ZERO for two formats; the only difference is in the quadrant. Under the logical functions. Add with carry and Subtract with carry control of instruction inputs, the desired function is performed instructions are useful for Multiprecision Add or Subtract. ‘on the specified sources and the result is stored in the TWO OPERAND FIELD DEFINITIONS 15 14 13 12 98 54 oO SRC-SRC com none] S| oem [a i st TWO OPERAND INSTRUCTIONS Ss Se me OTF a j0010 «=< TORIA. «RAM I ‘ACC }0001 SUBRC? S minus R an eres

0011 TODRA D RAM ACC with carry dtd R31 RAM Reg 31

1010 TORIY RAM | Y Bus ]0011 — SUBSC* _R minus S

11100 TORAR RAM ACC RAM [0100 ADD R pus S

1111 TODRR O RAM RAM with cary

1000 EXOR:

[isiveon [ore] Omea] a a bent] openers | 10001 TODAR O ACC RAM = |0000: ‘SUBR_ S minus R }00000 «ROO. RAM Reg 00 10010 «Ss TOAIR, «ACC OC RAM [0001 SUBRC? S$ minus R ee ae ee fee sues, ass 10011 SUBSC? R minus S nes

1010 OR +S

$= Source Se wasn ve 2 any spe 8

{srocion [er [ouma] ata] —__Opeoge anion 0010 «=TOA! ACC I 0001 SUBRC S minus R with 00001 NRA ACC 2 0010, ‘suBS R minus S 00101 NRAS ACC, Status‘ be 0100, ADD R plus S

0101 ADDC FR plus S with

1001 NOR Rts

Notes 1: R= Source S= Source i=0 to 7 (Word mode) 4: OVR=Cg © Cz (Byte mode) OVR = Cig @ C15 (Word mode) Y BUS AND STATUS CONTENTS - TWO OPERAND INSTRUCTIONS [marcton [opie [oven [ orw | vem [ren ]ran] "2 ome [ov ||| [ssn [Smnea [ore [seRvs [wo [wo fue [no] v [ululul pesencos [re me [re |e |» [fof] [us [ames] [FonvSrs [wo fe [we [we] w [Ulva TOR1 SUBSC R minus S with Y-R+5+QC NC NC NC NC U TOR2 carry aC Co a eC lwo [as] [emma [wo [nef | we] @ [ulolo] tuo [RS] [Wemnmws [no [no [we | no] o [ulolu] [eons] fre mmons [no [nef uc | no] o [ulolul [non [Res] rcmnons [no [ne [uc] no] 0 [ulolul [on [avs] remo [no [rot we] wo] © [ulolu| femon [es | __ [vm mnong [no [re [we [no | © [elo fu] U = Update: NC = No Chango 0 = Reset 1=Set i=0 to 15 when not specified f

SINGLE BIT SHIFT INSTRUCTIONS SINGLE BIT SHIFT ee 0110 ©=SHRR RAM RAM 0000 = SHUPZ Up ° 00000 ROO RAM Reg 00

0111 SHOR 0 RAM |0001 SHUP1 Up 1 Dee eee

SHFTR 0010 = SHUPL Up QUINK 11111 R31 RAM Reg 31 eo in BS 0111 ‘SHDNC Down QC SENS, Ber Siscovn [Cimswvion [ew [aww] 0 | ———neoae | —atoaton 0110 SHA ACC 0000 = SHUPZ Up oO 0000 NRY Y Bus. ont SHD oO 0001 ‘SHUPT Up 1 00001 NRA ACC ae Sue Bie) SE an 9

0110 SHDNL Down QLINK

1000 _SHDONOV Down ON@QOVR. Fenn Y BUS AND STATUS - SINGLE BIT SHIFT INSTRUCTIONS [Cinstacion [Opsose [ Dessapton [enw] __¥- um | Fags [Feg? [reat] une [oval _w_[o]2 ‘SHUPZ Up 0 Y¥/~ SAC), i= 1 to 15; NC NC SRC, sur |e 3 aan SHUPL | Up QLINK yi=SAG 1, T= 7 10 Ye~ SAC7, ¥,~SAC\\-9 No SRCg | 0] U ‘SHDNZ Down 0 Yj SAC) +3, 1=0 to 14; ‘Shit Ser fame PewvsSici [ve | ve [me | sco | 0 | ioe [oe ‘SHDNL Down QLINK ¥i~SRG + 1, 1=0 to 6; Y¥7,15°Shift Input Input ‘SRC = Source “Shifted Output is loaded into the QLINK. ‘U= Update TE ae eae

‘The Bit Oriented Instructions contain four indicators: byte or which forces the nl" bit to ZERO leaving the other bits ‘word mode, operation, source/destination, and the bit position unchanged; Test Bit n, which sets the ZERO Status Bit of the bit to be operated on (Bit 0 is the least significant bit). depending on the state of bit n leaving all the bits unchanged; They are further subdivided into two types. Tho first type uses Load 2", which loads ONE in Bit position n and ZERO in all the RAM as both source and destination and has two kinds of other bit positions; Load 2" which loads ZERO in bit position n formats which differ only by quadrant. The second type does. and ONE in all other bit positions; increment by 2", which adds a not use the RAM as a source or a destination. Under the 2" to the operand; and decrement by 2 which subtracts 2” control of the instruction inputs, the desired function is from the operand. For all the Load, Set, Reset and Test performed on the specified source and the result is stored in _ instructions, the N and Z bits are affected and OVR and C bit the specified destination or placed on the Y-bus or both. The _of the Status register are forced to ZERO. For all arithmetic operations which can be performed are: Set Bitn which forces _instructions the LSH (OVA, C, N, Z bits) of the Status register the n'” bit to a ONE leaving other bits unchanged; Reset Bitn _is affected. BIT ORIENTED FIELD DEFINITIONS 15 14 13 1298 54 ) soni [B/w] Quad] n [opcode | RAM Address sone [Brw]Gmad] » | Spcoue | RAM Aas eonn[Biw[oma] a [100 | Orcowe | BIT ORIENTED INSTRUCTIONS [rewooion Terw[ovea] a | Oneode—<d——~SC*RAM Aarons [ow | 1101 SETNR Set RAM, bit n ‘00000 ROO RAM Reg 00 BORT 01015 | 1110 RSNA Reset RAM, bit n i “ nee 1111__TSTNR__Tost RAM. bit n at Rat RAM Reg 31 [instruction [erw loved] | Opcode | RAM Adcress |

7700 LO2NR 2 RAM

pone to Hor Beane BRA 20000 ROO RAM Reg 00 1110 Aan ius 2°. RAM [instruction [erwlaual oe [|code

0000 TSTNA Test AOG, bit n

00001 RSTNA Reset AGC, bit n

00010 © SETNA Sot ACC, bit n 00100 © A2NA—— ACE plus 2" -. ACC 00101 © S2NA_ ACC minus 2° “ACC 00110 = LO2NA_ 2" ACC eoNnr oon) = LORNA acc

10000 TSTND— Test D, bit n

10001 ASTND Reset ©, bit n

30010 SETND— Sot D, bit n

10100 © AZNDY =D pus 2°. Y BUS yo1o1 = S2NDY mus 2. Y Bus yoo LS2NY. 2" |. Y Bus sors uocany_ 2 Bus

Y BUS AND STATUS - BIT ORIENTED INSTRUCTIONS | iestmcton [opcode] Description [erw] _Y-Bus | Fags | Faga | Fiagt [Lwnloval w[¢ [72 | mec [e [ee fers eel gory SST [Bee RAS Se n [Pw [Ysa tor tem Yor xe ann [yo itn YarsaGe | nef no [ne [roto fufolu | Virotrien Vert | ne [| no | no facto fufofo | sone REGRET Raw ——] [retmren vero [we [we [ve [re fo ful ote | icramre™ | no [ne | ne [wo tu futuyu | er a Vviro tori#n Verne | ne {| no | no [nc fo futo[u | VicAGG frién Varo] Ne _| ne | we [repo tutolu| lyracc.tori@nYart | no] no | ne [no fo fulofo | lank —[accrataace] = ffiracoea® wef no | we fc fu fututy | leona —acc=eacc | frraco-ar Sino | no [ne [wo fu fufute | Nn witm veri we [ne | ne [ne to tulolo | eonr lyirttri¢n vere | No | ne | ne [acto [ufofo | Vow ien vero pve no [ne [ve fo [utotul Wviro torien Varo] ne _[ no | no_[nc fo fufo[u | [Seno [ser Droen” | fviroreriem yarn | no_| no | no [no [oe Jutofo | Le SS a A A Wrowiza ver | ne _[ ne | ne [ne fo futefo | Keren vare tne [we | ne [ne fe futoto| SiG = owe U-= Update Yee ange path 1=Set 122 5 nen not pected

ROTATE BY n BITS INSTRUCTIONS The Rotate by n Bits Instructions contain four indicators: byte _i either stored in the specified destination or placed on the Y- or word mode, source, destination and the number of places bus or both. An example of this instruction is given in Figure 5. the source is to be rotated. They are further subdivided into In the Word mode, all 16-bits are rotated up while in the Byte two types. The first type uses RAM as a source and/or a _mode, only the lower &-bits (0-7) are rotated up; In the Word destination and the second type does not use RAM as a —_—mode, a rotate up by n bits is equivalent to a rotate down by source or destination. The first type has two diferent formats __(16-n) bits. Similarly, in the Byte mode a rotate up by n bits is and the only difference is in the quadrant. The second type equivalent to a rotate down by (8-n) bits, The N and Z bits of ‘has only one format as shown in the table. Under the control the Status Register are affected and OVR and C bits are of instruction inputs, the n indicator specifies the number of bit forced to ZERO. Positions the source is to be rotated up (0 to 15), and the result EXAMPLE: n= 4, Word Mode ROTATE BY n BITS FIELD DEFINITIONS Source 0001 0011 ont 4411 Destination 0011 ont 11 0001 18 14 19 1208 S4 © EXAMPLE: n= 4, Byte Mode ott [s/w] Quad] n [SRC-Dest | RAM Address Source 0001 0011 01nd abhi Destination 0001 oot 14 out RoTR2[B/W| Quad] n | SRC-Dest RAM Address Figure 5, Rotate by n Example ROTNA[B/w]Oued] [1100] _SAODest ROTATE BY n BITS INSTRUCTIONS [Cissmacton [ew [Oma [9 [oot hates Jom [et] © [ows [ER HR EGE [I owes | ROTA 1110 -ATRY «RAM Y Bus | : Reef

41 RTAR__RAM RAM” [11171 RAM Reg 31

notre ao eran aco aw [@™000 AOD RAW Rog CO

0001 RIOR =D RAM fl saint R31 _ RAM Reg 31

[_tnetruetion [| /w | Qued [on ft est Tio ATOY Yor 11001 a) a ROTNR 11100 RTAY ACC Y Bus 1N01__RTAA_ ACCC Note 1 U= Source Dest = Destination Y BUS AND STATUS - ROTATE BY n BITS INSTRUCTIONS. Op- - L_twrcton [ache |om | vom [recs rat at [ume] ove | _[e] | ROTA [i=w [viesrcenmoss TC [nc [nc [onc To ['srcis-n ToT | ROTR2 Y|—~ SRC) + § = SRCi.nymods ron Lore [ereray ere [ne Tne | ne [ve [oT srcen Lol | SRC = Source U=No Change 0= Reset 1=Set i=0 to 15 when not specified

U, is rotated up by the Barrel Shifter n places. The mask input to ZERO. An example of this instruction is given in Figure 7. Figure 7. Rotate and Merge Example. Figure 6. Rotate and Merge Function.

1000 MDAR ACC ORAM

1080 MORA DRAM ace 11111 R31 RAM Rog 91

3110 MRAL_RAM ACC

n places. The mask is inverted and ANDed on a bit-by-bit basis Figure 9. Figure 8. Rotate and Compare Function.

participation in the priority encoding function. different sources. Figure 10. Prioritize Function. ‘4 2 6 2

1014 PRIR __RAM 1001 Pain 11111__A91_ RAM Rag 31

generate these check bits for the CRC Forward function and OVR and C bits of the Status register are forced to ZERO. Figure 12. CRC Forward Function.

Figure 13. CRC Reverse Function.

Status Instructions - The Set Status Instruction contains a _ status register on CT output. See the discussion on the status single indicator. This indicator specifies which bit or group of register for a full description. bits, contained in the status register (Figure 14), are to be set (forced to a ONE). t | tT | Te | Th cr 4 |b | b hy wa Rex [Fe - aI [oe To [oe | o [meovm +z Flag3 Flagt | LINK [mo [0 [oe | 1 [Neovn wears [To foots to fz | Four 14. statue Byte epee fom The Reset Status Instruction contains a single indicator. This Feet ee gapoaconansmne | 1+ {ot 0 status register, are to be reset (forced to ZERO). pofrfo}s fe | The Stor Stats Insicton contains two indicators: wor = [ 0 | 1 [ t |e [zee | word and a second indicator that specifies the destination of [ns we a Ser de i weraene =f ott ts ts | status of the processor to be saved and restored later, which [1 [ofol|fo | LINK The status register is always stored in the lower byte of the | Fiag2 | Fe a ee cca cpmoperemmas ~—~ott 1? | the upper Ovte unchanged or loeded wih al Zenos = L_1 | © | + | + [ras | rospectively. “LOW means CT is forced LOW The Load Status instructions are included in the single ‘operand and two operand instruction types. sTaTUS ‘The Test Status instructions contain a single indicator which ‘specifies which one of the 12 possible test conditions are to 15141912 98 54 0 bbe placed on the Conditional-Test output. Besides the eight bits in the Status register (QZ, QC, ON, GOVR, QLINK, — =/ST [o [ous] 101s [ior] opcode ‘QFlag!, OFlag 2, and QFlag3), four logical functions (QN @ selected. These functions are useful in testing results of Two's Complement and unsigned number arithmetic operations. The status register may also be tested via the bidirectional T bus. svsta [B/W] Quad] 0111 | 1010 | RAM Address/Dest The code to test the status register via T bus is similar to the code used by instruction lines I; to 1g as shown below. instruction lines Ip - 4 have priorty over T bus for testing the SSTNA | B/W [ovaa] 0111 [1010] Destination STATUS INSTRUCTIONS [rameter [ow [owe [rete coor ‘SONGZ ‘Set OVA, N, GZ oo101 SL ‘Set LINK SETST 00110 Se Set Fest 1001 2 lage

01010 SF3 Set Fiag3

[_tretruction | ew | ved] [| Oeode ‘0011 RONGZ Raset OVA, NC, Z

00101 RL Raset LINK

RSTST 1010 00110 RY Reset Fiagt 1001 fed Rosot Flag2

1010 FS Reset Flag’

[_tnetruction [ew [qua | | RAM Addrese/Dest

100000 O00 RAM Flog 00

‘00000 NAY Y Bu [sen Pe [oe [om [ooo [ae

Cimtaston [ew [ome TT Ooeede CH an BC Tea OMIT

00010 TNO Test NSOVR

00110 TOVR Test OVR

gong) TORR ree oon Test Ww 01010 Te Test C 01100 arse} Test 2+T Note: TEN - test status instruction has priority over T; 4 instruction. Y BUS AND STATUS - FOR STATUS INSTRUCTIONS {simton [opcode | —ecenpion—[orw] v= bun [Fas [inst [rng uve [ove] w Te [= | [sone [exon NG Z jorefutmincwm [we frotrotnots [iti {s | [Cnc [owo [no [1 [ne [6 [NO [NG] serst [sev [set Feet [Cnc [no [1 [ne [nee ne [NC [seo [sor rege | [Cne[—[ Nene new [ne |W [Sra [sot regs | [fone [no [nen [ne | Ho |W Towra [re wo [ ne [nef ofofofo | a [one—[-ne“[-ne | 0 | we [we [weno astst [cne—[-ne—[ 0 | ne ne [ne [ne [ne [are [Resor Fags | [Cnc [~ Tne [-ne [neo WoW] ae a [Bem | fomesume (tre [Yeren see” | ve | ve [ve | ne [ve [ne [nen [Re [ ne NEWS| WW We [Cie [none | ne [6 | ne Non [cre [-ne—[ "ne [ no-no en ne | [one [ono | NG [ne [ ne" | no [We [NC [now [Tes tow | [ne —[ ne] ne [ne ne [ne [we ne Tost [ore —[-ne— [nen ne [ne we n [cre [wo] no -ng_[ ne [nc] ne [NC] a [Cre [no-no [Nene [ne | nen] [cne—[-ne“[-ne~[ n-ne [ne nn | [ne [ono [ne [ ne [ne |we [Wo [NC | [Ene [ne [none [n[e|wo|We [eT [no Te Tn ne [ne [ne U = Update Be ros 1=Set IZET 1s wen oct spcted in byte mode only the lower byte from the Y bus is loaded into the RAM or ACC and in word mode alll 16-bits from the Y bus are toaded into oo ma een fs Unt.

The NO-OP Instruction has a fixed 16-bit code. This instruction NO OPERATION FIELD DEFINITION does not change any internal registers in the Am29116. It 4514 19.12 98 54 0 preserves the status register, RAM register and the ACC rotoe woop Ce [| sooo [| vaio | coo] NO-OP INSTRUCTION ~ A [wor 0 | 00 08 000] Y BUS AND STATUS - NO-OP INSTRUCTION SRC = Source: U= Update NC = No Change 0= Reset 1=Set i= 0 to 15 when not specified *Y-Bus is undefined.

Instruction Type ‘Two Operand SOR Single Operand RAM TORAA Two Operand RAM, ACC to ACC SONR Single Operand Non-RAM TORIA Two Operand RAM, | to ACC TOR1 — Two Operand RAM (Quad 0) TODRA Two Operand D, RAM to ACC TOR2 — Two Operand RAM (Quad 2) TORAY Two Operand RAM, ACC to Y Bus TONR — Two Operand Non-RAM TORIY — Two Operand RAM, | to Y Bus SHFTR Single Bit Shift RAM TODRY Two Operand D, RAM to Y Bus SHFTNR_ Single Bit Shift Non-RAM TORAR Two Operand RAM, ACC to RAM ROTR1 Rotate n Bits RAM (Quad 0) TORIR — Two Operand RAM, | to RAM ROTR2 Rotate n Bits RAM (Quad 1) TODRR Two Operand D, RAM to RAM ROTNR Rotate n Bits Non-RAM TODAR Two Operand D, ACC to RAM BOR1 _ Bit Oriented RAM (Quad 3) TOAIR — Two Operand ACC, | to RAM BOR2 Bit Oriented RAM (Quad 2) TODIR Two Operand D, | to RAM BONR Bit Oriented Non-RAM TODA — Two Operand D, ACC ROTM Rotate and Merge TOAl Two Operand ACC, | ROTC — Rotate and Compare TODI Two Operand D, | PRT1 Prioritize RAM; Type 1 single Bit Shitt PRT2 Prioritize RAM; Type 2 PRT3 Prioritize RAM; Type 3 SHRR Shift RAM, Store in RAM PRTNR Prioritize Non-RAM SHDR Shift D, Store in RAM CRCF Cyclic Redundancy Check Forward SHA Shift ACG CRCR Cyclic Redundancy Check Reverse SHO Shift D NOOP —_No Operation Rotate n Bits Serer a se RTRA Rotate RAM, Store in ACC SySTN Seve Statue RAM RTRY Rotate RAM, Place on Y Bus RTAR Rotate RAM, Store in RAM sala save oe Non-RAM RTAR Rotate ACC, Store in RAM ost Status RTDR Rotate D, Store in RAM SOURCE AND DESTINATION RTDY Rotate D, Place on Y Bus RTDA Rotate D, Store in ACC Single Operand y SORA Single Operand RAM to ACC RTAY Rotate ACC, Place on Y Bus Ope R SORY Single Operand RAM to Y Bus TAA Rotate ACC, Store in ACC SORS Single Operand RAM to Status Rotate and Merge SOAR Single Operand ACC to RAM MDAI Merge Disjoint Bits of D and ACC Using SODR Single Operand D to RAM 1 as Mask and Store in ACC SOIR Single Operand | to RAM MDAR Merge Disjoint Bits of D and ACC Using SOZR Single Operand 0 to RAM RAM as Mask and Store in ACC sozen sre Operand pee) to RAM MDRI Merge Disjoint Bits of D and RAM Using OSE! Je Operand D{SE) to RAM as Mask and Store in RAM SORR Single Operand RAM to RAM MDRA — Merge Disjoint Bits of D and RAM Using SOA Single Operand ACC ACC as Mask and Store in RAM oD Single Operand D MARI Merge Disjoint Bits of ACC and RAM soi Single Operand | Using | as Mask and Store in RAM sOz Single Operand 0 MRAI —- Merge Disjoint Bits of RAM and ACC SOZE Single Operand D(0E) Using 1 as Mask and Store in ACC SOSE Single Operand D(SE) NRY —Non-RAM Y Bus Rotate and Compare NRA Non-RAM ACC CDAl Compare Unmasked Bits of D and ACC NRS Non-RAM Status Using | as Mask NRAS —_Non-RAM ACC, Status Mnemonics copyright © 1980 Advanced Micro Devices, Inc.

CDRI Compare Unmasked Bits of D and RAM SHDNZ Shift Down Towards LSB with 0 Insert Using | as Mask SHON — Shift Down Towards LSB with 1 Insert CDRA — Compare Unmasked Bits of D and RAM SHDNL Shift Down Towards LSB with LINK Insert Using ACC as Mask SHDNC Shift Down Towards LSB with Carry Insert CRA Compare Unmasked Bits of RAM and ACC SHDNOV Shift Down Towards LSB with Sign EXOR Using | as Mask Overflow insert Prioritize Loads ~ PRIA ACC as Destination for Prioritize Type 1 LDeNA Load 2" into RAM PRIY —_Y Bus as Destination for Prioritize Type 1 PRIR RAM as Destination for Prioritize Typo 1 LDC2NA Load 2 into RAM PRT1A ACC as Source for Prioritize Type 1 LD2NA Load 2° into ACC PRID Das Source for Prioritize Type 1 tony ‘a8 a aon PR2A ACC as Destination for Prioritize Type 2 loCeNY Plane 2 on ¥ Bus PR2Y —_Y Bus as Destination for Prioritize Type 2 PR3R RAM as Source for Prioritize Type 3 Bit Oriented PR3A ACC as Source for Prioritize Type 3 SETNR Set RAM, Bit n PR3D D as Source for Prioritize Type 3 SETNA Set ACC, Bit n PRTA Nonna? for Prioritize Type SETND Set D, Bit n PATD —_D as Source for Prioritize Type Non-RAM aN he ore aa Sate regeer PRA ACG as Mee for Promtize Type 2, 9, SFI Set Flag! Bit in Status Register PRZ Mask Equal to Zero for Prioritize Type SF2 Set Flag2 Bit in Status Register 2, 3, and Non-RAM SF3_Set Flag3 Bit in Status Register PRI | as Mask for Prioritize Type 2, 3, and RSTNA Reset RAM, Bit n Non-RAM RSTNA Reset ACC, Bit a RSTND Reset D, Bit n OPCODE RONCZ Reset OVA, N, ©, Z, in Status Register Addition RAL Reset LINK Bit in Status Register ADD Add without Carry REY Reset Flag! Bit in Status Register ADDC — Add with Cary RF2 Reset Flag2 Bit in Status Register ‘A2NA Add 2” to ACC RFS Reset Flag3 Bit in Status Register A2NR Add 2” to RAM TSTNR Test RAM, Bit n A2NDY Add 2" to D, Place on Y Bus TSTNA Test ACC, Bit n TSTND Test D, Bit n ‘Subtraction SUBR — Subtract R from S without Carry Arithmetic Operations - SUBRC Subtract R from $ with Carry MOVE — Move and Update Status SUBS Subtract S from R without Carry COMP Complement (1's Complement) SUBSC Subtract S from R with Carry INC Increment S2NR ‘Subtract 2" from RAM NEG Two's Complement S2NA Subtract 2" from ACC S2NDY Subtract 2" from D, Place on Y Bus Conditional Test TNOZ Test (N @ OVR) + Z Logical Operations TNO Test N @ OVA AND Boolean AND ard Test Zero Bit NAND Boolean NAND. TOVR — Test Overtiow Bit EXOR Boolean EXOR TLOW Test for LOW NOR Boolean NOR Tc Test Carry Bit OR Boolean OR Tz TestZ2 + T EXNOR Boolean EXNOR TN Test Negative Bit TL Test LINK Bit SHIFTS TF1 Test Flag! Bit SHUPZ Shift Up Towards MSB with 0 Insert TF2 Test Flag? Bit SHUP1 Shift Up Towards MSB with 1 Insert TF3 ‘Test Flag3 Bit SHUPL = Shift Up Towards MSB with LINK Insert Mnemonics copyright © 1980 Advanced Micro Devices, Inc.

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES DC Voltage Applied to Outputs For Military (M) Devices Stresses above those listed under ABSOLUTE MAXIMUM functionality of the device is guaranteed. RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating range unless otherwise specified; All APL and CPL products are included in Group A, Subgroup 1, 2, 3 tests unless otherwise noted. Typ. foe] ewe | tenemos [me Y Voc = Min. 0-15 ==1.8 mA-1.2 mA Y Voc = Min. al igh. = 16 mA/12 MA vi Guaranteed input Logical ial HIGH Voltage (Note 6) vi ‘Guaranteed input Logical . LOW Voltage (Note 6) [aT input Camp Votage | Voo=Min————[Arnputs—Jin==tema [18 | Vos | TW, =050 SRE ~0.50 DLE 71.00 Voc = Max. loot =1.00 th Input LOW Curent Vav= 0:5 Vos ‘gas =950 (Note 4) OEY -050 oF 2150 Tha 205s Yo-15 0.55 EN, 50 SRE 50 e 2 Voc = Max oe 1 Input HIGH Curent Vin = 24 Vos as | un (ote 4) Sey Hy oF 150 Tha 100 Yous 100 Veo = Max a Off State (HIGH Impedance) | Vcc = Max. Tha Output Current Vo = 2.4 Volts (Note 4) | Yo.15 ws Off State (HIGH Impedance) | Voc = Max 7, Ea A Voo= Max, +0.5 Volts [oe [ownsoncicacon [iets | | f= | |e | m | T= 0 tw 70° [ra=roro TT os mfr | | Fer an |e 2 $0) Power Supply Curent Voc = Max only) ZX a (am29116 — |(Note 7) on [row vesre ses) Notes 1. Typical Imits are at Voo = 50 V, 25°C ambient and maximum loading. 2. BP Sraitons shown a9 Min. of Max, use the appropriate valve specified under Operating Ranges for the applicable device type 3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. tT Yon ie Ty a are three-state outputs internally connected to TTL inputs. Input characteristics are measured under conditions such that the outputs are in the OFF state. 5, Worst case icc is at minimum temperature, 8: hase input vo prone zre oe iimunty and shed be eed ony na state, nooree onitonmant

Am29116 SWITCHING CHARACTERISTICS GUARANTEED CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE (Ta=0 to +70°C, Voc = 4.75 to 5.25 V, C_ = 50 pF) A. Combinational Delays (nsec) B. Enable/Disable Times (nsec) (CL =5 pF for disable only) [oa woom | «| - | To output | tzu | twat | tone | torz_| [ionssanstay) [77 [ee] = [oe | te Pe ps Po P| a cr ee ee ©. Clock and Pulse Requirements (nsec) a [Yous [eer | ee = [_tnput_[ min Low Time | min High Time _| DSI the delay too, 1g 00 an ouput can bo memos | Gterantoed eocty by ther tots : A D. Set-up and Hold Times (nsec) High-to-Low Low-to-High Transition Transition Set-up Hold Set-up Hold EO a [es@ata [|] | ah P lo-ssensta fo *|tae | mer | tw os [| TC | fexcow | | = Jove | = [oor of tminze] - Lomo of - [emo [eare | a TC a = GC a SX [ore ce tr to “Baus tier and accumulate Gestaliog ty

m29116 SWITCHING CHARACTERISTICS (Cont'd.) (All APL and CPL products are included in Group A, Subgroup 9, 10, 11 tests unless otherwise noted) GUARANTEED CHARACTERISTICS OVER MILITARY OPERATING RANGE (Tc =-55 to + 125°C, Voc = 45 to 5.5 V, C= 50 pF) B. Enable/Disable Times (nsec) A. Combinational Delays (nsec) (Cy = 5 pF for disable only) [von moto owt ete ere pyeineeelaelea eel Teaco [1m Tt | Fio-15 ATA) | 100 | toa | - | [or | tie |] 0] | 9 | [ios anstay [too [tos [so | a re ee ee C. Clock and Pulse Requirements (nsec) es a fone |e | [input [ win Low Time | Min High Time_] You1s musi be stored in the Data Latch and its source cisablod a 8 te aay to Yo, 15 an guut can be measured, i | “Guaranteed indirectly by other tests. D. Set-up and Hold Times (nsec) High-to-Low Low-to-High Transition Transition ‘With Respect to ‘Set-up Hold ‘Set-up Hold A SR fecommon [GER [owe [= Pe ee a a a loseunstay err ere 6 ewe [or | tof | ta abe feo [= f= fmm] [ure [em] [oor] = fmm a = CO ee = A OOS eS a toe er er ot “Trang Tor madato wnaweton for Wal apie **Status register and accumulator destination only. $= Not incuded in Group A tests

Am29116A SWITCHING CHARACTERISTICS GUARANTEED CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE (Ta=0 to +70°C, Voc = 4.75 to 5.25 V, CL =50 pF) A. Combinational Delays (nsec) B. Enable/Disable Times (nsec) [owas | —V—ew eee) a [ona moom [3 | Teo [| - | To output | tezn | tex | tenz | torz | [ots ara [sof - | [ o% | ww | w]e || 2 | [ons ensta) | sa [eo] 2) (oe | ts [os [elas] 2 | [oe | oe fw | a a a C. Clock and Pulse Requirements (nsec a ea (nsec) [rors | oe [ae [| [_imput_] min Low Time | Min High Time | before the delay to Yo_15 as an output can be measured. *Guaranteed indirectly by other tests. = D. Set-up and Hold Times (nsec) High-to-Low Low-to-High Transition ‘Transition ~ Set-up Hold Set-up Hold On [een acon | Geartow | wo? [TT [sey | A CA CE a ES few [f= Jur | = [uarfeoan] — foro] — evn [ea | [Ree eee a E'S, eS [ove ce iter 0g ce eae eT late ey

Am29L116A SWITCHING CHARACTERISTICS GUARANTEED CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE (Ta=0 to +70°C, Voc = 4.75 to 5.25 V, CL = 50 pF) A. Combinational Delays (nsec) B. Enable/Disable Times (nsec) won| | | - | To output tran | was | tone [ tz | [exsoa [om [oe |) es fm Pe a | loemsry [7 | je| [lo [ us Tae tote ts | a a cer a C. Clock and Pulse Requirements (nsec) [| [= | | [Yosser fe fd [input _[ Min Low Time | Min High Time_| fex___[ {Te a Yeats muha, sed he Date Lae a ee a es a uaay to Yor : PRcarrtood indscty by omer wes a a D. Set-up and Hold Times (nsec) High-to-Low Low-to-High Transition Transition With Respect to ‘Set-up Hold ‘Set-up Hold [esemnmn fr [wm Tome | - Tie [enwmwroon | Geter [oe [= [= [wot [Bsn | [onstage Se

5 CC C——

femiow | | - [oom | = [oar elena] - [ere] - [emie [eras | a CT | a <A | oe a a SN A Nc 7 | Tan ts adie namin for a oe **Status register and accumulator destination only.

Test Philosophy and Methods ‘Threshold Testing The following points give the general philosophy that we apply The noise associated with automatic testing, the long inductive to tests that must be properly engineered if they are to be cables, and the high gain of bipolar devices frequently give rise to implemented in an automatic testing environment. The specifics Secilations when testing high-speed circus These oscillations ‘of what philosophies are applied to which test are shown in the are not indicative of a reject device, but instead, of an overtaxed data sheet and the data-sheet reconciliation that follow. system. To minimize this problem, thresholds are tested at least Capacitive Loading for AC Testing once for each input pin. Treat, “hard” high and low levels _ df . this that function and ~ Automat tester and thar associated hardware have sry Mo und force tats, Generally is means hal uncon capacitance that varies from one type of tester to another, but ” is generally around 50 pF. This, of course, makes itimpossible ac Testing to make direct measurements of parameters that call for smaller capacitive load than the associated stray capacitance. ‘AC parameters are specified that cannot be measured accu- Typical examples of this are the so-called "float delays” that —_rately on automatic testers because of tester limitations. Data- measure the propagation delays in to and out of the high- input hold times fall into this category. In these cases, the impedance state and are usually specified at a load capaci- parameter in question is tested by correlating the tester to tance of 5.0 pF. In these cases, the test is performed at the bench data or oscilloscope measurements made on the tester higher load capacitance (typically 50 pF) and engineering —_by engineering (supporting data on file). correlations based on data taken with a bench setup are used to determine the result at the lower capacitance, Certain AC tests are redundant since they can be shown to be - ‘ fedicted by other tests that have already been performed. In ‘Similarly, a product may be specified at more than one capacitive pre Toad. Since the typical automatic tester is not capable of these cases, the redundant tests are not performed. switching loads in mid-test, it is impractical to make measure- ments at both capacitances even though they may both be Output Short-Circult Current Testing greater than the stray capacitance. In these cases, a measure- a a ment is made at one of the two capacitances. The result at the When performing los tests on devices containing RAM or registers, great care must be taken that undershoot caused by ‘other capacitance is determined from engineering correlations grounding the high-state output does not trigger parasitic bbased on data taken with a bench setup and the knowledge that Sjemanng te IETS Ren Ct change state. In tion. in OC tests are pe ” to facilitate this correla- order to avoid this effect, it is common to make the measure- ‘ment at a voltage (Voutput) that is slightly above ground. The ‘AC loads specified in the data sheet are used for bench Vcc is raised by the Same amount so that the result (as testing. Automatic tester loads, which simulate the data-sheet confirmed by Ohm's law and precise bench testing) is identical loads, may be used during production testing. to the Vout = 0, Voc = Max. case.

SWITCHING WAVEFORMS (Cont'd.) one vee || CR ‘ ee —— TER RRR RX rrnroe oat NOOR CREE ER TTTRTERERERLA NY BITRRRERN IRE mpm OOOOXNNXXXKRR ARR DORI XRAY y ROR me NW eereesecce Peactncenaeeresnenreceay ont) KR SR /-—-—»8. tia wroceseo Single Address Access Timing If the is satisfied, th1g need not be satisfied. one cveue FEAHUHUAHACEHWUUUS HHIHING, Oy [ocsRatnon KOO CERRO ate KBROK | RES RR SO A DISABLE ROSARY, SRK wnre ROAR SARA n wroces40 Double Address Access Timing

° te fot te ‘att Ped ~ im Terararecererererecacacenaceee, Kis Oe EERE) | ORE ‘lo-15 = INSTRUCTIONS: o_1 = OATA wro02ss0 Immediate Instruction Cycle Timing SWITCHING TEST CIRCUITS. A. THREE-STATE OUTPUTS B, NORMAL OUTPUTS Nee Vee Sp ‘Ry = 00 f s = Nour ooo . ny 200.0 / ms - . a Y I oo00421 ToRo1991 Notes: 1. CL =50 pF includes scope probe, wiring and stray capacitances without device in test fixture. 2. St, Sa, Sq aro closed during function tests and all AC tests except output enable tests. 3. S1 and Sg are closed while Sp is open for tpzy test. $1 and So are closed while S3 is open for tpzi_ test. 4. CL =5.0 pF for output disable tests.

SET-UP, HOLD, AND RELEASE TIMES PULSE WIDTH av ara Wy yyy tay 8mm sv wet AA !CUAAW Mee AWWW ts MW. “| a * av fo ty ' wenc2970 weR02790 Notes: 1. Diagram shown for HIGH data only. Out put transition may be opposite sense. ENABLE AND DISABLE TIMES 2. Cross hatched area is don't care condi- tion. Enable Disable sy PROPAGATION DELAY cOnTROL — —— f — isy \\ fly swnnaee_ sy se asy our come | oy cum OPPOSITE PHASE: . wrRoz660 ineoT TRANSITION RO Notes: 1. Diagram shown for input Control Enable- ov LOW and Input Control Disable-HIGH. 2. S1, Sg and Sg of Load Circuit are closed werozae0 cept where shown Note: 1. Pulse Generator for All Pulses: Rate <1.0 MHz; Zo 50 9% <25 ne; <2 ns, KEY TO SWITCHING WAVEFORM =o oer owe Igy may cnance WELBE FROML TOW FROME TOW WW Ss er sae Be poesnor Ene sh 000070

INPUT/OUTPUT CURRENT DIAGRAMS TTL Vee weur a peut B EN 18K OET 10K SRE 18K OLE *K loa 9K 16-15 bd Oey 18K cP eK Th 18K ‘TC003062 C\\*50 pF, all inputs THRE STATE | wonMiAL Vee 1CR00521 Co *5.0 pF, all outputs Note: Actual current flow direction shown, c J

Am29116A System Cycle Times SYSTEM BLOCK DIAGRAM DATA PATH TIMING ANALYSIS L ‘Without Any External Logic ALU R ares) bce i Bnst res] ‘Cycle Time: oe b. Pipeline stor (29821) cP-Q 12 ns MAPPING PALU Gorey ev 5 r wm tance an cn SEQUENCER STATUS] a Pipeline Register (29821) CP-Q 12 ns Tf] COMUX’ Multiplexer (F157) ‘Sob 15 d : Sta Fi aw! Satp* ¥ Cycle Time: si b. Pipeline Register (29821) CP-Q. 12 ns RALU (291164) -Y 53 Cycle Tine: oe or T= Te IM, Using Y-Bus as Input/Output in One Cycle oo vrengoe mon eee ie Source Select (29821) OE-Y 15 Destination (29621) ‘Setup 4 = — athe DLE can go LOW 6 ns (Y to DLE Setup) after data is valid on You ties “45 ns after CP 1). OEy should go LOW betore 68 BDOOS9S0 —_<¥ele will work at 90 ns with DLE tied to OEY to CP.

CONTROL PATH TIMING ANALYSIS Am2910A = Am29112,- Am29331 Type (est) (est) 1. Pipeline Register (29821) Branch Map Mapping PROM (2751904) Register (29821) oP 12 ns 12 12 ‘Sequencer Dy 20 23 19 Controt Memory wa 0 40 40 — Pipeline Register (29821) Setup 4 4 4 Cycle Time: 76 Tw. oe N.—Pipetine Register (20821) ora 12 12 12 Branch Buttor Enable (2959) OEY 20 20 NA ‘Sequencer DY 20 at 20 Control Memory tw 40 40 40 Pipeline Register (20821) Setup 4 4 4 Cycle Time: . +. 76 tt, Pipeline Register (29621) cr-a 1 12 2 Conditional RALU (291164) Tcr 23 Es 29 Branch ‘C-MUX (2323) ow 7 7 NA Polanty (74888) ay " NA NA ‘Sequencer coy 30 26 23 Control Memory tea 40 40 40 Pipeline Register (29821) Setup 4 4 4 Cycle Time: ie Te 08" IV. Pipeline Register (29821) oP 12 2 12 Conditional CC-MUX (2823) Sow 15 15 NA Branch Using Polarity (74886) Dy 1" NA NA External Status Sequencer coy 30 6 23 Register Control Memory ea 40 40 40 Pipeline Register (29821) Setup 4 4 4 Cycle Time: Tz wT Ww _ V. Pipeline Register (29621) oro 12 2 12 Instruction to Sequencer Ky 35 35° 20 Output Path Controh Memory (eoe2 tea 40 40 40 Pipeline Register " Setup 4 4 4 Cycle Time: oy ww. TT. VI Sequencer op-y 40 31 24 Clock to Sorc Manor see w “0 40 40 Output Path Pipeline Register (29821) up 4 4 cycle Time: . . - * For the Am29112 Instruction 18 (Tost SP with O (TSTSP.P)) is not used. It Instruction 18 is used O-Y is 35 ns and LY is 47 ns. **For the Am29112 Relative Branch Instructions are not used. If the Relative Branch Instructions are used D-Y is 43 ns,

THE USE OF AN EXTERNAL STATUS REGISTER IN REDUCING MICROCYCLE LENGTH The standard connection of the CT pin of the Am29116 and microcycle length calculation arising from that connection are shown below: CRITICAL PATH TIMING (FIGURE A) CRITICAL PATH TIMING (FIGURE B) Maximum Maximum ‘Commercial Commercial Delay (ns) Delay (ns) Pipeline Register cP-Q 12 “Am29621 Status Reg OPY 12 ‘Am2923 CC-MUX ow 7 74886 Polarity DY W ‘Am2910A cc-Y 30 Control Memory taA 40 —ee we Cote ee The cycle time has been reduced from 183 ns to 112 ns. cr TEST. Am2910A CONDITIONS bo- hb yy wats PROM REGISTER OTHER ‘SIGNALS ‘BD005960 Figure A. Am298XX_ fe eerkon fe eT de T wa SEL {—~ NEWPATH EXTERNAL MICROCODE TEST PROM Figure B.

PHYSICAL DIMENSIONS (Cont'd.) TD 052 ee ; aig! ope MAX. =| [05 me, Tn ee el ee fo crates +s as. TDX052 Fo | Fre wax IL osm. Ta ee cl oe T sors te TR Sl 7

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