AM2910A

AM29112 AMD | Alldatasheet

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microprogrammed machines and optimized for the new microcode. state-of-the-art ALU's and other processing components. Figure 1. Am29112 in a Single Pipelined System. 3

| RELATED PRODUCTS | | [Pat No. [Description | [Anaoii6 [A 168 Bplay Meopeamm | | | [ Am29114 | Vectored Prionty Interrupt Controller

| PIN DESCRIPTION |_Pin No. [Name [v0 [Description a [rer] 70 Brectonal mereronram adtess bos outputs Mroprepram sd658 and mputs rior vec. | [moma [1 | Mutway inet is for up > T6way brates ET Stair | ‘Aiso, the CMUX output is selected at the incrementer input [Fest puter sequincer Geo Table 2) [Tevet 1 [rest erat for te soasneer. (Gee Tab 2) [Po.__ | |_| Polarity input for test. (See Table 2) et Fi [sts [1 cont nga Sit one of Wee modes poral exended or Tred conte. Soe Tate 1) | [|siienin [oT inscats sack oven ovundoow [font TT | Unmaskabie interupt request input [INTRA | 1] Maskable interupt request put [nto [1 [sabe for maskable interrupts. [frat 0 | ast etouptackowiedge [iss 1 regan ie wast sgn! ei whon hgh moat agncan dip wan ow |__| [sua orev fon iene sek i nor an | maskable interrupts a [reo 10 [rectal aor 10 no a eacadea AnBOT BR [ecto 110 recone program counter 170 ine fer cascaeg ANgOTV@R [Joo 0 “fBisrectona cout V0 tne for cseaded AnzOHi26 [ Tezio | v0 [ Bicrectonal counter zero VO tine for cascaded Am@etizs

microprogram memory. A single register at the output of the next microprogram address. ‘executed, while the next is being fetched. External conditions The emergency detect circuit generates an unmaskabie inter. interrupt request (MINTR) to the Am29112, which acknowl handling is discussed in a later section. Figure 2. Control Path in a Single Pipelined System Using the Am29112.

condition code inputs. The next microprogram address is from the D port of the Am29112. chip on power-up for compatibility with the external hardware to the O port. Figure 3. Am29112 48-Pin Package.

TABLE 1. MODE CONTROLS and register, and interrupt groups of instructions. For these Continue | instruction regardless of instruction, shared for these instructions (see Figure 4 and Table 2). condition code, and multiway inputs. ‘on cascaded Am29112s function independently, and it is ro. mode, however, the counters on cascaded Am29112s behave Figure 4. Condition Code Circuit. between the counters degenerate into identical instructions.

[“opeose tan) | Gonation | _wnemone [beeps J 0 x JZ.U UNCONDITIONAL JUMP ZERO 1 PASS PUSHD.P PUSH D (PASS) ij 1 FAIL LDCMD.F LOAD COMMAND REGISTER FROM D (FAIL) 2 COND POP.C POP; CONDITIONAL STACKOUT TO D 3 COND CuD.C CONDITIONAL JUMP D- 4 COND CJSD.C CONDITIONAL JUMP SUBROUTINE D 5 COND CJUMW.C CONDITIONAL JUMP MULTIWAY D- 6 COND CJSMW.C CONDITIONAL JUMP SUBROUTINE MULTIWAY D 7 COND CRTN.C CONDITIONAL RETURN 8 COND: PUSHPL.C PUSH PC; COND LOAD LOWER COUNTER 9 COND LOLC.C LOAD LOWER COUNTER; COND PUSH COUNTER 10 x POPLC.U POP TO LOWER COUNTER WwW PASS RSTSP.P RESET STACK POINTER (PASS) an FAIL LOINTV.F LOAD UNMASKABLE INTERRUPT VECTOR (FAIL) 12" PASS RFCTUP REPEAT LOOP, UPPER COUNTER = 0 (PASS) 12° FAIL RFCTLF REPEAT LOOP, LOWER COUNTER = 0 (FAIL) 137° PASS RPCTU.P REPEAT PIPELINE, UPPER COUNTER =0 (PASS) 137° FAIL RPCTL.F REPEAT PIPELINE, LOWER COUNTER = 0 (FAIL) 14 COND LOOP.C TEST END LOOP 15 PASS: ENINT.P ENABLE INTERRUPTS (PASS) 15 FAIL DISINT.F DISABLE INTERRUPTS (FAIL) 16°** COND TWBL.C THREE-WAY BRANCH, LOWER COUNTER a7 COND TWBU.C THREE-WAY BRANCH, UPPER COUNTER 18 PASS TSTSP.P TEST SP WITH D (PASS) 18 FAIL TSTMT.F JUMP D IF STACK NOT EMPTY. 19 COND CJDF.C COND JUMP D/STACK AND POP: 20 COND CUSDF.C COND JUMP SUBROUTINE D/STACK AND POP 21 COND CJMWR.C COND JUMP MULTIWAY RELATIVE D 22 COND CJSMWR.C COND JUMP SUBROUTINE MULTIWAY RELATIVE D 23 COND CUPP.C COND JUMP PIPELINE AND POP. 24 COND PUSHPU.C PUSH PC; COND LOAD UPPER COUNTER 25 COND LDUC.C LOAD UPPER COUNTER; COND PUSH COUNTER 26 PASS: POPUC.P POP TO UPPER COUNTER (PASS) 26 FAIL POPDW.F POP TO DISPLACEMENT WIDTH (FAIL) 27 COND LDDW.C LOAD DISPLACEMENT WIDTH; COND PUSH DW 28 COND CJR.C ICOND JUMP D PC REL 29 COND CJRN.C ‘COND JUMP D PC REL NEGATIVE 30 COND CJSR.C COND JUMP SUBROUTINE D PC REL 31 COND CJSRN.C COND JUMP SUBROUTINE D0 PC REL NEGATIVE * These instructions are identical in the extended mode. “*These too. ***These too. Extensions: U - unconditional; C - conditional; P - PASS condition; F - FAIL condition. Note: PASS/FAIL condition can be produced as follows. P stands for polarity and | for input: se rr] xp [era] Lobe be [cow]

0 Jump Zero (JZ.U) 1 Push D (PUSHD.P) 1 Load Command Register from D (LDCMD.F) oo EN Py oe ” 0 st oF o sc 2 20 stack COMMAND REGSTER e so 9 n s n F000600 PFo00620 PF000611 UNCONDITIONAL FORCED PASS FORCED FAIL 2 Pop and Conditional Stack- 3 Conditional Jump D (CJD.C) 4 Conditional Jump Subroutine out to D (POP.C) D (CJSD.c) ry ” a 2 ‘stack 2 « = 33 co © o © a Sront « oer * +e 3s « (+2 %6 (+2 PASS 70 (+3 wv (+3 PFO00571 rae Pass Fa Pass PFO00S60 PF000590 CONDITIONAL CONDITIONAL CONDITIONAL 5 Conditional Jump Multiway D 6 Conditional Jump Subroutine 7 Conditional Return (CRTN.C) (CUMW.C) Multiway D (CJSMW.C)

0 STACK

“ ee ad W a na ‘otxcx Fy 2 a B= 88 Ma? ee D= 86 M=2 PASS a 82 ec 82 7 hd Ma 83 20 2 2 ror “ as os ee om » 6 as es oF 8s 2 FAIL PASS: FAR a PF000550 F000560 FAL Pass PF000540 CONDITIONAL CONDITIONAL CONDITIONAL

8 Push PC and Conditional 9 Load Lower Counter and 10 Pop to Lower Counter

Load Lower Counter Conditional Push Counter (POPLC.U) (PUSHPL.C) (LDLC.c) 2s @ Fa ©) ” | »@ ‘stack 2 (UNCONDMTONAL) Lowen counren / 2 39 OC nconomonaty «<@ 2 ©) 3A 40 20} Lowen counren 20 Gounres) “ Ceracn) hal mass, ae ‘STACK “ LOWER COUNTER Pass PFOOO511 PFO00521 PFO00531 CONDITIONAL CONDITIONAL UNCONDITIONAL

11 Reset Stack Pointer 11 Load Unmaskable Interrupt 12 Repeat Loop, Upper Count-

(RSTSP.P) Vector (LDINTV.F) er (RFCTU.P) " x 2 stack ~ 2 a ©) | « 2 Pay UPPER COUNTER © STACK POWTER 2 wwrvect s Aecrsten Fs EY 27@® Por ES F000460 PF000470 F000790 FORCED PASS FORCED FAIL FORCED PASS

12 Repeat Loop, Lower Count- 13 Repeat Pipeline, Upper 13 Repeat Pipeline, Lower

er (RFCTL.F) Counter (RPCTU.P) Counter (RPCTL.F) 4a STACK * 16 cy 7 v7 ‘PPER COUNTER Towen counren ac LOWER COUNTER * * o rs pew w o-w aE 2 2 ro Fy Fa so Por 2 2 Fa | prooos40 PF00851 PFo007e1 | FORCED FAIL FORCED PASS FORCED FAIL

14 Test End Loop (LOOP.C) —_15 Enable Interrupts (ENINT.P) 15 Disable Interrupts (DISINT.F) Tacx. Ey ES 2 2

2 Fa 2 2

2 14 “ sa g POP 1s ENABLE Py DISABLE MASKABLE MASKABLE Ps INTERRUPTS. INTERRUPTS ones PFo00430 PF000390 Pro00421 CONDITIONAL FORCED PASS FORCED FAIL 146 Three-Way Branch, Lower 17 Three-Way Branch, Upper 18 Test SP with D (TSTSP.P) Counter (TWBL.C) Counter (TWBU.C) « ‘STACK “ ‘STACK o ‘STACK e « c2 $ave Por “a Fan ry rm 3 “6s “ « a « al Fai al Fa cs @ «7 vestsewmno © o) 40 9 Pass 40 P PASS “ +t (+t ac “ “ oa (+2 nor a oes ea ewoucn | exouan Prooo411 PF000411 PF000400 CONDITIONAL, CONDITIONAL, FORCED PASS

18 Jump D if Stack Not Empty 19 Conditional Jump D/Stack 20 Conditional Jump Subrou-

(TSTMT.F) and Pop (CJDF.C) tine D/Stack and Pop (CJSDF.C) stack STACK 4s so PoP a POP STACK nm “ UNCONOMONAL a" rowes ” 70 9ST) ) 70 97mm} 65 c) a ° ne ero+t et ne Emmet +t « Os ny m+? (+2 RP sms? +2 “a (+2 3} (sMm+3 BP sTMK+3 stack STACK Fait Pass FAL Pass EMPTY NOT EMPTY (stack) (c) (stack) © PFOO0660 PFOO06S1 PFO00681 FORCED FAIL CONDITIONAL CONDITIONAL

| 21 Conditional Jump Multiway 22 Conditional Jump Subrou- 23 Conditional Jump Pipeline Relative D (CJMWR.C) tine Multiway Relative D and Pop (CJPP.C) | (CJSMWR.C) mex ba POP STACK " “0 a “ ease 2 a2? ° 1s * s ® mM eo ry eo ” © ow (0) +2 mots me onats prooo7e0 CONDITIONAL CONDITIONAL CONDITIONAL

24 Push PC and Conditional 25 Load Upper Counter and 26 Pop to Upper Counter

Load Upper Counter Conditional Push Counter (POPUC.P) (PUSHPU.C) (LDUC.c) = © iad © “a OK onconbeionar PS UNCONDMOWAL e n 0 @® ac®. = 1 umensauren at “Gone of Ged » Be * — te} unre cocwren 1” xe me « PFO00730 PFO007 10 PFO00770 CONDITIONAL CONDITIONAL FORCED PASS

26 Pop to Displacement Width 27 Load Displacement Width 28 Conditional Jump D PC

(POPDW.F) and Conditional Push DW Relative (CJR.C) (LDDW.C) n ” © a Simrranen one n® 19QX unconorrionaL « n Gacn) 8 ac dame nponess 6 ” DwiDTH REG 1c Ga) ry © mt ‘ pronoren pr000740 pr000780 FORCED FAIL CONDITIONAL D** is displacement (see Note 1). CONDITIONAL

29 Conditional Jump D PC Rel- 30 Conditional Jump Subrou- 31 Conditional Jump Subrou-

ative Negative (CJRN.C) tine D PC Relative (CUSR.C) tine D PC Relative Negative (CJSRN.C) “ ee “an ° “ns ovens a STACK ny stack Pass orn? PASS, aol “ “ol ot = -2 “c JUMP ADDRESS 1S. o ue “ ‘JUMP ADDRESS 1S o ame noo ° um aooness 8 © oes Fa Fai PF000490 PF000480 PF000500 D =-2, should be two's compie- Dis displacement (see Note 1). D** =-2, should be two's comple- ment (see Note 2). CONDITIONAL ment (see Note 2). CONDITIONAL CONDITIONAL Notes: 1. The number of bits of D used as displacement is stored in DWIDTH register. The remaining high order bits are zero-extended. 2. The number of bits of D used as displacement is stored in DWIDTH register. The remaining high order bits are ‘one-extended. BRANCHING INSTRUCTIONS If the displacement width register is loaded with any value greater than 8, it is exactly as if it were loaded with 8. Direct Branching Instruction 28 (29) is the relative jump (jump back) instruction, Instruction 0 is the unconditional jump to zero instruction. This ang instruction 30 (31) is the relative jump to subroutine (ump instruction also resets the stack pointer and the interrupt logic back to subroutine) instruction. For backward relative branch- as well as setting command register as follows: CR()= 1, 6, the displacement must be coded as a two's complement CR(1) = LSS, CRI2) = 1 negative number. When the displacement width is the same as Direct branching is implemented by instruction 3 (COND JUMP ‘the microaddress width the forward and backward relative D) and 4 (COND JSB D). The branch address is input through ‘P*anch instructions are identical. When the displacement the D port. If the condition is PASS, the branch is taken, width 1s less than the microaddress width, the more significant otherwise the sequencer executes a continue, Two-way direct bits of D outside the displacement are forced to all zeros for branching is implemented by instruction 19 (COND JMP D/ _PdStive branches and to all ones for negative branches. This STACK) and instruction 20 (COND JSB D/STACK). It the ‘8 effectively sign extension except thatthe sign information is condition is Pass, the branch address is taken from the D input. contained in the instruction rather than the displacement, and port, otherwise, the branch address is taken from the stack. In__ there is no need for sign information to propagate between Cithor case the stack is popped. This instruction assumes that 4Scaded chips since it is assumed that the displacement the alternative address was pushed on the stack by a previous _idth registers inthe two chips have been consistently loaded instruction. Jump to subroutine differs from JUMP in that the PC register is pushed on the stack. This enables the subrou- The disadvantage of having the sign information in the tine to use COND RETURN (7) to return to the point of call, __instruction rather than the displacement can be overcome by a Note that the two-way jump to subroutine (20) causes a _ judicious choice of instruction format. The opcodes for forward simultaneous pop and push so that the stack pointer is and backward relative branch instructions have been chosen Unaffected but the top of stack element is replaced by the _10 differ in the least significant bit position only, with a ‘O" in return address. that bit for forward branches and a '1" for backward branches. If the sequencer instruction field is contiguous with and on the Relative Branching more significant side of the displacement field in the pipeline register, then the least significant instruction bit is like the sign In the relative branch instructions, a dynamically alterable bit for the displacement for relative branch instructions. This subfield of the D inputs is added to the PC to form the branch permits the assembler to use the same opcode for forward address. The remaining most significant bits of the D inputs and backward relative branch instructions, but overlap the are ignored and internally converted to all O's for forward displacement field (now declared to be one bit longer than the branches and ali 1's for backward branches. The displace- actual displacement field in the pipeline) with the sequencer ment width (OWIDTH) register in the Am29112 holds the instruction field by one bit. If the assembler now generates a number of least significant bits of D that participate in the negative displacement, the sequencer opcode formed is the relative branch as the displacement, and can be loaded from backward branch; while if the displacement is positive, the the lower four bits of the D port. In cascaded systems, the sequencer opcode formed is forward branch. displacement width has to be loaded consistently in the two chips. For example, for a displacement width of 9, the lower When the instruction is executed, the PC already has been order chip gets a displacement width of 8 and the higher order incramented and points to the next sequential instruction, chip gets a displacement width of 1. As another example, ithe hence a forward branch with a displacement of O causes the | ower order chip has a displacement width of less than 8 bits, ext sequential instruction to be executed. the higher order chip must have a displacement width of zero.

| Multiway Branching ‘address on top of stack. This frees the D inputs for other use, i . but makes it necessary to push the address of the start of the wo variants of multiway branching are available on the jon on the stack batee entering the loop. Also, if the loop is | Am2a112 — muitiway substitute O and multiway relative D. In terativitis necessary to load a count value in the counter at Imuttway substitute D the 4 multway inputs directly replace the the samo time, Inavovone oa (PUSH PC: COND LOAD eeas clgnticant bits of the branch address input at D. pen COUNTER) and 8 (PUSH PO, COND Lone LOWER Instruction 6's a conditional multway branch and instruction COUNTER) combine both ween requirements. @ conditional multiway subroutine call, In these instructions, the least significant 4 bits of the D input port are not used by _Instruction 14 implements a simple conditional repeat loop. If the sequencer, and may be shared, for instance to select the condition is FAIL the sequencer loops back using the top among different sets of multiway inputs. of stack address, and if the condition is PASS, the sequencer Performs a continue to the next sequential address, and Multiway branching has the disadvantage that the jump table simultaneously pops the stack to remove the address of the must be aligned on a 16 word boundary. This disadvantage is jogp head. The instruction may be described in Pascal-like overcome in the Am29112 multvay relative branching instruc Syntay as tions. In these instructions, the number input on the multiway pins is added to the branch address input at D. Instruction 21 repeat PUSH PC is a conditional multiway relative branch and instruction 22 a LOOP BODY conditional multiway relative subroutine call, until condition = TRUE; One of the advantages of multiway branching is that it enables _Instruction 23 (COND LOOP EXIT) implements a loop exit that @ 16 way docision to be made in exactly one microcycle, May be used with any of the Am29112 loop instructions. Itis a However, the 16 target addresses are constrained to be Conditional jump to D, which simultaneously pops the stack. If contiguous in memory. Hence, if the target routines need more the condition is FAIL, it simply performs a continue. than one microword each, as is vary likely, they are addressed as giscussed earlier, the counters present in cascaded indirectly through a table of 16 contiguous branch instructions. amagii2e, may be used independently or cascaded as a For very high speed applications, the extra microcycle needed single 16-bit counter under microprogram control. The mode {0 branch indirectly off the jump table may not be acceptable. t= select the cascaded configuration only in the extended This penalty is avoidable if the multiway bits are offset with mode, There. are separate repeat and three-way branch respoct to the D imputs. When two cascaded Am29112s are instructions for upper and lower counter. In tho eouenns the used, Inere are two sets of 4-bit multivay inputs. The least repeat instructions, the condition code is deed te Onoe tne Significant chip has a muitiway input with no offset, while the between the repeat on tre upper and the repeat on lower ‘Tost Significant chip has a multiway input with an B-bit offset. Counter (a condition of PASS sects the upper counter). In the The Amz29112 command register has a bit CR(1) that enables Case of tho three-way branch whch neste ine condition code or Gisables multway branching on the chip: in a system with input for the external condition, ters’ are ine separate wo cascaded Am20112s, each chip has a command register Gocodes for three-way branch on upper (opcode 17) and bit Multway branching may be disabled in either chip by —_threeway branch om loner (opcode 16). When a single resetting the command register bit on that chip, or enabled by —_4m29112 is used only the repoat on lower counter instructions Saxena she command register bit. When multiway branching 6 are. useful; and when two AMZBt oe we kecceded os disabled on a chip, for that chip both multiway and multiway Sperated in the extended rode. the tepeat instructions on ota ranches are converted to direct branches, and the upper and lower counter are identical m effect and bor Imultiway inputs are a Don't Care. Multiway branching with an operate on the 1ésbit cascaded oot rner B.bit offset is implemented by disabling multiway in the least significant slice and enabling it in the most significant slice. In Instruction 12 (REPEAT LOOP iF COUNTER NOT ZERO) is. this case, the 16 target addresses are dispersed in memory, _the iterative analog of instruction 14 (CONDITIONAL REPEAT Separated by 256 locations each. Another useful configuration LOOP), Instruction 8 (PUSH PC; COND LOAD COUNTER) is is obtained by enabling multiway on both chips. In this case, up used with condition code as forced PASS and the desired to 16 sets of target addresses are dispersed in memory, count in the D field of pipeline. This causes the address of tho separated by 256 locations each. loop head to be pushed on the stack, and the lower counter loaded with the count. At the end of the loop body, the repeat The Amz9112 does not have an unconditional continue in its ingtruction checks if the count is z6ro. I it ve nee zero, it trecton set This is not expected to be a drawback because performs a loop back using the top of slack aodroce ond {he instruction set requires that both unconditional PASS and simultaneously decrements the counter il itie zero pops the unconditional FAIL are programmable by the sequencer to address of the loop head off the stack and simultaneously select among different instructions sharing the same opcode. selects the next sequential address thereby exiting the loop. A Hence, a continue 's obtained by executing instruction 3 repeat ioop on the uppor counter car teat up using (COND JUMP D) with a forced FAIL condition. instruction 24 instead of 8 to push PC and load upper counter and using instruction 14 to loop back with condition code as LOOPING INSTRUCTIONS forced PASS. Note the potential off-by-one error: since the The looping instructions on the Am29112 are of two kinds: count is checked before itis decremented, a count of 1 causes Conditional, which depend on an external condition to signal two iterations: the first iteration finds ‘a count of 1 and loop termination, and iterative, which decrement the Am29112 decrements; on the second iteration the count is found to be Counter and check for a count of zero. There is also a three- zero. and the loop terminates, Hence. the value of count way branch instruction that combines the check for external loaded should be one less than the desired number of condition with the check for count of zero in a single iterations. In the example above, loading the counter with 7 instruction. resulted in 8 iterations. All the looping instructions are similar in two respects. Firstly, The single instruction repeat (instruction 13) is provided for the check for the loop condition is done at the end of the loop. _ applications where the loop body is a single microinstruction, THis implies that the loop body is always executed at least _for example, an ALU shift. The loop is set up as belore using once. Secondly, in the case that the loop has tobe repeated, a _ instruction 9 or 25 (LOAD COUNTER AND COND PUSH backward branch to the loop head is made by using the COUNTER). The repeat instruction then presents its own

‘address to the D inputs of the sequencer. As with the repeat. COND STACKOUT TO D) with a forced FAIL condition and loop instruction, the single instruction repeat checks for instruction 18 (COND TEST SP/BRANCH STACK NOT EMP- counter = 0. If the counter is equal to zero, it continues to the —_—‘TY) also with a forced FAIL condition. The branch instruction next sequential instruction; otherwise it repeats the address _ performs a branch to D if the stack is not empty. presented to the D inputs, which is its own address, and decrements the count by one. Instruction 13 can also be used _‘[he stack nesting level in an interruptible sequencer varies in place of instruction 12 where there is no stack location cynamically. Hence. tne Amores Provided with te (COND for checking the available stack space: instruction available to hold the address of the loop head. TEST SP/BRANCH STACK NOT EMPTY). Two distinct in- Often it is necessary to repeat an action until either some structions for testing the stack pointer have been packed into external condition becomes true or a predetermined count is _ the same opcode and are differentiated by the condition code. reached: for example, searching a character string for an A condition code of PASS selects the Test Stack Pointer ‘occurrence of some character. The three-way branch instruc-_ instruction. in this instruction, the sequencer tests the stack to tions of the Am29112 combine the test for count and external _see if there is enough space, as determined by a constant condition in one cycle. At any loop iteration, if the condition _input at the D port; if there is enough space, the sequencer becomes PASS when the three-way branch is executed, then performs a continue, whereas if there is not enough space, the the sequencer performs a continue to the next sequential ‘sequencer performs a subroutine return. The number of stack instruction, and pops the stack. If the condition is FAIL when —_locations required is input at the D port. In a system with only the three-way branch is "xecuted, the sequencer tests the one Am29112, the least significant 6 bits of the D are used ‘count. If the count is zero, then the search is unsuccessful and within the chip for this instruction. In a system with two the sequencer performs a branch to the address input at the D cascaded Am291 12s the determination is made independently port, simultaneously popping the stack. if the count is not zero, _in the two chips (since the stack pointer is at all times identical and the condition is FAIL, the sequencer performs a loop back —_in the two chips). Hence, the same number must be presented Via the stack. The instruction always decrements the counter _to the two chips. The adders in the two Am29112s are not by one if the counter is non-zero. cascaded for this instruction but function independently. in Since interrupts may occur at any point in the execution of Doth Am29112s only the 6 LSBs of the D port are actually microcode, itis necessary to be able to save counter values US@d in the comparison. ‘on the stack so that the interrupt routines can use the counter. |NTERRUPT HANDLING without interfering with the operation of the interrupted code. The sequencer provides instructions that permit arbitrary The Am29112 recognizes two kinds of interrupts: maskable nesting of loops and subroutine calls. Instruction 9 (LOAD and unmaskable. Maskable interrupts cause automatic saving LOWER COUNTER; CONDITIONAL PUSH COUNTER) can __ of status on the internal stack and can be inhibited, either be used to load the lower counter from the D port. If the externally via the INTERRUPT DISABLE pin, or internally via condition is PASS, then the instruction also causes the old instruction 15 (COND ENABLE/DISABLE INTERRUPT). In counter value to be pushed on the stack. To restore the addition, maskable interrupts are disabled when there is not counter from the stack, instruction 10 (POP TO LOWER —_ enough space on the stack to service the interrupt, though this COUNTER) can be used with a forced FAIL condition, internal inhibit can be overridden be clearing a bit in the Instructions 25 (LOAD UPPER COUNTER; CONDITIONAL command register. The unmaskable interrupt, on the other PUSH COUNTER) and 26 (COND POP TO UPPER COUNT. _ hand, cannot be disabled and does not cause saving of status ER/POP TO DISPLACEMENT WIDTH) are the counterparts on the internal stack. It is intended for handling abnormal and for operating on the upper counter. Note that in cascaded _itrecoverable situations like power failure or stack overtiow. systems, when the counter is pushed, regardless of whether When an unmaskable interrupt occurs, the sequencer branch- instruction 25 or instruction 10 is executed, the entire counter _@8 to the address of the unmaskable interrupt routine stored in is pushed to keep the stack balanced in the two Am29112s, the INTVECT register. This address is stored on chip at system initialize time using instruction 11 (COND RESET SP/ STACK AND REGISTER INSTRUCTIONS LOAD INTERRUPT REGISTER) with a condition of FAIL. if a In addition to all the instructions mentioned earlier that Maskable interrupt is being processed when the unmaskable explicitly or implicitly alter the stack, the Am29112 has some interrupt occurs, the unmaskable interrupt may be delayed at specialized instructions for stack manipulation. most one cycle to prevent contention on the Y bus. In any case, the unmaskable interrupt request should persist for at The stack on the Am29112 is 33 deep. Attempting to push east one clock edge. when the stack is full or to pop when the stack is empty causes the STACK ERROR signai out of the Am29112 to be The Am29112 contains an interrupt disable flip-flop on-chip. generated. The error is latched internally and persists untii_ The flip-flop is set by the DISABLE INTERRUPT instruction either the chip is reset or the stack is popped in case of (opcode 15 with forced FAIL) and reset by the ENABLE ‘overflow or pushed in case of underflow. When the stack INTERRUPT instruction (opcode 15 with forced PASS). The ‘overtiows, the stack pointer does not wrap around, and all __lip-flop output performs the same function as the interrupt subsequent pushes on the full stack write over the top-of- _disable pin. On reset, or on receiving an unmaskable interrupt, stack location. the flip-flop is set thereby disabling maskable interrupts. ‘The slack on the Am20112 can be loaded through the D port ‘Hence. al the endo! allalizalon. the ENAGLE INTERRUPT Using instucton 1 (COND PUSH D/LOAD COMMAND REG. etwveion wil have fo be executed 10 resot the fiplop and ISTER) with condition as forced PASS and unloaded out of the D port using instruction 2 (POP; COND STACKOUT TO D) with _In tho case of maskable interrupts, the interrupt return address a forced PASS condition. In the stackout instruction the D port _is saved on the stack automatically using the INTRTN register. becomes an output port. Care must be taken to avoid the INTRTN register is loaded with the CMUX output with ‘contention on the D bus when this instruction is executed. The _every clock. When an interrupt is acknowledged, the Am29112 D bus is output enabled while CP is low for this instruction. The output is turned off and the vector applied externally. Howev- | ability to load and unload the stack is useful for implementing er, the sequencer executes the instruction which is in the context switches. For fast unloading of the stack, a tight two- _ pipeline register in that cycle. The result of executing the instruction loop can be set up using instruction 12 (POP; _ interrupted instruction, namely the next address, does not

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The International Standard of Quality guarantees a 005% AQL on all electrical parameters, AC and DC, over the entire msee——

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