AM2909A

AM2911A AMD | Alldatasheet

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NOV 24 19g / Pa | Microprogram Sequencers DISTINCTIVE CHARACTERISTICS. 3 © 4-bit slice cascadable to form longer word width © Individual OR input for each bit for branching to higher 3S _— @ Branch input for N-way branches: microinstructions (Am2909A only) > © 4.x 4 file with stack pointer and push/pop control for © @ Am2909A in 28-pin package & Am2911A in 20-pin > nesting microsubroutines package 3 © Zero input for returning to the zero microcode word 8 MICROPROGRAM SEQUENCER BLOCK DIAGRAM > Trameioak ony] pur, FILE ENABLE an ¢1 > REGISTER: i tease” | me “DLoNe Mes eytey it owen | Qo | Dank ) Poneereo “W Satamdatia fa) | oncy ‘ axarne \\) _ ‘ omect | ° =. ‘0 x ucroprocnaM ; sure Terenas fo) TN ge TOR OY iw] f OR | a 8 I fon —T Ie x. | [oho = la) UUUY ‘ 9 a0 vy ¥ Y wn a 4 a a aol _ AA Yot vt vot ya) cy Coed Publication # Rev, Amendment 03578 Cc 10 . ! Issue Date: April 1989

The Am2909/ is a 4-bit wide sequencer intended for sequenc- includes certain control lines so that it can efficiently execute ing through a series of microinstructions contained in memory. nested subroutine linkages. Each of the four outputs can be Two Am2309As may be interconnected to generate an 8-bit OR’ed with an external input for conditional skip or branch address (256 words), and three may be used to generate a 12- instructions, and a separate line forces the outputs to all zeros; bit address (4K words). the outputs are three-state. The Am2909A can select an address from any of four sources: 1) a set of external direct inputs (D); 2) external data from the The Am2911A is an identical circuit to the AM2909A, except R inputs, stored in an internal register; 3) a 4-word deep push/ the four OR inputs and the R inputs are removed and the D pop stack; or 4) a program counter register (which usually inputs connect to the ADDRESS REG/HOLDING REG. The contains the last address plus one). The push/pop stack ‘Am2911A is in a 20-pin, 0.3" centers package. RELATED AMD PRODUCTS. eWay Branch Control Unit Newt Adress Canta [anastsies st Gouner For applications information, see Chapter 11 of Bit Slice Microprocessor Design, Mick & Brick, McGraw Hill Publications.

‘Am2909A DIPs Lec* co 217 ve ns Je ae 5 ° = ecer $528 C3 ap jee OOooeuano re, Che at) wigs) > 7) * ” Bae no Is 2417) Cora on Ds x [Xone ons C16 2 & oy)? of =i? auf yo om Ts alo om C48 aE) o )* oi Cis io om J 10 oft on, FJ 10 sy C [1 % On . 7 wo , 7 eee sw wow ty" wf vo AARAAAARA ‘ong [[] 12 wDs eeggere oe 6 Os ep004312 ono [J 1s[7] m6 0004333 *Am2909A is also available in a 28-Pin Ceramic Flatpack; _ pinout is identical to the LCC. Am2911A DIPs tec oe 20/7] eur we $6 3 e Vee (2 19["] Fe OoOodod _ ‘ 302 4 wD ae C]3 18] Snea ys 8 CL Cnea 4 170) So eU = me ys wo 2 (]s 16[ ] OF a 16 ({ Of C16 181] Ys % S] 7 ra menzy % (7 141] 2 Guo Djs uv eno [Je wp 1 2s on 2 8 ~ zero [9 121) Yo A_A_A_LA_LH Sp [10 ups: eg eS 6 SF coo04s22 cpo04s02 Note: Pin 1 is marked for orientation.

Hl RyRy | Dg SoS; nea ZERO 4 cP Yovs oe a PUP FE fe Vog = Power Supply BB = Grouns Lso0a110

Am2909A ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is | formed by a combination of: a. Device Number | b. Speed Option (it applicable) ©. Package Type 4. Temperature Range €. Optional Processing ~ AM29094 om & B L, OPTIONAL PROCESSING Blank = Standard processing B= Burnin d, TEMPERATURE RANGE C= Commercial (0 to +70°C) M=Military* (55 to + 125°C) ©. PACKAGE TYPE P = 28-Pin Plastic DIP (PD 028) 0 = 28-Pin Ceramic DIP (CD 028) X= Dice b. SPEED OPTION Not Appiicable a. DEVICE NUMBER/DESCRIPTION ‘Am29098 Microprogram Sequencer Valid Combinations - ‘AM2909A, PC, DC, DCB, Valid Combinations list configurations planned to be support XC._XM ed in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to *Military or Limited Military temperature range products are check on newly released combinations, and to obtain addi- “NPL (Non-Compliant Products List) or Non-MIL-STD-883C tional data on AMD's standard military grade products. Compliant products only.

Am2909A MILITARY ORDERING INFORMATION APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Device Class d. Package Type e. Lead Finish AM2909A. 3B x A —_ e. LEAD FINISH ‘A= Hot Solder Dip . PACKAGE TYPE X = 28-Pin Ceramic DIP (CD 028) Y = 28-Pin Ceramic Flatpack (CFM028) 3 = 28-Pin Ceramic Leadless Chip Carrier (CLT028) ©. DEVICE CLASS /B = Class 8 b. SPEED OPTION Not Applicable a. DEVICE NUMBER/DESCRIPTION ‘Am2909A Microprogram Sequencer Valid Combinations Valid Combinations /BXA, /BYA, (B3A Valid Combinations list configurations planned to be ‘supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups

Am2911A ORDERING INFORMATION Standard Products ‘AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Package Type 4. Temperature Range e. Optional Processing AM2911A, a £ B — OPTIONAL PROCESSING Blank = Standard processing B= Burn-in d. TEMPERATURE RANGE C= Commercial (0 to +70°C) M=Milltary* (-55 to + 125°C) ¢. PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) D=20-Pin Ceramic DIP (CD 020) X= Dice b. SPEED OPTION Not Applicable a. DEVICE NUMBER/DESCRIPTION Am2911A Microprogram Sequencer Valid Combinations Valid Combinations — AM2O11A PC, DC, DCB, Valid Combinations list configurations planned to be support: XC, XM ed in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to “Military or Limited Military temperature range products are check on newly released combinations, and to obtain addi- "NPL" (Non-Compliant Products List) or Non-MIL-STD-883C tional data on AMD's standard military grade products. Compliant products only.

Am2911A MILITARY ORDERING INFORMATION APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MiL-STD-883C requirements. The order number (Valid Combination) for APL Products is formed by a combination of: a. Device Number b. Speed Option (if applicable) ©. Device Class 4. Package Type e. Lead Finish AM2911A, B Rg 4 — LEAD FINISH A= Hot Solder Dip . PACKAGE TYPE R = 20-Pin Ceramic DIP (CD 020) 2= 20-Pin Ceramic Leadiess Chip Carrier (CLT020) ©. DEVICE CLASS 78 = Class B b. SPEED OPTION Not Applicable a. DEVICE NUMBER/DESCRIPTION Am2911A Microprogram Sequencer Valid Combinations Vatid Combinations M2911 7BRA, /B2A Valid Combinations list configurations planned to be ‘supported in volume for this device. Consult the local AMD. sales office to confirm availability of specific valid combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups

Am2909A/Am2911A RE Register Load Enable (Input; Active LOW) Cp Carry in (Input) Enable input for internal address register. Carry input to the incrementer. So, $1 Source (Input) litplexer that select the source of Cn Carry Out (Output) Control inputs to the mul ‘Carty out from the incrementer the next microinstruction address. CP Clock Pulse (Input) Yo-3 Address (Output; Three State) Clock input to the AR and PC register and push/pop stack. Address outputs. ~ Do-3 Direct Input (Input) ZERO Zero (Input; Active LOW) Direct input to the multiplexer. Forces the four Y outputs to binary zero (except when OE is ee HIGH). FE File Enable (Input; Active LOW) » Used along with PUP to control the push/pop stack. Am2909A Only OE Output Enable (Input; Three State, Active LOW) ORo-3 Logic OR (Input) Three-state control of Yj outputs. Logic-OR inputs on each address output line PUP Push/Pop (Input) Ro-3 Register Input (Input) Used along with FE to control the push/pop stack. Inputs to the internal address register. FUNCTIONAL DESCRIPTION The last source available at the multiplexer input is the 4x 4 file (stack). The file is used to provide return address linkage i when executing microsubroutines. The file contains a built-in Architecture of the Am2909A/Am2911A stack pointer (SP) which always points to the last file word ‘The Am2909A/Am2911A are bipolar microprogram sequenc- el ore waht sack roreronce operations (looping) to be ers intended for use in high-speed microprocessor applica. P™ @ push oF pop. tions. The device is a cascadable 4-bit slice such that two The stack pointer operates as an up/down counter with devices allow addressing of up to 256 words of microprogram separate push/pop and file enable inputs. When the file and three devices aliow addressing of up to 4K words of enable input is LOW and the push/pop input is HIGH, the push microprogram. A detailed logic diagram is shown in Figure 1. operation is enabled. This causes the stack pointer to incre- ment and the file to be written with the required return linkage ~ The device contains a 4-input multiplexer that is used to select. © — the next microinstruction address following the subroutine eithor the address register, direct inputs, microprogram count- jump which initiated the push, Fhie aetonee souros one Or the Sand St inate If the file enable input is LOW and the push/pop contro! is 1 7 LOW, a pop operation occurs. This implies the usage of the : return linkage during this cycle and thus a return from The address register consists of four D-type, edgetriggered ——. broutine. The next LOW-to-HIGH clock transition causes the flip-flops with a common clock enable. When the address tack pointer to decrement, If the fle enable ie HIGH, register enable is LOW, new data is entered into the ragister, Sua POINET ta Necromenl. He le a of any other ‘on the clock LOW-to-HIGH transition. The address register is a “a is taken by the stack pointer regardless of any other available at the multiplexer as a source for the next microin- "Pt struction address. The direct input is a 4-bit field of inputs to The stack pointer linkage is such that any combination of the multiplexer and can be selected as the next microinstruc- pushes, pops, or stack references can be achieved. One tion address. On the Am2911A, the direct inputs are also used microinstruction subroutines can be performed. Since the as inputs to the register. This allows an N-way branch where N-_stack is four words deep, up to four microsubroutines can be is any word in the microcode. nested, The Am2909A/Am2911A contains a microprogram counter Th® 2ERO eee ne oO ett youre (u°C) that is composed of a 4-bit incrementer followed bya Tow \\ocugese of et Mss oxen oe Sas 4-bit register. The incrementer has carry-in (Cp) and carry-out regardless of any other inputs except in the ‘Am2909A, each Y output bit also has a separate OR input (Cn + 4) such that cascading to larger word lengths is straight- A™eoue. Gach & Gull See each forward. The sPC can be veedin ether of woways, When tho Su=h tat @ conditional logic one can be forced at oa least significant carryin to the incrementer is HIGH, the OutD¥t. This allows, imping 10 different microinsiructions on microprogram register is loaded on the next clock cycle with Progr ons. the current Y output word, plus one (Y+1~yPC); thus The Am2909A/Am2911A feature three-state Y outputs. These - ‘soquential microinstructions can be executed. If this least _can be particularly useful in designs requiring external equip- significant Cr is LOW, the incrementer passes the Y output ment to provide automatic checkout of the microprocessor. word unmodified and the microprogram register is loaded with The internal control can be placed in the high-impedance the same Y word on the next clock cycle (YPC). Thus, the state, and preprogrammed sequences of microinstructions same microinstruction can be executed any number of times can be executed via external access to the control ROM/ by using the least significant C, as the control. PROM.

similar, buts fixed at 12 bits in length and has a fixed set of 16 “return-trom-subroutine”, etc. The bits representing this se. sequence control instructions. The Am2909A or Am2911A quence command are logically combined with bits represent. © Address longer than 12 bits ‘combinational. Figure 5. Recommended Computer Control Unit Architecture Using the Am2911A

place. The Am29811,, in addition to controlling the Am2911A, to "The Microprogramming Handbook".

8 NeXT ‘ADDRESS:

Figure 6. A Typical Computer Control Unit Using the Am2911A and Am29811A

Y result in @ branch to 1100, 1101, 1110, or 4111 Contents of PC placed on Y outputs; PC incremented. lines. Increment address and place in PC. vlulvly [w_] Subroutine address fed from D inputs to memory address.

7 Current PC is pushed onto stack, where it is saved for the

cycle. The stack is popped to remove the return address. Figure 10. Use of OR Inputs to [None [None [eee epee

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature hoeeeceeteeeseeeess 65 to + 150°C Commercial (C) Devices . Military (M) Devices: DC Voltage Applied to Outputs For Case Temperature (To) .vsssessssssssseess 55 tO +125°C High Output State... 0.5 V to +Veo max Supply Voltage Vas vi ¥S3V DC Input Voltage ees eeeeeeeee -0.5 V to +7.0V fees ~ “ Stresses above those listed under ABSOLUTE MAXIMUM Thermal Resistance (Typical) RATINGS may cause permanent device failure. Functionality Am2909A at or above these limits is not implied, Exposure to absolute mtn rong tor oon porate ney ate! covce [Sms | ms [Sea am ene reliably. | scrw | (isc [wa fs [7 fe row Am2911A [_Symbot | Pd 020 | co 020 | curozo | unit_| [aa_| 76 [7 [7 aa | scrw | ge oe 6 ew “Military product tested at To = + 25°C, + 125°C, and - 55°C. DC CHARACTERISTICS over operating range unless otherwise specified (for APL products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) Parameter Parameter "sea | ceca | Test Condon ot oot Vou | Output HIGH Voltage Voc = MIN, Me v [va [ovoniowvomm ——(Wermrarye facweme || oe | [vw [rownenion atmos arma Le | | [Tn ne wpe eg [eo] | a ee ee [eens | [at [a-owewe [| = | vee ame encore | | fore | = | Tey Samay ee Mare a an ced vie Opa ros pe

SWITCHING CHARACTERISTICS over B. Maximum Combinational Propagation Delays ‘operating ranges unless otherwise specified (for APL {all in ns, CL = 50 pF (except output disable tests)) Products, Group A, Subgroups 9, 10, 11 are tested | commercial | MILITARY unless otherwise noted) Tables A, B, and C below define the timing characteristics of the AmZ909A/AM291TA over the operating voltage and =| | t7”—| ae 20 | 28 temperature range. The tables are divided into three types of inputs to outputs, and setup and hold-ime requremerts. The | ORM” || 2a | a0 | 25 | latter table defines the time prior to the end of the cycle (i.e., to guarantoe that the correct data is written into one of the | ZERO | 2a | ga | a0 | 35 | Measurements are made at 1.5 V with Vj, = 0 V and Vi = 3.0 OE HIGH (disable)* | 2 | - | 2 | - | V. For three-state disable tests, C, = 5.0 pF and measurement is to 05 V change on output voliage level Alloutputs have | lock | SiSo=UH | 3a | 4a | 45 | 50 | maximum DC loading, Glock 1 SiSo=tt | 39 | 44 | 45 | 50 | A. Cycle Time and Clock Characteristics Glock + SiSo=He [44 | 49 [59 | 58 | *CL=5 pF [time [COMMERCIAL] MILITARY C. Minimum Setup and Hold Times (all in ns) (Note 1) COMMERCIAL MILITARY From Input Setup Time [Hold Time | Setup Time [| __Hold Time [Re es a (OG a < C a CO: OS ON a OS (SS [ome oo [Sosa i < Notes: 1 All tmes relatve to dock LOW-to HIGH transition 2. On amea11A. R, and 0, are internally connected together and labeled 0, Use Fi setup and hold times when D inputs are used to load rogsier. *+am290aA only

Key to Switching Waveforms Sac Seaby | Es a FHA ae {EF Evan | mem idk mu seae x y sors |_ BRIER BBS your OOO OY ome ROO os wrens - ane ov wrneains

c | | ; | ; f $3 Tc001150 YE001140 2av Roe 'oH 5.0-Vee-VoL 5.0-Vee-VoL Ryo Ry = VBE TOe tou + Vou/1k Tou + Vou/Re A. Three-State Outputs ‘8. Normal Outputs Notes: 1. C= 50 pF includes scope probe, wiring and stray capacitances without device in text fixture. 2. St, Sz, Sg are closed during function tests all and AC tests except output enable tests. 3. S; and 33 are closed while Sq is open for tpzH test. St and Sz are closed while Sg is open for tpz. test. 4. C= 50 pF for output disable tests TEST OUTPUT LOADS Am2909A | _ 18-21 AmasiiA| 12-15 Yos 220 1k am2otta| 18 | Cn+4 2.4K

TEST PHILOSOPHY AND METHODS capacitances. The result at the other capacitance is predicted from engineering correlations based on data The following nine points describe AMD's philosophy for high taken with a bench setup and the knowledge that certain volume, high speed automatic testing, DC measurements (ion. lo. for example) have already been taken and are within spec. In some cases, special DC 1. Ensure that the part is adequately decoupled at the test head. Large changes in Voc current as the device switches tests are performed in order to facilitate this correlation. may cause erroneous function failures due to Vcc changes. 7. Threshold Testing 2. Do not leave inputs floating during any tests, as they may ‘The noise associated with automatic testing (due to the start to oscillate at high frequency. Jong, inductive cables) and the high gain of the tested 3. Do not attempt to perform threshold tests at high speed. device when in the vicinity of the actual device threshold, ~ Following an output transition, ground current may change frequently give rise to oscillations when testing high speed by as much as 400 mA in 5-8 ns. Inductance in the ground circuits. These oscillations are not indicative of a reject cable may allow the ground pin at the device to rise by device, but instead of an overtaxed test system. To hundreds of millivolts momentarily minimize this problem, thresholds are tested at least once for each input pin. Thereafter, “hard” high and low levels 4. Use extreme care in defining point input levels for AC tests. are used for other tests. Generally this means that function Many inputs may be changed at once, so there will be and AC testing are performed at “hard” input levels rather significant noise at the device pins and they may not than at Vi. Max. and Viy Min. actually reach Vi or Vit until the noise has settled. AMD recommends using Vi_ <0 V and Vij > 3.0 V for AC tests. 8. AC Testing 5. To simplify failure analysis, programs should be designed to Occasionally, parameters are specified that cannot be perform OC, Function, and AC tests as three distinct groups measured directly on automatic testers because of tester of tests. limitations. Data input hold times often fall into this catego- ty. In these cases, the parameter in question is guaranteed 6. Capacitive Loading for AC Testing by correlating these tests with other AC tests that have ‘Automatic testers and their associated hardware have stray been performed. These correlations are arrived at by the capacitance that varies from one type of tester to another, cognizant engineer by using precise bench measurements but is generally around 50 pF. This, of course, makes it in Conjunction with the knowledge that certain DC parame- impossible to make direct measurements of parameters ters have already been measured and are within spec. el Samatttance: Typed srarnplog ‘han the associated In some cases, certain AC tests are redundant, since they Called "float delays.” which measure the propagation can be shown to be predicted by some other tests which delays into the high-impedance state and are usually have already been performed. In these cases, the redun- specified at a load capacitance of 5.0 pF. In these cases, dant tests are not performed. the test is performed at the higher load capacitance 9, Output Short-Circuit Current Testing = (typically 50 pF), and engineering correlations based on data taken with a bench setup are used to predict the result When performing log tests on devices containing RAM or at the lower capacitance. registers, great care must be taken that undershoot caused by grounding the high-state output does not trigger parasit- Similarly, a product may be specified at more than one ic elements which in turn cause the device to change state. capacitive load. Since the typical automatic tester is not in order to avoid this effect, it is common to make the capable of switching loads in mid-test, it is impossible to measurement at a voltage (VouTPUT) that is slightly above make measurements at both capacitances even though ground. The Voc is raised by the same amount so that the they may both be greater than the stray capacitance. In result (as confirmed by Ohm's iaw and precise bench these cases, a measurement is made at one of the two testing) is identical to the Vout = 0. Voc = Max. case. a

F ate --ll = oa i 3— » = — a at — EA ae % *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering.

PHYSICAL DIMENSIONS (Cont'd.) cD 028 ~ — \\ ed Lge F a es x au ="| 8 tog " et —- . an ois it *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering.

PHYSICAL DIMENSIONS (Cont'd.) CFM028 « “ Ba», i beaal SS Ee. — E—=_— ——| = = —F — 7” == _ ais | s _—— 22 we 2 z = z Bee “For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic ‘Space Centering. a

PHYSICAL DIMENSIONS (Cont'd.) CLTO28 a em ee a ott i A fee aio fet # To hota a ee OB wwoex connen, wx: reF. 0%) aioe 7 au OQ ||# 4 | L | = i —2=——_ se veEW 2— ~ voswew *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering.

PHYSICAL DIMENSIONS (Cont'd.) PD 020 P| i {PF iL ee ze 2 ome *For reference only. All dimensions are measured in inches. BSC is an ANS! standard for Basic Space Centering.

PHYSICAL DIMENSIONS (Cont'd.) cD 020 Lo ait ) FA afb A = Bsc vd oso ; @ — oe

2 Fr fs

*For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering.

PHYSICAL DIMENSIONS (Cont'd.) CLTO20 _ 0 ee LSM “to '@ 8B oe FP] ' Fe [se LI nw Fs a + mi ' a Ct — 7. Ie — Pr ca | we a oe sorrouwew oe ss Sonne 7 Semon) —2— soevew oe von toe vew anes *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering. [Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics. The performance ‘SNeracorateslsiodinhs document ars gua‘arted by sec ets, quad banding, design andotherpractoas common fo he industry. For speci esbng dete, ontact your eal AMO sales tproventawe. The combary assumos fo responsi) for he use of any crc Getribed herein, “Advanced Micro Devices, Ine 20% Thompson Mace, P.O. Box 2453, Sunnyale, CA 94068, USA [sencaname madi ‘Tet: (408) 732-2400 = TWX: 910-339-9280 + EX: 34-6306 + TOLL FREE: (800) 538-8450 APPLICATIONS HOTLINE TOLL FREE: (800) 222-9323 + (408) 749-5703. AIS-WCP-2.5N-4/89-0 Printed in USA OFE70E v -- ae