AM2901BXM

AM2901B AMD | Alldatasheet

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Technical content

Four-Bit Bipolar Microprocessor Slice o DISTINCTIVE CHARACTERISTICS ry © Two-address architecture ~ © Left/right shift independent of ALU ~ Independent simultaneous access to two working regis- ‘Add and shift operations take only one cycle, ‘ ters saves machine cycles. © Four status flags - © Elght-function ALU - Carry, overflow, zero, and negative. Performs addition, two subtraction operations, and five © Flexible data source selection - logic functions on two source operands. ALU data is selected from five source ports for a total of © Expandable - 203 source operand pairs for every ALU function. Connect any number of Am2901s together for longer word lengths. GENERAL DESCRIPTION The Am2901 industry standard four-bit microprocessor groups of three bits each and selects the ALU source slice is @ high-speed cascadable ALU intended for use in operands, the ALU function, and the ALU destination 5 CPUs, peripheral controllers, and programmable micropro- _register. The microprocessor is cascadable with full look cessors. The microinstruction flexibility of the Am2901 ahead or with ripple cary, has three-state outputs, and permits efficient emulation of almost any digital computing _provides various status flag outputs from the ALU. AMD's machine. ion-implanted micro-oxide (IMOX) processing is used to fabricate the 40-lead LSI chip. The device, as shown in the block diagram below, consists, of a 16-word by 4-bit two-port RAM, a high-speed ALU, and te the associated shifting, decoding and mutiplexing circuity. fn "3ae0 taetor tray tne, Manson ne Ame08: ‘The nine-bit microinstruction word is organized into three MICROPROCESSOR SLICE BLOCK DIAGRAM sa. lpunooesaE) —— | U —=— | =ieT | fe Waiver ‘80002120 MOK i « Fadomert of Advanced Mo Docs 016568 54 eter to Page 12:1 for Essential Infomation on Mikary Devens

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3 RELATED PRODUCTS

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ORDERING INFORMATION

‘AMD products are available in several packages and operating ranges. The order number is formed by a combination of the following: Device number, speed option (if applicable), package type, operating range and screening option (if desired). ‘Am2901B Valid Combinations “Am2901C . c L PC Screening Option Blank - Standard processing ‘Am2901B pg, bce, OMB 8 - Burn-in XC, XM ESommesa (ew NIFC) 5G “Commercial (0°C 10 + M - Military (-55°C to + 125°C) DC, DCB, DMB Am2901C FMB Hae CERDIP LC, LMB F - 42-pin flatpak XC, XM L_44-pin leatless chip carrier P- 40-pin plastic DIP X= Dice Valid Combinations Device type Consult the AMD sales office in your area to Four-Bit Microprocessor Slice determine if a device is currently available in the combination you wish. 016568

53 Foe 10 Pape 191 fr Eseries Mita Deven

8 PIN DESCRIPTION

E[Pinno [weme [vO [Desenpton Py pase? feo ft | “The four address inputs to the register stack used to select one register whose contents are displayed through the A- = port. Sl 17,18 80-3 "The four address inputs 1o the register stack used to select one register whose contents are displayed through the B- Bl is ea ee Ua Sanbe aan when te. och foes LOW. & “The rine instruction control lines, Used to determine what data sources will be applied to the ALU (Ip12), what function Te ie eho onal ras, ea Se Seascale Grebo’ he rogue bach a ra RSS Po Gru (Os) ad he opto rack GUNG). Eoctay These es ae tee sla ‘outputs connected to TTL inputs internal to the device. When the destination code on ig7g indicates an up shift (octal Sa a er re ae cao rine Sp pvana Ronse a the ALU output is available on the AMG pin. Otherwise, the three-state outputs are electrically OFF (high-impedance) te ALU aap eat on A pa he peo oad oe data inputs to the MSB of the Q register (octal 4) and RAM (octal 4 or 5). Se} oS ess Ona ttt et SS of ro Gogo ard RAM Tse pao Udo Op anda pa Bie Sion a Onan RAM, a nS oe ea 0 a sna oon and a Sa oe So re sans fad wich tay be sbed a oreo he AL da soucos to veg dla 0 ze waa es Oras va Fe aT aa FS0wae GAT an When sabi ey Silay ar ht Os oF Tor See eee ee See ana aa ta Saati hy 6 aneeaton Cees {ao ]5E 11 oat nate, Whon OF HIGH, the ¥ outputs aro OFF: when OF le LOW, the ¥ Ovput are activo HIGH oF LOW Se eS eat baa a be rival Ni. Thos aga we ed wih AAO? fr con lookahead. Sa Wgiay be DESO he Gay Wa Gera oo WSB ato ALU. te Rw nr, Tis Be gS > Se aioe or as mamoks me's comport operon ht, a ee Se a wih por HGH GFA) Os ts Tow A ous Fa we aT TOW positive logic, it indicates the result of an ALU operation is zero. a a a [Tee Pe eat ot ita A The clock input. The © register and register stack outputs change on the clock LOW-lo-HIGH transition. The clock The oc ek, Te Ore nd oa a Ot cash ecynces ae ln le ope ‘stack. While the clock is LOW, the "slave" latches on the RAM outputs are closed, storing the data previously on the RAM outputs. This allows synchronous master-slave operation of the register stack. DETAILED Am2901C MICROPROCESSOR BLOCK DIAGRAM ~4 — rit Fl fH=H=H=l nn ere ape ae salle =f: Cif=H=H=H=k i 2 al NESS a(i ae i — miner GH. (EHEH=H= hy (=) oa =A re [eHeHsH=) 2 ee 5 yy ‘Note: SB is numbered "0"; MSB is numbered “3°. mp ry r¥ ry Las 8 n . onto Figure 2. 016568 oo sa Fg (3 ts sl wien ay Don

ARCHITECTURE Shown in Figure 4. Tho octal code is also shown for reference. H normal technique for cascading the ALU of several A dotailod block diagram ofthe bipolar micropogrammable —Govicgs win a look-ahead carry move, Cary gonerae,&. and 3 microprocessor structure is shown in Figure 1. The circuit is Cany propagate, P, are outputs of the device for use with a | S four-it slice cascadable to any number of bits. Therefore, all Carrylook-ahead-generator such as the Am2902. A-carry-out, | & data paths within tho circuit are four bits wide. The two Key «4, i also generated and is avaiable as an output for use| elements in the Figure 1 block diagram are the 16-word by 4 as the carry lag in a status register. Both carryin (Gq) and z bit 2-port RAM and the high-speed ALU. carryout (Cn +.) are active HIGH. 8 Data in any of the 16 words of the Random Access Memory g (RAM) can be read from the A-port of the RAM as controlled re Anas eee fone (OVN) he ted ese most Gy) by the 4-bit A address field input. Likewise, data in any of the Co icant (eign bit ofthe ALU and can bo used to determine "| 18 words of the RAM as defined by the B address field input Gositve or negative results without enabling the three-state can be simultaneously read from the B-port of the RAM. The av bi noguitte Tan Bete Me hee same code can be applied to the A select field and B select puts. Fg werted with respect to the sige ‘ ‘output Y9. The F =0 output is used for zero detect. It is an eld in which case the identical file data will appear at both the eae a re OR ed between micro. RAM A-port and B-port outputs simultaneously. processor slices. F = 0 is HIGH when all F outputs are LOW. When enabled by the RAM write enable (RAM EN), new data The overflow output (OVA) is used to flag arithmetic opera- is always written into the file (word) defined by the B address tions that exceed the available two's complement number field of the RAM. The RAM data input field is driven by a 3- range. The overflow output (OVA) is HIGH when overflow input multiplexer. This configuration is used to shift the ALU _oxists. That is, when Cn +3 and Cn + 4 are not the same polarity. if |, This three-input multiplexer scheme Shows he seta tobe ated ‘one bit postion sifted Gown _The ALU data output is routed to several destinations. It can tne bit position, or not shifted in either direction be a data output of the device and it can also be stored in the * RAM or the Q register. Eight possible combinations of ALU The RAM A-port data outputs and RAM B-port data outputs destination functions are available as defined by the Ig, I7, and 5 drive separate 4-bit latches. These latches hold the RAM data Ig microinstruction inputs. These combinations are shown in while the clock input is LOW. This eliminates any possibierace Figure 5. conditions that could occur while new data is being written into the RAM. The four data ouput fd () features troesato outputs and can be directly bus organized. An output control (OE) is Tran eteeete ana ive eas Unit au) can rollers used to enable the three-state outputs. When OE is HIGH, the met e logic operations on y " ia input words Rand S. The R input field is driven from a 2-input Outputs are in the high-impedance state multiplexer, while the S input field is driven from a input A two-input multiplexer is also used at the data output such muttiplexer. Both multiplexers also have an inhibit capability, _that either the A-port of the RAM or the ALU outputs (F) are that is, no data is passed. This is equivalent to a "zero" —_selected at the device Y outputs. This selection is controlled ‘source operand. by the Ig, I7, and Ig microinstruction inputs. Refer to Figure 12 Referring to Figure 2, the ALU Reinput multiplexer has the ©" the selected output for each microinstruction code combination RAM A-port and the direct data inputs (D) connected as ‘As was discussed previously, the RAM inputs are driven from inputs. Likewise, the ALU S-input multiplexer has the RAM A- a three-input multiplexer. This allows the ALU outputs to be port, the RAM B-port and the Q register connected as inputs. entered non-shifted, shifted up one position (x2) or shifted This mutpener scheme gives, the capanity of selecting down one. position (2), ‘herve bbolod HAMS fone ores operands hth A 80. wee irae itten to ata, ports consist of a butter-driver with a three-state output and an time, result in ten possible combinations of source operand input to the multiplexer. Thus, in the shift up mode, the RAMa pairs. These combinations include AB, AD, AQ, AQ, BD, BQ, _Duffer is enabled and the RAM multiplexer input is enabled. 0, DQ, DO and QO. It is apparent that AD, AQ and ‘AO are Likewise, in the shift down mode, the RAMo buffer and RAM3 somewhat redundant with BD, 6Q and BO in that if the A heats orate nero made, both buffers aren the address and B address are the same, the identical function npedance tiploxer input results. Thus, there are only seven completely non-redundant selected ‘This shifter is controlled ‘om me 'e, '7 and |g source operand pairs for the ALU. The Am2901 microproces- "™ tuction inputs as defined in Figure 5. ‘sor implements eight of these pairs. The microinstruction —_—_ Similarly, the Q register is driven from a 3-input multiplexer. in inputs used to select the ALU source operands are the Io. 11, the no-shift mode, the multiplexer enters the ALU data into the and Iz inputs. The definition of lg 1, and lz for the eight source register. In elthor the shift-up or shift<down mode, the operand combinations are as shown in Figure 3. Also shown is multiplexer selects the Q register data appropriatoly shifted up the octal code for each selection. ‘or down. The Q shifter also has two ports; one is labeled Qo The two source operands not fully described as yet are the D and the other is Q3. The operation of these two ports is similar input and Q input, The D input is the four-bit wide direct data 0 the RAM shifter and is also controlled from Ig, 17, and le as. field input. This port is used to insert all data into the working ‘shown in Figure 5. registers inside the device. Likewise, this input can be used in Tg Giock input to the Am2901 controls the RAM, the Q the ALU to modity any ofthe internal data tes. The © register register, and the A and B data latches. When enabled, data is is a separate 4-bit fle intended primarily for mutipicaton a ‘clocked into the Q register on the LOW-o-HIGH transition of division routines but it can also be used as an accumulator or the clock. When the clock input is HIGH, the A and B latches holding register for some applications. are open and will pass whatever data is present at the RAM The ALU itself is a high-speed arithmetic/logic operator _ outputs. When the clock input is LOW, the latchos are closed capable of performing three binary arithmetic and five logic and willretain the last data entered. If the RAM-EN is enabled, functions. The Ig, , and Is microinstruction inputs are used to _—_new data will be written into the RAM file (word) defined by the select the ALU function The definition of these inputs is 8 address field when the clock input is LOW. 016568

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3 FUNCTIONAL TABLES

zw JHlujye ° A notas |H|L|H| 5 |RANDS | Fas. Figure 3. ALU Source Operand Control. Figure 4. ALU Function Control. 8 = Register Addressed by & inputs. UP is toward MSB, DOWN is toward LSB. Figure 5. ALU Destination Control. Figure 6. Source Operand and ALU Function Matrix.

56 Faler to Page 19: tr EssartalIommason on Mitary Doves

When Io through Is and Cy, are viewed together, the matrix of are defined in these operations.

41 AaB 00 A+ A+Q+1

45 DAA 01 A+B | ADD pus | A+B+1

46 DaQ o5 D+A ‘one D+Ati

61 AvB 12 Q-1 Q

65 OVA 13 B-t 8

70 WG a7 o-1 D

71 AVE 22 -0-1 =O

76 DvG 24 wA-1 | (Nogate) | -A

62 Q 16 Q-D-1 Q-0

63 B 20 A-Q-1 A-Q

64 A a4 A-B-1 A-B

67 E) 25 D-A-1 D-A

51 AaB

55 Boa

56 Baa

Figure 7. ALU Logic Mode Functions. Figure 8, ALU Arithmetic Mode Functions.

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2 LOGIC FUNCTIONS FOR G, P, Definitions (+ = OR)

» AND OVR g C+ Po= Ro So Go = RoSo | The four signals G. P, Cn+4, and OVR are designed to Prats. eens! 5 | incicate cary and overtiow coneitions when the Am2901 i in inte Sine © | the add or subtract mode. The table below indicates the logic ‘3 Ro So Fa ‘equations for these four signals for each of the eight ALU C4 = Gg + PgGe + PaP2G1 functions. The R and S inputs are the two inputs selected + PgP2P4Go + PaP2P1PoCn & | according to Figure 3. a= Gp + PoG1 + PaP1Go_+PaP1PoCn [teas [rumour] FT Tee | OR [o | rvs | Pari | GasPaGaePypmn rari | | ate [+ | s-n_| +———————Same as f+ S equations, but substitute Fi for Rin detinitons + | [a fas | tow aPaeiro | PaPaPPO Gn | PPDPIPD + Cn [« [ms | tow «| GarGgetrr Ge | Gat Ger Git Goren | Ga Gar Gi Gorn] [s | Fas | __tow | Samo as Ans equations, bu sete Fi for in defitone———+ | GrPaGa + PPT Note: [P2+ GaP; + GeSiPo + G25 1GoCa] +=OR (Pa + GoP2+ GoGePr + GsG2GiPo + GaG2G Gorn Figure 9. MINIMUM CYCLE TIME CALCULATIONS FOR 16-BIT SYSTEMS ‘Speeds used in calculations for parts other than Am2901C are representative for available MSI! parts. AFOO1621 Pipelined System. Add without Simultaneous Shift. DATA LOOP ‘CONTROL LOOP @hogsor ‘Glock to Oust SC +See” Fas ee + Que” Soect'o Cup 18 +@2002A Go, Po to Crs z 7 +@2010A CC to Oulput 30 +@2001C Crt Crag OVR, 25 +@PROM Access Time 40 +@Register Setup Time 2 + QRegister Sotup Time 2 a pane Minimum clock pariod = 94ns 016568

58 Retr to Page 1:1 for Essent formation on Métny Devices

=] 3 a = 3 +] 5 fe 8 ttt os] | a 3 =i] aman . 2 alia Pipelined System. Simultaneous Add and Shift Down. DATA LOOP ‘CONTROL LOOP 5 legister Clock to Output 9 register Clock to Output 9 + Go. Po to Cn+z 7 + 104, CC to Output 30 TORR end MUX Fy 1 QRopeter Setup Time A i a a Figure 10. 016568 vs cone one

3 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES

3 (C Voltage Applied to Outputs For Maiany (M) Devices 7 PPOBHUE ee seeeeeeereseeeesesssees 55°C tO + 125°C | High Output State... seen O.5V to +Vog max ee eR 0 4 8V | dc Output Current, Into Outputs .... cesrseesese SOMA tty of he Olea w cumanteed ction Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied, Exposure to absolute maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating range unless otherwise specified [Parameters | Deserption [Test Gonaitone wow) in| max | unite Tons -16ma Yovs. Yo. Ya [lon==1.0mA, Cova | aa [lon==e00w Ove, BT aa [| Voc = MIN You Ouput HIGH Votage | Vil Vn oF Vi [lon==600uA Fo | ea NOS feces Te P| FAM, 9, Qo Tow=-16ma, GT ee TT = Se lee ee For F = 0 Output Vin= Vira oF Vit. [lou=20mA (COM) (Note a) Tos | Yo Wt ¥2 ¥8 [og = 16mA (MIL) Note 4) jos | Voo=Min, [SB F=0 [i= tema os | Vou Output LOW Voltage Viv=Viq [Grea [tu= tomas | ova POV [ig soma os | Fo, RAM, - gree forcom Te | “Guaranteed input logical HIGH ec ‘Guaranteed input logical LOW [x __[rontowinw [aerate | oe oe [wr __| teput Clamp Votiage | Voc= MIN, w=—t8mA 48 Vos | Cock, OE [| 036 | Ao. At, Az. Aa a Ts ee LI [BoD Dabs | 072 | me Inpa LOW Curent Woo = MAX. Vin = 0.54 cs a a co [tet TY =072 | [RAMo, 3, Qo Nowe 9) | -08 | [oq 8 a [Ao Ar An Ag Tao a | TN "npat HIGH Curent Woo= MAX: Vin 2:70 A “* A rr [RAMo. 3. Qos (Note 9) | 00 [oT 200 016568

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[Parameters | Description | Test Conditions (Note 1) [wa Tmax] unis] 5 = 3 lozn ‘Off State. (High impedance) 2 = bay $ iat | Stan ways [een || we | mB Qo, 3 Vo = 0.5V (Note 3) [ove 8 | oo ee 3 [Gree oa] ipa son cr comet | voc =max rosy, vonosy [vm F | =a0 [ae] ma a ee rove iy caret | vor eye HORS ——_[Tazsvoe te wit Gry [To=-s6r0wrvesc | too) __[io=svaste 2 ‘Note: vc condions enown an MN or MAX, reff ho mit (10%) or commorsl (+53) Voc tts 2. Not more than one output should be stored at a time. Duration of the short circuit test should not exceed one second. Nt more than cow" ovput shou bere a ne, at ehrecates we enor wah yn sa Sh that He oie} 4, "MIL" = Am2901CXM, DM, FM, LM, "COM'L" = Am2901CXC, PC, OC, LC. See errs Iota created operating rane. 5 & Wort cae ics manne ai owe ee ra aay emanate noe reo enviroment, fot unctonaly West 016568 sn te Fag 1 nl ra on yD

2 [1. Am2901B Guaranteed Commercial A. Cycle Time and Clock Characteristics. Range Performance Fa ngs Read-Modify-Write Cycle (from selection of A, co E | The tables below specity the guaranteed performance of the |B teaisters to end of cycle.) oO Am2901B over the commercial operating range of 0°C to Maximum Clock Frequency to shift Q (50% | 70°C, with Voc trom 4:75V to 5.25V. All data are in ns. with | duty cycle. |= 432 or 632) tronte made tv. al ouputs have maximum OC foaa | Minimum Clock LOW Time | Fe ments made at 1.5V. All outputs have maximum DC load. Minimum Clock LOW Time | sons _| : [ Minnsn- Gack HGH Tine nn Tce totam 4ng90;8%¢ [ima Gosk Peed te | 1BDC Minimum Clock Period 69ns 8. Combinational Propagation Delays. (Note 1) CL = 50pF [ramon |v | ro | cove | ar | eno | om | Rams | 8 | [ABAdiress [oo fo [se To fT mo Te fat - [oo oe eo eT of fT foe me a a as ee os oT [we ae Ps | ‘A Bypass ALU (= 20) [cock Fe fe | Ta se ts |e C. Set-up and Hold Times Relative to Clock (CP) input. (Note 1) cp: Set-up Time Set-up Time Hold Time Before H ~L Before L -H After =H [Re Sacention |_| one | onowo | 0 B Destination a GO [ere i a ange oe) RAMO, 3, 00, 3 CO D. Output Enable/Disable Times. Output disable tests performed with C. = 5pF and measured to 0.5V change of output voltage level. Does Ts NOTES: 1. A dash indicates a propagation delay path or set-up time constraint dows not exist. 2 Certain signals must be stable during the entice clock LOW ‘ime to avoid erroneous operation. This is indicated by the phrase "do not change" 3. Soufce addresses must be siable prior to the clock HL transition to alow tne to access the source data before the latches close. The A address may then be changed. The B address could be changed if it is not 2 dostnaton Le, i data % not being writen back ito the RAM. Normally Aand 8 ere not changed during the ‘lock LOW «4. Tho sotup me prior to the clock LH ranstion is 10 allow time for deta to be sccessed, passed through the ALU, and returned 10 the AM, I indicates all the time from stable A and 6 addresses to tho clock LH transition, regardless of when the clock HL wansition occurs. 016568

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Il, Am2901B Guaranteed Military Range A. Cycle Time and Clock Characteristics. 3 Performance Read-Modify-Write Cycle (trom selection of A, | sane | 3 ‘The tables below specify the guaranteed performance of the B registers to ond of cycle.) a ‘Am2901B over the military operating range of -55°C to | Maximum Clock Frequency to shift 0 (50% | ean | | > + 125°C, with Voc from 4.5V to 5.SV. All data are inns, with | duty oyole. | = 432 or 632) ous |B inputs Swichng Bee On are De eas, | Minimum Giock LOW Time | ments made at 1.5V. All outputs have maximum DC load. Minimum Clock LOW Time | sons _| 3 [wre cost HGH Tie | oom || 2 Tecan apni sowrgparnminn anzer80M nnn est Pet | or | puberty Minimum Clock Period 88ns B. Combinational Propagation Delays. (Note 1) ‘Cy = 50pF Pr eee losis | me ws Te [oC me me fe [we Cis we ee Pw se [ee Cs eT |! | Ud] de | : ‘A Bypass ALU (= 200 C. Set-up and Hold Times Relative to Clock (CP) Input. (Note 1) cP: Input — — Set-up Time Hold Time ‘Set-up Time Hold Time Before H -L Atter HL. Before L -H After L_-H ree aes tot [ete B Destination ee ee ee AY | [rama sons | - dP D. Output Enable/Disable Times. Output disable tests performed with C, = 5pF and measured to 0.5V change of output voltage level. Com [| vy [ # [| NOTES: 1, A dash indicates @ propagation delay path or setup tme constraint does not exist 3, A, dash indies dal be Sable during tne entre clock LOW limo to avod erroneous operation. Ths is incicated by tho plwase "'do not change” oats oot cat Ie stable prior to the clock HL transition to alow time to access the source data before Soe ee The A address may then be changed. The 8 address could be changed fit is not a destine- Ie atc a's not beng wrifton Back inlo the RAM. Normally A and & are not changed during the clock LOW t 4m. setup tie prior to the clock L~H transition is to alow time for data 10 be accessed, passed trough the Ire ety cnn to the AMT includos all the time from stable A and 8 addresses to ihe clock L-H Cansiton, regardless of when the clock HL transition occurs 016568

5.13 Rotor to Page 1:1 for Essent lotomaton on satay Dowcos

Q | i. Am2901C Guaranteed Commercial A. Cycle Time and Clock Characteristics. Range Performance g va Read-Modify-Write Cycle (from selection of A, & The tables below specify the guaranteed performance of the B registers to end of cycle.) ‘Am2901C over the commercial operating range of °C to 7 | +70°C, with Voc from 4.75V to 5.25V. All data are in ns, with iin aptinated wo shit Q (50% ES © | inputs switching between OV and 3V at 1V/ns and measure- cyte, Po Amaovicle Minimum Clock Period | sins_| B. Combinational Propagation Delays. (Note 1) Cy = 50pF Qo cn+4 as ee ce es CS ‘A Bypass ALU (= 2xx) [cock Fs as fas ass sas 28 C. Set-up and Hold Times Relative to Clock (CP) input. (Note 1) 30, 15+ Tpwe Some [| tome | ee [| B Destination Rae mew | | [on a a TY A OE SS D. Output Enable/Disable Times. Output disable tests performed with C, = 5pF and measured to 0.5V change of output voltage level. a | NOTES: 1. A dash indicates a propagation delay path or set-up time constraint does not exist 2 Certain signals must be stable during the entire clock LOW time 10 avoid erroneous operation. Thie is indicated by the phrase "do not change” 3, Source addresses must be stable prior to the clock H~L transition to allow time to access the source data before the latches close. The A address may then be changed. The 8 addiess could be changed if It is not a destina- tion; i.e. data is not being written back into the RAM. Normally A and B are not changed during the clock 4. The 01 te prior to the lock LH tanaion isto alow tine fr data {0 be accessed, passed tough the ‘ALU, and returned to the RAM. It inckides all the time from stable A and addresses to ihe clock L—H. ‘transition, regardless of when the clock HL transition occurs 016568

514 Peter to Page 12-1 for Essent information on Matar Devices

IV. Am2901C Guaranteed Military Range A. Cycle Time and Clock Characteristics. 2 Performance Read-Modify.Write Cycle (from selection of A, The tables below specify the guaranteed performance of the |B ragisters to end of cycle.) 2 ‘Am2901C over the military operating range of -55°C to CJ 27125". with Voo from 4.5V to SV. Alldata aroin ns, with | Maximum Clock Frequency to shift 2 (602% > inputs switching between OV and 3V at 1V/ns and measure- uty cycle, or 632) A ens Nase St i cui have rsum De eas | Minna Geck LOW Tine |e || ‘Am2901CLM B. Combinational Propagation Delays. (Note 1) C_ = 50pF eX ‘a0 From Input cn+4 Q3 fo i fe me we eT [oid Ts eT ef es fe 5 ree SO | dT TR A Bypass ALU (l= 2Xx) ©. Set-up and Hold Times Relative to Clock (CP) Input. (Note 1) cP: Set-up Time Hold Time Set-up Time Before H -L After Ho ~L Before LH 30, 15 + Tow. a B Destination bere 0 0 args sie [rawaos | - i. ye D. Output Enable/Disable Times. Output disable tests performed with C= SpF and measured to 0.5V change of output voltage level. Cio | vy [ss [ss] NOTES: 1. A dash indicates a propagation delay path or set-up time constraint does not exist. 2 Cottam signals must be stable during the entre clock LOW time to avoid erroneous operation. This is indicated by the plvase "do not change" a aaa Sarceses must be stable prior 10 the clock HL transition to alow time to access the source data before Te cnes clove, The A address may then be changed. The B address could be changed i it is not a desting. fy iar sata rt ang ween bao io th FAM: Rermaty A and ar not canaRs rings cose Low 4 ‘The setup time prior to the clock LH transition is to allow time for dats to be accessed, passed through the wreaks atumned to the RAM. I includes. al the ime trom stable A and 8 addrossos 10 the clock LH Transition, regardiess of when the clock H™L transition occurs. 016568 5415 eter to Page 19 fr Exsenial formation on Mitary Ooicos

3 SWITCHING TEST CIRCUIT

E Ss es Fa A. THREE-STATE OUTPUTS 8, NORMAL OUTPUTS C. OPEN-COLLECTOR E OUTPUTS i o w Pa Sy ™ 3 m s, i Yon 00% Your oo Your 000 a I Ry | ey | cs c recooe0 res010%0 10001100 Ton 5.0- Vee - VoL 5.0-Vpe - VoL 5.0-Vor Ry Ry =-—— R= Tou + VoL/1K lo. + VoL/Ra Tou Notes: 1. CL = 50pF includes scope probe, wiring and stray capacitances without device in test fixture, 2. S1, Sz, S3 are closed during function tests and all AC tests except output enable tests. 3. Sq and Sg are closed while Sz is open for tpzH test. $1 and Sp are closed while Sg is open for tpz, test. 4. CL=5.0pF for output disable tests. TEST OUTPUT LOADS FOR Am2901C (DIP) [Chee | Pin tater [Test Grom [ mr | me _ a je [Ramo | seo Lo feed ed ed ED Re Poa fT co [owe fe otk cee a [seco [vos Teo Tk 016568 516 elec o Page 13: for Essent nematen on Mitary Devices

TTL INPUT/OUTPUT CURRENT INTERFACES A a wer SCHOTTKY PNP 7 tec ORIEN WUT OnVEN meUT DRIVEN PUT 3 Sf Jaweh SF ° bas7 o ci en » une om b 1 Ci =5.0pF, all inputs > THREE-STATE OPEN COLLECTOR: ” —" | [ [ r r =] = a Co =5.0pF, all outputs Figure 11. 016568

cs) 3 LIFE TEST AND BURN-IN CIRCUIT FOR MILITARY CLASS B PARTS. 2 a ec s ” fT tots Te Te |e fe ane 3 ae So & nee a xox e . Qo oy Op Oy o rr a ‘6 hy feof Awa =p [se | aah , toa ee _ Yee ey fay! Gn % 9) Op 3 16 Voc GND Ay Ag Ay Ay Yo Yy Ya Yo vec PPPPPrerer re PF aaa = a + Le am Veo = 50V ec ey Ta 128°C This circuit conforms to MIL-STO-883, method 1015, condition D. Nec: reamoro (Contact Factory for Commercial Burn-in Conditions) Figure 12. lotes on Testi: may allow the ground pin at the device to rise by 100's of ing millivolts momentarily. incoming test procedures on this device should be carefully a planned, taking into account the high complexity and power 4. Use extreme care in defining input levels for AC tests. Many levels of the part. The following notes may be useful. inputs may be changed at once, so there will be significant noise at the device pins and they may not actually reach Vi,_ 1. Insure the part is adequately decoupled at the test head. or Vix until the noise has settled. AMD recommends using Large changes in Voc current as the device switches may Vi SOV and Viq > 3.0V for AC tests. cause erroneous function failures due to Voc changes. 5. To simplity failure analysis, programs should be designed to 2. Do not leave inputs floating during any tests, as they may perform DC, Function, and AC tests as three distinct groups start to oscillate at high frequency. of tests. 3. Do not attempt to perform threshold tests at high speed. 6. To assist in testing, AMD offers complete documentation on Following an input transition, ground current may change by our test procedures and, in most cases, can provide as much as 400mA in 5-8ns. inductance in the ground cable Fairchild Sentry programs, under license. For additional information on testing, see section “Guidelines on Testing Am2900 Family Devices" in the Bipolar Microprocessor Logic and Interface Data Book. ore568 5-18 Refer to Page 13- for Essential Information on Milftary Devices