AM28F010A-150JEB

AM28F010A AMD | Alldatasheet

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Publication# 16778 Rev: D Amendment/ +2 Issue Date: May 1998 Am28F010A

1 Megabit (128 K x 8-Bit)

CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms DISTINCTIVE CHARACTERISTICS ■ High performance — Access times as fast as 70 ns ■ CMOS low power consumption — 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption ■ Compatible with JEDEC-standard byte-wide 32-pin EPROM pinouts — 32-pin PDIP — 32-pin PLCC — 32-pin TSOP ■ 100,000 write/erase cycles minimum ■ Write and erase voltage 12.0 V ±5% ■ Latch-up protected to 100 mA from –1 V to V CC +1 V ■ Embedded Erase Electrical Bulk Chip Erase — 5 seconds typical chip erase, including pre-programming ■ Embedded Program — 14 µs typical byte program, including time-out — 4 seconds typical chip program ■ Command register architecture for microprocessor/microcontroller compatible write interface ■ On-chip address and data latches ■ Advanced CMOS flash memory technology — Low cost single transistor memory cell ■ Embedded algorithms for completely self-timed write/erase operations GENERAL DESCRIPTION The Am28F010A is a 1 Megabit Flash memory orga- nized as 128 Kbytes of 8 bits each. AMD’s Flash memo- ries offer the most cost-effective and reliable read/write non-volatile random access memory. The Am28F010A is packaged in 32-pin PDIP , PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F010A is erased when shipped from the factory. The standard Am28F010A offers access times of as fast as 70 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#) and output enable (OE#) controls. AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F010A uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. The Am28F010A is compatible with the AMD Am28F256A, Am28F512A, and Am28F020A Flash memories. All devices in the Am28Fxxx family follow the JEDEC 32-pin pinout standard. In addition, all devices within this family that offer Embedded Algorithms use the same command set. This offers designers the flexi- bility to retain the same device footprint and command set, at any density between 256 Kbits and 2 Mbits. AMD’s Flash technology reliably stores memory con- tents even after 100,000 erase and program cycles. The AMD cell is designed to optimize the erase and program- ming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal elec- tric fields for erase and programming operations pro- duces reliable cycling. The Am28F010A uses a 12.0±5% V PP input to perform the erase and program- ming functions. The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up pro- tection is provided for stresses up to 100 mA on address and data pins from –1 V to V CC +1 V . AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F010A electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM pro- gramming mechanism of hot electron injection.

2 Am28F010A

The Am28F010A is byte programmable using the Embedded Program algorithm, which does not require the system to time-out or verify the data programmed. The typical room temperature programming time of this device is two seconds. Embedded Erase The entire device is bulk erased using the Embedded Erase algorithm, which automatically programs the entire array prior to electrical erase. The timing and ver- ification of electrical erase are controlled internal to the device. Typical erasure time at room temperature is five seconds, including preprogramming. Commands are written to the command register using standard microprocessor write timings. Register con- tents serve as input to an internal state-machine, which controls the erase and programming circuitry. During write cycles, the command register internally latches addresses and data needed for the program- ming and erase operations. For system design simpli- fication, the Am28F010A is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE#, whichever occurs last. Data is latched on the rising edge of WE# or CE#, whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms Am28F010A with Embedded Algorithms Am28F010 using AMD Flashrite and Flasherase Algorithms Embedded Programming Algorithm vs. Flashrite Programming Algorithm AMD’s Embedded Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, verifies the programming, and counts the number of sequences. A status bit, Data # Polling, provides the user with the programming operation status. The Flashrite Programming algorithm requires the user to write a program set-up command, a program command, (program data and address), and a program verify command, followed by a read and compare operation. The user is required to time the programming pulse width in order to issue the program verify command. An integrated stop timer prevents any possibility of overprogramming. Upon completion of this sequence, the data is read back from the device and compared by the user with the data intended to be written; if there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 25 times. Embedded Erase Algorithm vs. Flasherase Erase Algorithm AMD’s Embedded Erase algorithm requires the user to only write an erase set- up command and erase command. The device automatically pre-programs and verifies the entire array. The device then automatically times the erase pulse width, verifies the erase operation, and counts the number of sequences. A status bit, Data # Polling, provides the user with the erase operation status. The Flasherase Erase algorithm requires the device to be completely programmed prior to executing an erase command. To invoke the erase operation, the user writes an erase set-up command, an erase command, and an erase verify command. The user is required to time the erase pulse width in order to issue the erase verify command. An integrated stop timer prevents any possibility of overerasure. Upon completion of this sequence, the data is read back from the device and compared by the user with erased data. If there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 1,000 times.

Family Part Number Am28F010A Speed Options (VCC = 5.0 V ± 10%) -70 -90 -120 -150 -200 Max Access Time (ns) 70 90 120 150 200 CE # (E#) Access (ns) 70 90 120 150 200 OE # (G#) Access (ns) 35 35 50 55 55 16778D-1 Erase Voltage Switch Input/Output Buffers Data Latch Y-Gating 1,048,576 Bit Cell Matrix X-Decoder Y-Decoder Chip Enable Output Enable Logic Program/Erase Pulse Timer Low VCC Detector Command Register WE # CE # OE # A0–A16 DQ0–DQ7 VCC VSS Address Latch State Control VPP To Array Program Voltage Switch Embedded Algorithms

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Note: Pin 1 is marked for orientation. 16778D-2 VCC WE # (W#) NC A14 A13 A11 OE # (G#) A10 CE # (E#) DQ7 DQ6 DQ5 DQ4 DQ3 V PP A16 A15 A12 DQ0 DQ1 DQ2 V SS 17 18 19 20161514 13 1 3 02343 2 DQ0 A14 A13 A11 OE (G) A10 CE# (E#) DQ7 A12 A15 A16 V PP VCC WE# (W#) NC DQ1 DQ2 V SS DQ3 DQ4 DQ5 DQ6 16778D-3

CONNECTION DIAGRAMS (continued) LOGIC SYMBOL A11 A13 A14 NC WE# VCC VPP A16 A15 A12 OE# A10 CE# VSS A11 A13 A14 NC WE# VCC VPP A16 A15 A12 OE# A10 CE# VSS 16778D-4 32-Pin TSOP—Standard Pinout 32-Pin TSOP—Reverse Pinout DQ0–DQ7 A0–A16 CE # (E#) OE # (G#) WE # (W#) 16778D-5

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be support- ed in volume for this device. Consult the local AMD sales of- fice to confirm availability of specific valid combinations and to check on newly released combinations. DEVICE NUMBER/DESCRIPTION Am28F010A

1 Megabit (128 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms

Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C= Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations B Valid Combinations AM28F010A-70 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE AM28F010A-90 AM28F010A-120 AM28F010A-150 AM28F010A-200

A0–A16 Address Inputs for memory locations. Internal latches hold addresses during write cycles. CE # (E#) Chip Enable active low input activates the chip’s control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode. DQ0–DQ7 Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles. NC No Connect—corresponding pin is not connected internally to the die. OE # (G#) Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. Output Enable is high during command sequencing and program/erase operations. VCC Power supply for device operation. (5.0 V ± 5% or 10%) VPP Program voltage input. VPP must be at high voltage in order to write to the command register. The command register controls all functions required to alter the mem- ory array contents. Memory contents cannot be altered when V PP ≤ VCC +2 V. VSS Ground WE # (W#) Write Enable active low input controls the write function of the command register to the memory array. The tar- get address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writ- ing to the device.

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This section contains descriptions about the device read, erase, and program operations, and write opera- tion status of the Am29FxxxA, 12.0 volt family of Flash devices. References to some tables or figures may be given in generic form, such as “Command Definitions table”, rather than “Table 1”. Refer to the corresponding data sheet for the actual table or figure. The Am28FxxxA family uses 100% TTL-level control inputs to manage the command register. Erase and reprogramming operations use a fixed 12.0 V ± 5% high voltage input. Read Only Memory Without high VPP voltage, the device functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes. Command Register The command register is enabled only when high volt- age is applied to the V PP pin. The erase and repro- gramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The tradi- tional read, standby, output disable, and Auto select modes are available via the register. The device’s command register is written using standard microprocessor write timings. The register controls an internal state machine that manages all device opera- tions. For system design simplification, the device is de- signed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# which- ever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with re- spect to the WE# signal. OVERVIEW OF ERASE/PROGRAM OPERATIONS Embedded Erase Algorithm AMD now makes erasure extremely simple and reli- able. The Embedded Erase algorithm requires the user to only write an erase setup command and erase com- mand. The device will automatically pre-program and verify the entire array. The device automatically times the erase pulse width, provides the erase verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the erase operation. Embedded Programming Algorithm AMD now makes programming extremely simple and reliable. The Embedded Programming algorithm re- quires the user to only write a program setup command and a program command. The device automatically times the programming pulse width, provides the pro- gram verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the programming operation. DATA PROTECTION The device is designed to offer protection against acci- dental erasure or programming caused by spurious system level signals that may exist during power transi- tions. The device powers up in its read only state. Also, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. The device also incorporates several features to pre- vent inadvertent write cycles resulting from V CC power-up and power-down transitions or system noise. Low V CC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for V CC < VLKO (see DC characteristics section for volt- ages). When VCC < VLKO , the command register is dis- abled, all internal program/erase circuits are disabled, and the device resets to the read mode. The device ig- nores all writes until V CC > VLKO . The user must ensure that the control pins are in the correct logic state when V CC > VLKO to prevent unintentional writes. Write Pulse “Glitch” Protection Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE# = VIL, CE#=V IH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit Power-up of the device with WE# = CE# = VIL and OE# = VIH will not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up.

Table 1. Am28F010A Device Bus Operations (Notes 7 and 8) of VPPH . 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

1. VPPL may be grounded, connected with a resistor to ground, or < VCC + 2.0 V. VPPH is the programming voltage specified for

the device. Refer to the DC characteristics. When VPP = VPPL , memory contents can be read but not written or erased.

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.
2. Read operation with VPP = VPPH may access array data or the Auto select codes.
3. With VPP at high voltage, the standby current is ICC + IPP (standby).
4. Refer to Table 3 for valid DIN during a write operation.
5. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either VIL or VIH levels. In the Auto select mode all

addresses except A9 and A0 must be held at VIL.

1. If VCC ≤ 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP

rise time and fall time specification of 500 ns minimum.

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lect data, or be standby mode. draw active current until the operation is terminated. to soldering the device to the board. functional over the entire temperature range of the device. MSB (DQ7) defined as the parity bit. Table 2. Am28F010A Auto Select Code

command will not be executed. gramming Waveforms for specific timing parameters. writing specific data codes into the command register. register contents are altered. Waveforms for the specific timing parameters. Table 3. Am28F010A Command Definitions

1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# pulse.

1. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.

1. Please reference Reset Command section.

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verify the entire memory for an all zero data pattern. timing during these operations. tion) atwhich time the device returns to Read mode. timing during these operations. standard erase verify command is used. gorithm, a typical command string and bus operation. Table 4. Embedded Erase Algorithm Figure 1. Embedded Erase Algorithm

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are either in progress or completed. the two write pulse sequence. the two Write pulse sequence. ded Programming or erase algorithms. an alternative method is available using Toggle Bit. DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5 or after DQ5. Figure 3. Data# Polling Algorithm

Figure 4. AC Waveforms for Data# Polling during Embedded Algorithm Operations

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rithms are either in progress or completed. DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”. Figure 5. Toggle Bit Algorithm

corresponding device data sheet. lel erase algorithm, total erase time may be minimized.

1.0 Volt, the voltage difference between VPP and VCC

(including program or erase). reset the device to the Read mode. first Reset command is interpreted as program data. resets the device to the Read mode. Memory contents are not altered in any case. Figure 6. AC Waveforms for Toggle Bit during Embedded Algorithm Operations

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This detailed information is for your reference. It may prove easier to always issue the Reset command two consecutive times. This eliminates the need to deter- mine if you are in the Setup Program state or not. In-System Programming Considerations Flash memories can be programmed in-system or in a standard PROM programmer. The device may be sol- dered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the circuit board. Auto Select Command AMD’s Flash memories are designed for use in appli- cations where the local CPU alters memory contents. In order to correctly program any Flash memories in-system, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access the sig- nature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a generally desired system design practice. The device contains an Auto Select operation to supple- ment traditional PROM programming methodologies. The operation is initiated by writing 80h or 90h into the command register. Following this command, a read cycle address 0000h retrieves the manufacturer code of 01h (AMD). A read cycle from address 0001h returns the device code (see the Auto Select Code table of the corresponding device data sheet). To terminate the op- eration, it is necessary to write another valid command, such as Reset (00h or FFh), into the register.

Voltage with Respect to Ground All pins except A9 and VPP (Note 1) .–2.0 V to +7.0 V Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9 and VPP is –0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 and VPP is +13.0 V, which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Industrial (I) Devices Extended (E) Devices Ambient Temperature (T VCC Supply Voltages VPP Voltages Operating ranges define those limits between which the functionality of the device is guaranteed.

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+0.8 V –0.5 V 20 ns –2.0 V 16778D-12 Maximum Negative Input Overshoot 20 ns VCC + 0.5 V 2.0 V 20 ns 20 ns VCC + 2.0 V 16778D-13 Maximum Positive Input Overshoot 16778D-14 Maximum V PP Overshoot 20 ns 13.5 V VCC + 0.5 V 20 ns 20 ns 14.0 V

DC CHARACTERISTICS over operating range unless otherwise specified TTL/NMOS Compatible Notes: 1. Caution: The Am28F010A must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC ≤ 1.0 volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F010A has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP. 4. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V CC = VCC Max, VIN = VCC or VSS ±1.0 µA ILO Output Leakage Current V CC = VCC Max, VOUT = VCC or VSS ±1.0 µA ICCS VCC Standby Current V CC = VCC Max, CE# = VIH 0.2 1.0 mA ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE # = VIH IOUT = 0 mA, at 6 MHz 20 30 mA ICC2 VCC Programming Current CE = VIL Programming in Progress (Note 4) 20 30 mA ICC3 VCC Erase Current CE # = VIL Erasure in Progress (Note 4) 20 30 mA IPPS VPP Standby Current V PP = VPPL ±1.0 µA IPP1 VPP Read Current VPP = VPPH 70 200 µA VPP = VPPL ±1.0 IPP2 VPP Programming Current VPP = VPPH Programming in Progress (Note 4) 10 30 mA IPP3 VPP Erase Current VPP = VPPH Erasure in Progress (Note 4) 10 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.5 V VOL Output Low Voltage I OL = 5.8 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage I OH = –2.5 mA, VCC = VCC Min 2.4 V VID A9 Auto Select Voltage A9 = V ID 11.5 13.0 V IID A9 Auto Select Current A9 = V ID Max, VCC = VCC Max 5 50 µA VPPL VPP during Read-Only Operations Note: Erase/Program are inhibited when VPP = VPPL 0.0 V CC +2.0 V VPPH VPP during Read/Write Operations 11.4 12.6 V VLKO Low VCC Lock-out Voltage 3.2 3.7 V

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Notes: 1. Caution: The Am28F010A must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC ≤ 1.0 volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F010A has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP. 4. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V CC = VCC Max, VIN = VCC or VSS ±1.0 µA ILO Output Leakage Current V CC = VCC Max, VOUT = VCC or VSS ±1.0 µA ICCS VCC Standby Current V CC = VCC Max, CE# = VCC ±0.5 V 15 100 µA ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE # = VIH IOUT = 0 mA, at 6 MHz 20 30 mA ICC2 VCC Programming Current CE # = VIL Programming in Progress (Note 4) 20 30 mA ICC3 VCC Erase Current CE # = VIL Erasure in Progress (Note 4) 20 30 mA IPPS VPP Standby Current V PP = VPPL ±1.0 µA IPP1 VPP Read Current V PP = VPPH 70 200 µA IPP2 VPP Programming Current VPP = VPPH Programming in Progress (Note 4) 10 30 mA IPP3 VPP Erase Current VPP = VPPH Erasure in Progress (Note 4) 10 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 V CC VCC + 0.5 V VOL Output Low Voltage I OL = 5.8 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC Min V CC –0.4 VID A9 Auto Select Voltage A9 = V ID 11.5 13.0 V IID A9 Auto Select Current A9 = V ID Max, VCC = VCC Max 5 50 µA VPPL VPPL during Read-Only Operations Note: Erase/Program are inhibited when VPP = VPPL 0.0 V CC + 2.0 V VPPH VPP during Read/Write Operations 11.4 12.6 V VLKO Low VCC Lock-out Voltage 3.2 3.7 V

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SWITCHING CHARACTERISTICS over operating range, unless otherwise specified AC Characteristics—Read-Only Operations Notes: 1. Guaranteed by design; not tested. 2. Not 100% tested. Parameter Symbols Am28F010A Speed Options JEDEC Standard Parameter Description -70 -90 -120 -150 -200 Unit tAVAV tRC Read Cycle Time (Note 3) Min 70 90 120 150 200 ns tELQV tCE Chip Enable Access Time Max 70 90 120 150 200 ns tAVQV tACC Address Access Time Max 70 90 120 150 200 ns tGLQV tOE Output Enable Access Time Max 35 35 50 55 55 ns tELQX tLZ C h i p E n a b l e t o O u t p u t i n L o w Z ( N o t e 3 ) M i n 00000 n s tEHQZ tDF Chip Disable to Output in High Z (Note 1) Max 20 20 30 35 35 ns tGLQX tOLZ Output Enable to Output in Low Z (Note 3) Min00000 n s tGHQZ tDF Output Disable to Output in High Z (Note 3) Max 20 20 30 35 35 ns tAXQX tOH Output Hold Time From First Address, CE#, or OE# change (Note 3) M i n 00000 n s tVCS VCC Set-up Time to Valid Read (Note 3) Min 50 50 50 50 50 ns 16778D-17 3 V 0 V Input Output 1.5 V 1.5 VTe s t Po i n ts AC Testing for -70 devices: Inputs are driven at 3.0 V for a logic “1” and 0 V for a logic “0”. Input pulse rise and fall times are ≤10 ns. 2.4 V 0.45 V Input Output Test Points 2.0 V 2.0 V 0.8 V0.8 V AC Testing (all speed options except -70): Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are ≤10 ns.

AC Characteristics—Write (Erase/Program) Operations Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Embedded Program Operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the minimum time for one pass through the programming algorithm. 3. Embedded Erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested. Parameter Symbols Am28F010A Speed Options JEDEC Standard Description -70 -90 -120 -150 -200 Unit tAVAV tWC Write Cycle Time (Note 4) Min 70 90 120 150 200 ns tAVWL tAS A d d r e s s S e t u p T i m e M i n 00000 n s tWLAX tAH Address Hold Time Min 45 45 50 60 75 ns tDVWH tDS Data Setup Time Min 45 45 50 50 50 ns tWHDX tDH Data Hold Time Min 10 10 10 10 10 ns tOEH Output Enable Hold Time for Embedded Algorithm only M i n 1 01 01 01 01 0 n s tGHWL R e a d R e c o v e r y T I m e B e f o r e W r i t e M i n 00000 n s tELWLE tCSE CE # Embedded Algorithm Setup TIme Min 20 20 20 20 20 ns tWHEH tCH CE # H o l d T I m e M i n 00000 n s tWLWH tWP Write Pulse Width Min 45 45 50 60 60 ns tWHWL tWPH Write Pulse Width High Min 20 20 20 20 20 ns tWHWH3 Embedded Program Operation (Note 2) Min 14 14 14 14 14 µs tWHWH4 Embedded Erase Operation (Note 3) Typ 5 5555 s e c tVPEL VPP Setup Time to Chip Enable Low (Note 4) Min 100 100 100 100 100 ns tVCS VCC Setup TIme (Note 4) Min 50 50 50 50 50 µs tVPPR VPP Rise Time (Note 4) 90% VPPH Min 500 500 500 500 500 ns tVPPF VPP Fall Time (Note 4) 90% VPPL Min 500 500 500 500 500 ns tLKO VCC < VLKO to Reset (Note 4) Min 100 100 100 100 100 ns

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Figure 9. AC Waveforms for Read Operations

DQ7 # is the complement of the data written to the device. Figure 10. AC Waveforms for Embedded Erase Operation

28 Am28F010A

D IN is data input to the device. DQ7 # is the complement of the data written to the device. D OUT is the data written to the device. Figure 11. AC Waveforms for Embedded Programming Operation

AC Characteristics—Write (Erase/Program) Operations Alternate CE# Controlled Writes Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Embedded Program Operation of 14 µs consists of 10 µs program pulse and 4 µs write recovery before read. This is the minimum time for one pass through the programming algorithm. 3. Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested. Parameter Symbols Am28F010A Speed Options JEDEC Standard Description -70 -90 -120 -150 -200 Unit tAVAV tWC Write Cycle Time (Note 4) Min 70 90 120 150 200 ns tAVEL tAS A d d r e s s S e t u p T i m e M i n 00000 n s tELAX tAH Address Hold Time Min 45 45 50 60 75 ns tDVEH tDS Data Setup Time Min 45 45 50 50 50 ns tEHDX tDH Data Hold Time Min 10 10 10 10 10 ns tOEH Output Enable Hold Time for Embedded Algorithm only M i n 1 01 01 01 01 0 n s tGHEL R e a d R e c o v e r y T i m e B e f o r e W r i t e M i n 00000 n s tWLEL tWS WE # Setup Time by CE# M i n 00000 n s tEHWK tWH CE # H o l d T i m e M i n 00000 n s tELEH tCP Write Pulse Width Min 65 65 70 80 80 ns tEHEL tCPH Write Pulse Width High Min 20 20 20 20 20 ns tEHEH3 Embedded Program Operation (Note 2) Min 14 14 14 14 14 µs tEHEH4 Embedded Erase Operation (Note 2) Typ 5 5555 s e c tVPEL VPP Setup Time to Chip Enable Low (Note 3) Min 100 100 100 100 100 ns tVCS VCC Setup Time (Note 3) Min 50 50 50 50 50 µs tVPPR VPP Rise Time (Note 3) 90% VPPH Min 500 500 500 500 500 ns tVPPF VPP Fall Time (Note 3) 90% VPPL Min 500 500 500 500 500 ns tLKO VCC < VLKO to Reset (Note 3) Min 100 100 100 100 100 ns

30 Am28F010A

D IN is data input to the device. DQ7 # is the complement of the data written to the device. D OUT is the data written to the device. Figure 12. AC Waveforms for Embedded Programming Operation Using CE# Controlled Writes

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. 25°C, 12 V VPP. 2. Maximum time specified is lower than worst case. Worst case is derived from the embedded algorithm internal counter which allows for a maximum 6000 pulses for both program and erase operations. Typical worst case for program and erase is significantly less than the actual device limit. 3. Typical worst case = 84 µs. DQ5 = “1” only after a byte takes longer than 96 ms to program. LATCHUP CHARACTERISTICS PIN CAPACITANCE Note: Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Limits CommentsMin Typ (Note 1) Max (Note 2) Unit Chip Erase Time 1 10 sec Excludes 00h programming prior to erasure Chip Programming Time 2 12.5 sec Excludes system-level overhead Write/Erase Cycles 100,000 Cycles Byte Programming Time 14 µs (Note 3) ms Parameter Min Max Input Voltage with respect to V SS on all pins except I/O pins (Including A9 and VPP ) –1.0 V 13.5 V Input Voltage with respect to VSS on all pins I/O pins –1.0 V V CC + 1.0 V Current –100 mA +100 mA Includes all pins except VCC . Test conditions: VCC = 5.0 V, one pin at a time. Parameter Symbol Parameter Description Test Conditions Typ Max Unit C IN Input Capacitance V IN = 0 8 10 pF C OUT Output Capacitance V OUT = 0 8 12 pF C IN2 VPP Input Capacitance V PP = 0 8 12 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

32 Am28F010A

PD032—32-Pin Plastic DIP (measured in inches) PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches) Pin 1 I.D. 1.640 1.670 .530 .580 .005 MIN .045 .065 .090 .110 .140 .225 .120 .160 .016 .022 SEATING PLANE .015 .060 16-038-S_AG PD 032 EC75 5-28-97 lv 32 17 16 .630 .700 10° .600 .625 .009 .015 .050 REF..026 .032 TOP VIEW Pin 1 I.D. .485 .495.447 .453 .585 .595 .547 .553 16-038FPO-5 PL 032 DA79 6-28-94 ae SIDE VIEW SEATING PLANE .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 REF. .490 .530

33 Am28F010A

TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 18.30 18.50 7.90 8.10

0.50 BSC

0.05 0.15 0.95 1.05 16-038-TSOP-2 TS 032 DA95 3-25-97 lv 19.80 20.20 1.20 MAX 0.50 0.70 0.10 0.21 0.08 0.20

TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters) 18.30 18.50 19.80 20.20 7.90 8.10 0.05 0.15 0.95 1.05 16-038-TSOP-2 TSR032 DA95 3-25-97 lv Pin 1 I.D. 1.20 MAX 0.50 0.70 0.10 0.21 0.08 0.20

35 Am28F010A

DATA SHEET REVISION SUMMARY FOR AM28F010A Revision C+1 Distinctive Characteristics: High Performance: The fastest speed option available is now 70 ns. General Description: Paragraph 2: Changed fastest speed option to 70 ns. Product Selector Guide: Added -70, deleted -95 and -250 speed options. Ordering Information, Standard Products: The -70 speed option is now listed in the example. Valid Combinations: Added -70, deleted -95 and -250 combinations. Operating Ranges: VCC Supply Voltages: Added -70, deleted -95 and -250 speed options in the list. AC Characteristics: Read Only Operations Characteristics: Added the -70 column and test conditions. Deleted -95 and -250 speed options. AC Characteristics: Write/Erase/Program Operations, Alternate CE# Con- trolled Writes: Added the -70 column. Deleted -95 and -250 speed options. Switching Test Waveforms: In the 3.0 V waveform caption, changed -95 to -70. Revision D Matched formatting to other current data sheets. Revision D+1 Programming In A PROM Programmer: Deleted the paragraph “(Refer to the AUTO SELECT paragraph in the ERASE, PROGRAM, and READ MODE section for programming the Flash memory de- vice in-system).” Revision D+2 General Description Embedded Program: Changed “The typical room tem- perature programming time of this device is four sec- onds.” to “The typical room temperature programming time of this device is two seconds.” Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. ExpressFlash is a trademark of Advanced Micro Devices, Inc. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.