AM2833 AMD | Alldatasheet

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1024-Bit Static Shift Registers ———— Distinctive Characteristics © Second source to Signetics 2533 © 100% reliability assurance testing in compliance with © All inputs are low-level DTL/TTL compatible MIL-STD-883. © Static operation with single clock input. ®@ DC to 2.0MHz operation with Am2833 FUNCTIONAL DESCRIPTION Logic symBo The Am2533/2833 is a quasi-static 1024-bit MOS shift register using low-threshold P-channel silicon gate tech- nology. The device has a single TTL/DTL compatible clock input, a Cp. Data in the register is stored in static, cross-coupled se smussions latches while the clock is LOW, so that the clock may be > }, 102eat emiPT RegisteR OUT ' stopped indefinitely in the LOW state, When the clock ote shifts from LOW to HIGH to LOW a dynamic transfer of data occurs from one static latch to the next. The input of i the register is a two-input multiplexer with both data in- puts available, A select line, S, determines whether data will Vee «P, be accepted from the Ig input (S = LOW) or the 1} input veo wine (S = HIGH). The register can be placed in the recirculate Vous Pana mode by tying the output, O, to one of the data inputs, and ° using the select fine as a write/recirculate control. The ‘Am2833 is functionally identical to the Am2533 but has superior performance over an extended temperature range. Mos-429 LOGIC DIAGRAM a [= Db a wears gut i ie s cr Os-«90 ORDERING INFORMATION CONNECTION DIAGRAM Top View Am2533Am2833 or EWvccrsovr Package Temperature Order Order Type Flange Number __ Number eavives] = Molded DIP OC to #70°C_-— AM 2533 AM2839PC. sc a Hermetic DIP 0°C to #70°C AM2533DC = AM28330C Hermetic DIP —85°C to +128°C AM2833DM (GN0WVo9 CI Dic Note: Pin 1 marked for orientation Mos-491 5-36

MAXIMUM RATING (Above which the useful life may be impaired) Storage Temperature 65°C to +150°C Temperature (Ambient) Under Bias 85°C to +125°C Vop Supply Voltage Veo —20V to Voc +0.3V Vaa Supply Voltage Voc —20V to Voc +0.3V DC Input Voltage Veo —20V to Voc +0.3V OPERATING RANGE Part No. Temperature Vee Veo Voo Am2833PC/Am2533PC ° 470°! * ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted) Typ. . Parameters Description Test Conditions Min, (Note?) Max. Units [von] Output HIGH Vorane Voo= MIN, lon =—10008 [24] LT vere] Vou | Output LOW Voltage Vec=MINvigu=tomASS~—~wSCSsC~C~sd [oa | vors_| ~ Guaranteed input logical Vec-! f evel 13 | Vol vin | inet HIGH Level HIGH voltage for all inputs (Note 3) Vecr0.s ons Guaranteed input logical LOW 1 Te input LOW Curent Voc = MAX., Vin =OV, Ta = 25°C ee on “Faput HIGH Current | ‘Ta = 25°C, Vin = Veg —1.0 (Note 3) a Peak input transition | _ ers ir current (Note 3) 1.5 < Vgg — Vin < 4.0, Ta = 25°C “16 [om | Vimax | Voltage at maximum os - - 2 [opetsmie [ Amasas [Pte too | poe Power Sveply yo 20WH amaezarc,0e | «| 8A ms | SONNE ~___Am28330M 7 - 20 Veg power Suppl feteMHe | A233 a 50 Igo | oa Fomer surely + 20mHe 1 ‘Am2B33PC, OC =50 [ie | ma “ : [Amaasabw 708 Notes: 1, Typical limits are at Vec = §.0V, Vag = —12V, 25°C ambient. 2) Power supply currants are with inputs ang outputs open, 3. A spec input pull-up circuit becomes active at Vipy = Vg ~2.5V to pull the internal input node up to the MOS threshold. To return the ‘iauenal nowe to the LOW state, current must be drawn trem the MOS input, This current is maximum at approximately 2.0V. SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unies Otherwise Noted) ‘Am2533 Am2833 . Typ. Typ. Parameters Description Test Conditions Min. (Note 1) Max. Min, (Note 1)_ Max, Units (inex [Wminceerreaeey [Ts Tze aot go | [me | [teaat | Cocktow tine p00 nao f= [Rout | Clock HIGH Tine sd SSSSS~ 8 | t00 Loz fro | Glock Rise and Fall Times _ — ee tn) Set-up Time, Ig or 1 Input (see definitions) Wold Time, 19 ory Input 50 (see definitions)

28 Setintions) _—_ t= ty < 2508

Set-up Time, S Input 80 (see definitions) Hold Time, § Input {see definitions) Delay, Clock to Output . . Vip [oonmmwnanitime | wows | [Gin | Capacitance, Any Input (Note 2) f= MHz, Vin = Voc pose tt | F | Notes: 1. Typical limits are at Voc ~ 5.0V, Vgg = —12.0V and Ta = 25°C 2. This perametor Is periodically sampled but not 100% tested, It is guaranteed by design. 5:37

TIMING DIAGRAM. aya ov eoolt 10% wena 10% gt) MAX fa + ttl MAX. | _ XY XXX Y XY \\/ \\XXX Y XXXX Y XX YY XXX VYVYVYY XX YVY ARRAN KS | RRR RAR RRR ov KXXAXKKXKX A PRXOOO OO XA “ AV AVAVAVAAVAVAVAVAVAVAVAVA AVAVAVAVAVAVAVAVAVAVAVAVAVAVAN, YYYVVYVY Dn EEE ee wv LOOK DOKXK : “ WYYYYVYYVYV YYVYV YY YY YY YYYVY ORREW RRR) AIRY ow XXXXXXXXX) | XXXXKXXKAXK A DRX co YARRA RRR ov DPXXKXXX oa DXXXKXX | TYPICAL PERFORMANCE CURVES, Power Dissipation tpd asa Function Versus Ambient Temperature +0 of Ambient Temperature «of of ven fb LL eb N re DEFINITION OF TERMS SET-UP and HOLD TIMES The shift register will accept the data that is present on its input around the time the lock goes from STATIC SHIFT REGISTER A shift register that is capable of HIGH-to-LOW. Because of variations in individual devices, there maintaining stored data without being continuously clocked. is some uncertainty as to exactly when, relative to this clock Most Static shift registers are constructed with dynamic master transition, the data will be stored. The set-up and hold times and static slave flip-flops. The data is stored dynamically while define the limits on this uncertainty. To guarantee storing the the clock is HIGH and is transferred to the static slaves while the correct data, the data inputs should not be changed between clock is LOW. The clock may be stopped indefinitely in the the maximum set-up time before the clock transition and the LOW state, but there are limitations on the time it may reside maximum hold time after the clock transition, Data changes in the HIGH state. within this interval may or may not be detected. 5-38

APPLICATIONS

[7 | vee sor hTBEooun sooe af an RESISTER saa arr eoTER o173e5e789 I “a a | Vit) ‘ a briit i seats oak REGISTER in ae ef MEGISTER 7 | i a Pt enetnene Eight Register 2048-Bit Memory System oaTAOUT Data enters one of the eight 2048-bit registers when the write enable input to the decoder is LOW. The addressed register will accept the data on the data input; the other seven registers will recirculate their data. Outputs are driven directly into an Am9312 8-input multiplexer. Obviously, the read and write registers need not be the same. Mos-434 TRUTH TABLE s lo in Data Entered v L x v L 4 x H 4 x L L 4 x 4 4 H= HIGH Voltage tevel L = LOW Voltage Level X= Don't Care Metallization and Pad Layout f TTT EIA ou Veo 2——Hfl | 7 il , so i] DIE SIZE: 0.133" X 0.163" 5:39