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semiconductors Nov. 2020 V0.6 - 1 - AM2789 Three Phase Brushless Motor Driver  Features  2.7V to 15V Operating Voltage Range  3.5A Maximum Continuous Current  Wide PWM input operating range to 100KHz  Low MOSFET ON-resistance: HS + LS = 90mΩ  Operating ambient junction temperature: -20℃ ~85℃  Built-in precise LDO Regulator 3.3V ±3%  Turbo current limit function adjusts by external Re s ist or.  Over temperature protection  QFN5 X 5 Package for small PCB layout  Halogen-Free Green Product & RoHS compliant Package  Application  Gimbal  Robotics  Consumer products  Household appliance  For 1~3 cells Li batteries source application.  Description The AM2789 provides three individual controllable half-bridge drivers. The device is intended to drive a three-phase brushless DC motor, though it can also be used to drive solenoids or other types of load. Each output driver channel consists of P-channel +N-channel power MOSFETs in a half-bridge configuration. The AM2789 can supply up to 6A peak or 3.5A continuous output current per channel (with proper PCB heat sink at 10V and 25℃) per half-Bridge. There is internal shutdown function for over-temperature protection. The device provides internal shutdown functions for Short-circuit protection, turbo current limit and over temperature protection.  Ordering Information Part number Package Body Size AM2789 QFN 5X5 5.0mm X 5.0mm

semiconductors Nov. 2020 V0.6 - 2 -  Absolute Maximum Ratings (TA=25℃) Parameter Symbol Limits Unit Power Supply Voltage PVCC_X 19 V Analog Supply Voltage VCC 19 V Output Continuous Current Io CONT 3.5 A Output Peak Current Io peak 6 A Operate Temperature Range Topr -20~+85 ℃ Storage Temperature Range Tstg -40~+150 ℃  ESD Rating Value Unit V(ESD) Electrostatic discharge Human Body Mode(HBM) (1) 4000 V (1) The test method refers to JEDEC EIA/JESD22-A114-B.  Recommended Operating Conditions (TA =25℃) (Set the power supply voltage taking allowable dissipation into considering) Parameter Symbol Min Typ Max Unit Power Supply Voltage PVCC_X 2.7(note) 10 15 V Analog Supply Voltage VCC 2.7(note) 10 15 V PWM_X and STBY_X VPWM_X / VSTBY_X -0.3 3.3 3.7 V H-Bridge Output Continuous Current IOUT 3.5 A Externally Applied PWM Frequency FPWM 0.02 100 KHz Note: 1. The LDO_3.3V operation range should be considered in choosing VCC. 2. The LDO 3.3V operation range should be considered in choosing VCC and LDO voltage drop 0.4V max at ILDO=100mA.

semiconductors Nov. 2020 V0.6 - 3 -  Electrical Characteristics ( Unless otherwise specified, TA = 25℃,PVCC=VCC=10V) Parameter Symbol Value Unit Condition MIN TYP MAX Power Supply VCC/PVCC Operating Current 1 ICC1 0.5 mA PWM_X=STBY_X=L VCC/PVCC Operating Current 2 ICC2 1 mA PWM_X=STBY_X=H LDO Output Voltage VLDO 3.2 3.3 3.4 V ILDO=100mA, VCC=10V Dropout Voltage VDO - - 400 mV ILDO=100mA, VLDO=3.3V PWM_X/STBY_X Inputs Input High Level Logic VPWM_XH VSTBY_XH 2.0 3.5 V Input Low Level Logic VPWM_XL VSTBY_XL 0 0.7 V Input Frequency FPWM 0.02 100 kHz Input Pull-up Resistance RIPD 100 KΩ Input Pull-down Resistance RIPD 130 KΩ H-Bridge FETs Rds(on) HS+LS FET On-resistance Rds(on) 90 mΩ ILoad = 1A, TJ: 25℃ Current Sense Input Current Sense Voltage VCS 120 150 180 mV

semiconductors Nov. 2020 V0.6 - 4 -  Pin configuration QFN 5X5 1STBYC 2STBYB 3STBYA ERR LDO CS 26 25 24 PWMC PWMB PWMA 5VCC 4AGND 6PVCC AGND 9 10 11 12 OUTB PG_B 16151413 OUTA PG_A 20 21 22 23 OUTC PG_C

19 PVCCPVCC30

 Pin Descriptions PIN Number Pin Name I/O Description

1 STBYC I Standby Input C

2 STBYB I Standby Input B

3 STBYA I Standby Input A

4 AGND - Analog Ground

5 VCC - Analog Power Supply

6, 19, 30 PVCC - Power Supply of Half Bridge 7, 8, 9, 10 OUTB O Output of Half Bridge B 11, 12 PG_B - Power GND of Half Bridge B 13, 14 PG_A - Power GND of Half Bridge A 15, 16, 17, 18 OUTA O Output of Half Bridge A

semiconductors Nov. 2020 V0.6 - 5 -  Block Diagram Control Input Core Logic & Pre-deiver AHG OUTB AGND ALG BHG BLG CHG CLG OUTA OUTC STBYA STBYB STBYC PWMA PWMB PWMC VCC Current limit LDOLDO CS ALG AHG PG_A CLG CHG PG_C BLG BHG PVCC PG_B ERR 20, 21 OUTC O Output of Half Bridge C 22, 23 PG_C - Power GND of Half Bridge C

24 PWMA I Driver Logic Input A

25 PWMB I Driver Logic Input B

26 PWMC I Driver Logic Input C

27 CS I Current Sense

28 LDO O Low Dropout Regulator

29 ERR I Error Output

semiconductors Nov. 2020 V0.6 - 6 -  Application Circuit AM2789 STBYA STBYC STBYA STBYC PWMB PWMB STBYB STBYB PWMA PWMA PWMC PWMC OUTA OUTB M OUTC GND PG_B 75mΩ/1W PG_A CS 223 PG_C104100uF/16V VCC PVCC 0 Ω LDO 105 ERR 104 104 104 C5 LDO PVCC ERR Description: 1. The C1、C2、C3、C4 are power supply stabilization for both PWM driver and kickback absorption. A large capacitor C1 must be used when the coil inductance is large or when coil resistance is low. The pattern connecting to PVCC and GND must be as wide and as short as possible. 2. The C5 is analog power supply stabilization. The pattern connecting to VCC and GND must be as short as possible. 3. AM2789 LDO output are for internal reference voltage using, the Vref and LDO output should be always turn on, C6 capacitor must be connect to GND. 4. R2 is a current sense resistor . R3 and C8 as a low pass filter to catch the voltage of R2 for current sense function. If the current sense function is not needed then short PG_A, PG_B, PG_C, CS PIN to GND 5. ERR PIN can provide an error massage to MCU. As close as possible to PVCC Current limit function, if it is no needed, the CS pin should connect to GND.

semiconductors Nov. 2020 V0.6 - 7 -  Application Note 1) PVCC Capacitor: The PVCC capacitor is power supply stabilization for both PWM driver and kickback absorption. Normally PVCC Capacitor is 47~100uF. The pattern connecting to PVCC and GND must be as wide and as short as possible 2) VCC Capacitor: The VCC capacitor is power supply stabilization. Low pass filter is composed of R and C can be used to suppress PWM driver noise and kickback absorption. Normally R=0ohm, C=0.1uF. The pattern connecting to VCC and GND must be as short as possible. 3) LDO Capacitor: Recommend Capacitor=1μF or more. 4) CS: CS is current limit input pin. There is a reference voltage (150mV_TYP) at input node A of comparator. The input node B of comparator is CS. When input voltage of CS >150mV, that will trigger current limit function to keep output current on setting value. ERR: ERR is an error message output pin. ERR pin can provide an error message to MCU. Error message signal includes TSD function. When IC is operating normally, ERR keep high level signal, When IC is operating abnormally, ERR pull low level signal which feedback to MCU. 6) Setting Current limiter design target: The current limiter value is calculated in equation SENSE LIMITED R mVI 150= For example: If design target for current limiter is 3A, the RSENSE value may be calculated as following: Ω=== mA mV I mVR LIMITED SENSE 503 150150 Please follow steps to set up RSENSE value in real application circuit Step 1. Initial setting R3=1KΩ, then calculate RSENSE: EX1 : If current limit setting ILIMITED =3A; Ω=⇒= mA mV I mVR LIMITED SENSE 503 150150 , Initial value R SENSE =50mΩ、R3=1KΩ、C8=22nF, the motor output waveform is as follows:

semiconductors Nov. 2020 V0.6 - 8 - There are different type motors which have different inductive reactance and resistance, customers have to follow real motor load status to optimize RSENSE limit value; therefore, please follow step 2、step 3 to optimize C8 and RSENSE value again. Step 2. Optimize C8 to make motor output working frequency in 20~40KHz range: EX2:Change C8 from 22nF to 10nF, R3=1KΩ (RSENSE =50mΩ) stays the same, the output current waveform is as follows: Result:The output frequency is in 20~40 KHz range after C8 value is changed. Note 2:After C8 value is optimized for different type motor load, the current limit clamp level is shifted, customers have to follow step 3 to optimize RSENSE value to obtain correct current limit clamp level. Step 3. Optimize RSENSE: Base on step 2 output waveform result, please optimize RSENSE value again to obtain correct current limit clamp level ILIMITED. EX3:Fix R3, C8 value, optimize RSENSE from 50mΩ to 60mΩ, the output current waveform is as follows: 3.8A 3.6A F=22.7 KHz F=11.4 KHz Test Condition: VCC=6V, STBYA=STBYB=PWMA=DC 3V, PWMB=DC 0V, R3=1K、C8=10nF、 RLIMIT=50mΩ Test Condition: VCC=6V, STBYA=STBYB=PWMA=DC 3V, PWMB=DC 0V, R3=1KΩ、 C8=22nF、RLIMIT=50mΩ

semiconductors Nov. 2020 V0.6 - 9 - The final setting value are RSENSE =60mΩ、R3=1KΩ、C8=10nF, the Current Limit = 3.0A which meets customer application current limit level. Note1: When using the same R SENSE and R3 and C8, the current limit clamp level might be different because the different type motor (inductive reactance and resistance might be different) and different V CC value. To get the best current limit clamp level, it needs to test in actual load model when motor type and VCC setting is changed, Note 2:If current limit function is not needed, the CS pins should be connected directly to ground. 7) Over-temperature protection: If the IC junction temperature exceeds 150 ℃ (Typ.), the internal over- temperature protection function will be triggered, partial FETs in the H -bridge are disabled, that will ensure the safety of customers' products. If the IC junction temperature falls to 110℃(Typ.), the IC resumes automatically. 3.0A Test Condition: VCC=6V, STBYA=STBYB=PWMA=DC 3V, PWMB=DC 0V, R3=1KΩ、 C8=10nF、RLIMIT=60mΩ

semiconductors Nov. 2020 V0.6 - 10 -  Timing Requirement Timing parameter Parameter Typical value Unit Condition Output rising time Tr 20 ns TA = 25℃ , VCC =PVCC=10 V , FPWM_X=10 kHz ,Rload=20 Ω Output falling time Tf 20 ns Output rising delay time Trd 600 ns Output falling delay time Tfd 100 ns 1) Tr : Output rising time, output voltage rising from 10% to 90%. 2) Tf : Output falling time, output voltage falling from 90% to 10%.. 3) Trd : Delay time, PWMX low to OUTX high. 4) Tfd : Delay, time, PWMX high to OUTX Low. Trd TfdPWMX STBYX OUTX Tr Tf Hiz

semiconductors Nov. 2020 V0.6 - 11 -  Truth Table The PWMX and STBYX pins control the state (high or low) of the OUTX outputs. Table1. Shows the logic: STBYX PWMX OUTX

0 X Hi-Z

Table1. Logic States Note: Z:High impedance

semiconductors Nov. 2020 V0.6 - 12 -  Thermal Information θja junction-to-ambient thermal resistance 41.5℃/W Ψjt junction-to-top characterization parameter 0.6℃/W  Θja is obtained in a simulation on a JEDEC-standard 2s2p board as specified inJESD-51.  The Θja number listed above gives an estimate of how much temperature rise is expected if the device was mounted on a standard JEDEC board.  When mounted on the actual PCB, the Θja value of JEDEC board is totally different than the Θja value of actual PCB.  Ψjt is extracted from the simulation data to obtain Θja using a procedure described in JESD-51, which estimates the junction temperature of a device in an actual PCB.  The thermal characterization parameter, Ψjt, is proportional to the temperature difference between the top of the package and the junction temperature. Hence, it is useful value for an engineer verifying device temperature in an actual PCB environment as described in JEDEC JESD-51-12.  When Greek letters are not available, Ψjt is written Psi-jt.  Definition: Tj Tt PTT dtjjt /)( −=ψDFEINITION : Where : Ψjt (Psi-jt) = Junction-to-Top(of the package) °C/W Tj= Die Junction Temp. °C Tt = Top of package Temp at center. °C Pd = Power dissipation. Watts  Practically, most of the device heat goes into the PCB, there is a very low heat flow through top of the package, So the temperature difference between Tj and Tt shall be small, that is any error caused by PCB variation is small.  This constant represents that Ψjt is completely PCB independent and could be used to predict the Tj in the environment of the actual PCB if Tt is measured properly.

semiconductors Nov. 2020 V0.6 - 13 -  How to predict Tj in the environment of the actual PCB Step 1 : Used the simulated Ψjt value listed above. Step 2 : Measure Tt value by using  Thermocouple Method We recommend use of a small ~40 gauge(3.15mil diameter) thermocouple. The bead and thermocouples wires should touch the top of the package and be covered with a minimal amount of thermally conductive epoxy. The wires should be heat-insulated to prevent cooling of the bead due to heat loss into wires. This is important towards preventing “too cool” Tt measurements, which would lead to the calculated Tj also being too cool.  IR Spot Method An IR Spot method should be utilized only when using a tool with a small enough spot area to acquire the true top center “hot spot”. Many so-called “small spot size” tools still have a measurement area of 0~100+mils at “zero” distance of the tool from the surface. This spot area is too big for many smaller packages and likely would result in cooler readings than the small thermocouple method. Consequently, to match between spot area and package surface size is important while measuring Tt with IR sport method. Step 3 : calculating power dissipation by IccVCCIVVVCCP outLoHi ×+×−−≅ )( _0_0 Step 4 : Estimate Tj value by TtPTj +×=Ψjt Step 5: Calculated Θja value of actual PCB by the known Tj ( ) P/Θja(actual) TaTj −= Maximum Power Dissipation (de-rating curve) under JEDEC PCB & actual PCB

semiconductors Nov. 2020 V0.6 - 14 -  Power dissipation curve: Actual PCB Based on 30x30 mm2 FR4 PCB (1 oz.) at double side PCB

semiconductors Nov. 2020 V0.6 - 15 -  Package outline--- QFN 5x5 Unit :mm

semiconductors Nov. 2020 V0.6 - 16 - SYMBOL MILLIMETERS INCHES A2 0.20 REF 0.008 REF e 0.50 BSC 0.020 BSC e1 0.425 BSC 0.017 BSC e2 0.075 BSC 0.003 BSC e3 1.175 BSC 0.046 BSC e4 0.45 BSC 0.018 BSC e5 1.35 BSC 0.053 BSC e6 0.3055 BSC 0.012 BSC e7 0.40 BSC 0.016 BSC e8 1.363 BSC 0.054 BSC e9 0.595 BSC 0.023 BSC e10 0.625 BSC 0.025 BSC e11 1.7225 BSC 0.068 BSC e12 0.458 BSC 0.018 BSC e13 0.117 BSC 0.005 BSC K 0.25 BSC 0.010 BSC K1 0.35 BSC 0.014 BSC K2 0.30 BSC 0.012 BSC K3 0.356 BSC 0.014 BSC K4 0.344 BSC 0.014 BSC K5 0.357 BSC 0.014 BSC

semiconductors Nov. 2020 V0.6 - 17 -  Marking Identification Package Type:QFN 5X5 Device:AM2789 NOTE: Row1 :Logo Row2 :Device Name Row3 :Row3 :Wafer Lot No use five codes、Assembly Year use one code、Assembly Week use two codes Assembly Week use two codes Assembly Year use one code Wafer Lot No use five codes Example:Wafer lot no is FG268 + Year 2019 is J + Week 49 is 49,we type 〝FG268J49〞 The last code of assembly year, explanation as below:: (Year: A=0,B=1,C=2,D=3,E=4,F=5,G=6,H=7,I=8,J=9. For example: year 2019=J ) Notice : The information in this document is subject to change without notice. Please contact AMtek for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating AMtek products into any application. AMtek will not assume any legal responsibility for any said applications.