AM1217S

AM1217S AMTEK | Alldatasheet

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semiconductors Sep. 2014 V1.0 - 1 - Three Channels Power Driver AM1217S The AM1217S is a three-channel driver for DC motor s and it integrates the Motor and Logic supply Pins. The AM1217S provides a high integrated motor-driver solution for Helicopters. The output driver block consists of two open-drain N-MOS; one H-bridge to drive motor winding. The AM1217S operates on a device power -supply voltage from 3.0 V to 6.5 V . CH_A can supply up to 0.8A of output continuous current and 2.0 A of output maximum current ; CH_B and CH_C can supply up to 3.0A of output continuous current and 4.0 A of output maximum current. The AM1217S has internal shutdown function for Over-temperature protection (TSDp = 150 ﾟ C ) , Over-temperature protection recover (TSDr = 125 ﾟC ) , Power reverse-connect protection to prevent the IC damage in any wrong using ,the CH_B/CH_C have the shutdown function for Over-current protection(IOCP = 4.5 A)。 Its package material is Pb -Free and Halogen-Free (Green) for the purpose of environmental protection and for the sustainable development of the Earth.  Applications RC Helicopter  Features 1) Surface mount package (SOP-16) 2) Lower supply current 3) Lower VCC standby current 4) Lower MOSFETs On-resistance 5) Over-temperature protection 6) Over-temperature protection recover 7) Over-current protection (CH_B&C)  Ordering Information Orderable Part Number Package Marking AM1217S SOP-16 AM1217S

semiconductors Sep. 2014 V1.0 - 2 -  Absolute Maximum Ratings (TA=25℃) Parameter Symbol Limits Unit Supply voltage VCC 7.0 V CH_A Output continuous current Iocont 0.8 A CH_A Output maximum current Iomax 2.0 A CH_B/C Output continuous current Iocont 3.0 A CH_B/C Output maximum current Iomax 4.0 A Operate temperature range Topr -40～+125 ℃ Storage temperature range Tstg -40～+150 ℃  Recommended operating conditions (TA =25℃) (Set the power supply voltage taking allowable dissipation into considering) Parameter Symbol Min Typ Max Unit Operating supply voltage range VCC 3.0 6.5 V Input signal voltage VIN -0.3 Vcc+0.3 V CH_A output current IOUT 0 0.8 A CH_B/C output current IOUT 0 3.0 A Externally applied PWM frequency fPWM 0.02 65 KHz

semiconductors Sep. 2014 V1.0 - 3 -  Electrical Characteristics ( Unless otherwise specified, Ta = 25℃,VCC=5V) Parameter Symbol Limit Unit Conditions Min Typ Max Supply current ICC 25 uA Input signal IN_AX=H, IN_/B/C= L, No load on OUT_A/B/C Standby current ISTB 5 10 uA Input signal IN_AX/B/C=L, No load on OUT_A/B/C PWM input Input H level voltage VPWMH 2.5 VCC V Input L level voltage VPWML 0 0.7 V Input H level current IPWMH 30 μA VCC = 5 V , VIN = 3 V Input frequency FPWM 0.02 65 KHz Input pulldown resistance RIPD 100 KΩ Output On-resistance of CH_A Rds(on) 0.72 Ω ILoad= 200mA Upper and Lower total On-resistance of CH_B Rds(on) 0.12 Ω ILoad = 600mA, Lower total On-resistance of CH_C Rds(on) 0.12 Ω ILoad = 600mA, Lower total Output Protection Thermal shutdown protection TSDp 150 ℃ Thermal shutdown release TSDr 125 ℃

semiconductors Sep. 2014 V1.0 - 4 -  Block Diagram Level Shifter Level Shifter High-side / Low-side Driver MG3 MG4 MG6 OUT_C IN_A1 IN_A2 OUT_A2 OUT_A1 GND MG5 Level Shifter Pre-driver MG2 IN_B MG1 Level Shifter Pre-driver MG1 IN_C VCC OUT_B MG2 OCP TSD MG5MG3 MG4 MG6 1 98

semiconductors Sep. 2014 V1.0 - 5 -  Pin configuration TOP VIEW 1 16 OUT_A1 IN_C OUT_C IN_A2 GND NC GND GND NC IN_B OUT_A2 VCC NC OUT_B NC IN_A1 AM1217S  Pin Description PIN No Pin Name I/O Description

1 GND - Ground

2 OUT_A2 O Output negative terminal of CH_A

3 IN_A2 I Input reverse signal for CH_A

4 IN_B I Input of CH_B

5 NC - No connector

6 OUT_B O Output negative terminal of CH_B

7 NC - No connector

8 GND - Ground

9 GND - Ground

10 NC - No connector

11 OUT_C O Output positive terminal of CH_C

12 VCC - Power input

13 IN_C I Input of CH_C

14 IN_A1 I Input forward signal for CH_A

15 OUT_A1 O Output positive terminal of CH_A

16 NC - No connector

semiconductors Sep. 2014 V1.0 - 6 -  Application M 0.1μF IN_A1IN_A2 IN_B IN_C 1 16 OUT_A1 IN_C OUT_C IN_A2 GND NC GND GND NC IN_B OUT_A2 VCC NC OUT_B NC IN_A1 AM1217S M 1μF M 1μF Power Supply 10μF0.1μF C2 C1  Circuit Descriptions The functional description of capacitors on the application circuits: I. C1, C2: VCC input capacitor: 1) The capacitor can reduce the power spike from the motor, to avoid the IC being directly damaged by the peak voltage. It also can stabilize the Vcc voltage and decay its ripples. 2) The capacitor can offer motor the compensated power in motor start running. 3) The capacitor value depends on the value of the VCC and motor loading. In general, a 10μF capacitor is enough in low voltage power (VCC). If the large voltage power or a heavy loading motor is used, a larger capacitor should be chosen. 4) On the PCB configuration, the C1&C2 must be mounted as close as possible to VCC (PIN12). II. C3, C4, C5: The across-motor capacitor: 1) The C3 capacitors can reduce the power spike of motor in start running. A 0.1μF capacitor is recommended. 2) The C4&C5 capacitors can reduce the power spike of motor in start running. A 1μF capacitor is recommended

semiconductors Sep. 2014 V1.0 - 7 -  Input Logic Description Function truth table of CH_A IN_A1 IN_A2 OUT_A1 OUT_A2 Mode L L L L Stop/ Brake L H L H Reverse H L H L Forward H H L L Stop Function truth table of CH_B/CH_C IN_B/IN_C OUT_B/OUT_C Mode L H Open H L Active ※Low standby current function when IN_A1 = IN_A2 = IN_B = IN_C = Low level

semiconductors Sep. 2014 V1.0 - 8 -  Operating Mode Descriptions 1) H-Bridge basic operation mode a) Forward mode Definition：When IN_A1=H，IN_ A2=L，then OUT_A1=H，OUT_A2=L b) Reverse mode Definition：When IN_A1=L，IN_ A2=H，then OUT_A1=L，OUT_ A2=H c) Stop/Break mode Definition：When IN_A1=IN_ A2=L or H，then OUT_A1=OUT_ A2=L (1) Forward mode (2) Reverse mode (3) Stop/Break mode 2) CH_B/C basic operation mode a) Stop mode Definition : When IN_B/C = L，then OUT_B/C = H b) Start mode Definition : When IN_B/C = H，then OUT_B/C = L (1)Stop mode (2) Start mode  Protection Descriptions 1) Over-temperature protection If the IC junction temperature exceeds 150 ﾟ C (Typ), the internal over-temperature protection circuits will be triggered and all the FETs in H-bridge are disabled to ensure the safety of customers' products. If it falls to 125 ﾟC(Typ), the IC resumes automatically. 2) Over-current protection (OCP) While the CH_B/C passes through a large current, 4.5A (Typ), the internal OCP circuits will be triggered and entry a protection mode of auto-recover to avoid damage in IC and EE system of device. ON ON ON ON ON ON QBO F F V c c M QBON V c c M

semiconductors Sep. 2014 V1.0 - 9 -  Thermal Information θja junction-to-ambient thermal resistance 87.41℃/W Ψjt junction-to-top characterization parameter 4.15℃/W  Θja is obtained in a simulation on a JEDEC-standard 1s0p board as specified inJESD-51.  The Θja number listed above gives an estimate of how much temperature rise is expected if the device was mounted on a standard JEDEC board.  When mounted on the actual PCB, the Θja value of JEDEC board is totally different than the Θja value of actual PCB.  Ψjt is extracted from the simulation data to obtain Θja using a procedure described in JESD-51, which estimates the junction temperature of a device in an actual PCB.  The thermal characterization parameter,Ψjt, is proportional to the temperature difference between the top of the package and the junction temperature. Hence, it is useful value for an engineer verifying device temperature in an actual PCB environment as described in JEDEC JESD-51-12.  When Greek letters are not available,Ψjt is written Psi-jt.  Definition: Tj Tt PTT dtjjt /)( DEFINITIONS : Where : Ψjt (Psi-jt) = Junction-to-Top(of the package) C/W Tj= Die Junction Temp. C Tt= Top of package Temp at center. C Pd= Power dissipation. Watts

semiconductors Sep. 2014 V1.0 - 10 -  Practically, most of the device heat goes into the PCB, there is a very low heat flow through top of the package, So the temperature difference between Tj and Tt shall be small, that is any error caused by PCB variation is small.  This constant represents that Ψjt is completely PCB independent and could be used to predict the Tj in the environment of the actual PCB if Tt is measured properly.  How to predict Tj in the environment of the actual PCB Step 1 : Used the simulated Ψjt value listed above. Step 2 : Measure Tt value by using  Thermocouple Method We recommend use of a small ~40 gauge(3.15mil diameter) thermocouple. The bead and thermocouples wires should touch the top of the package and be covered with a minimal amount of thermally conductive epoxy. The wires should be heat-insulated to prevent cooling of the bead due to heat loss into wires. This is important towards preventing “too cool” Tt measurements, which would lead to the calculated Tj also being too cool.  IR Spot Method An IR Spot method should be utilized only when using a tool with a small enough spot area to acquire the true top center “hot spot”. Many so-called “small spot size” tools still have a measurement area of 0~100+mils at “zero” distance of the tool from the surface. This spot area is too big for many smaller packages and likely would result in cooler readings than the small thermocouple method. Consequently, to match between spot area and package surface size is important while measuring Tt with IR sport method. Step 3 : calculating power dissipation by P  (VCC–|Vo_Hi – Vo_Lo|) x Iout + VCC x Icc Step 4 : Estimate Tj value by Tj= Ψjt x P+Tt Step 5: Calculated Θja value of actual PCB by the known Tj Θja(actual) = (Tj-Ta)/P

semiconductors Sep. 2014 V1.0 - 11 -  Maximum Power Dissipation (de-rating curve) under JEDEC PCB & actual PCB

semiconductors Sep. 2014 V1.0 - 12 -  Packaging outline --- SOP16 Unit: mm SYMBOL MILLIMETERS INCHES Min. Max. Min. Max. A -- 1.75 -- 0.069 A1 0.05 0.225 0.002 0.009 A2 1.30 1.50 0.051 0.059 A3 0.60 0.70 0.024 0.028 b 0.39 0.48 0.015 0.019 c 0.21 0.26 0.008 0.010 D 9.70 10.10 0.382 0.398 E 5.80 6.20 0.228 0.244 E1 3.70 4.10 0.146 0.161 e 1.27 TYP. 0.05 TYP. h 0.25 0.50 0.010 0.020 L 0.50 0.80 0.020 0.031 L1 1.05 TYP 0.041 TYP.

semiconductors Sep. 2014 V1.0 - 13 -  Marking Identification NOTE: Row1 ： Logo Row2 ： Device Row3 ： Wafer Lot No、Assembly Year、Assembly Date Code Example : Wafer Lot No is CH + last number of assembly year is 2 (C=2) + produce at the week 51 Then mark〝88888C51〞 Assembly Year Code： ( Year_A=0,B=1,C=2,D=3,E=4,F=5,G=6,H=7,I=8,J=9, e.g. : 2012=C )