AM2130-55JC

AM2140 AMD | Alldatasheet

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1024x8 Dual-Port Static Random-Access Memories DISTINCTIVE CHARACTERISTICS © True dual port operation © Automatic power-down feature © Access time as fast as 55 ns © All inputs and outputs are TTL-compatible ® Master device (Am2130) has on-chip arbitration © 48:pin DIP or 52-pin PLES © Expandable data bus width in multiples of 8 bits using @ Single +5-volt power supply one master (Am2130) and required number of siave @ Advanced N-MOS technology devices (Am2140) GENERAL DESCRIPTION The Am2130 and the Am2140 are members of the 1K x8 interrupt generators. If any data is written at the address dual-port static RAM family. The Am2130 is designated as (3FF)y from the left port, an interrupt signal becomes active tha master and the Am2140 as the slave device. The for the right port. The interrupt signal is deactivated by master provides the necessary control signal to the slave reading from the right port at the same address, The devices to facilitate implementing a wider data bus in a _ address (3FE)y is used in a similar fashion by the right port ‘system, The master/slave concept allows expansion with to activate the interrupt signal for the left port. minimal external logic. Both devices have two independent ports called Left and The Am2130/Am2140 also have two chip enable signals Right port. Each port consists of an €-bit bidirectional data COrTesponding to the left and right ports. Before any bus and a 10-bit address input bus and necessary control. ‘transaction on a port takes place, the corresponding chip signals, ‘enable input must be activated. If a chip enable signal is not active, the circuitry corresponding to its side automatically ‘The Am2130 has an on-board arbiter to resolve contention —_ powers down and enters standby mode. between the left and right ports. When contention between ports ee ee is given priority while the other port — The am2130/Am2140 are packaged in 48-pin DIPs or 52- receives a Dusy indication. pin plastic leaded chip carrier. All inputs and outputs are The Am2130 also contains on-chip facilities for supporting TTL-compatible and the devices operate from a single +5- semaphores. Addresses (SFE) and (3FF)y serve as volt power supply. BLOCK DIAGRAM 1 — were wa % me TD iat Cy Pa a ED Sate a= ca ce + oe ml U}) io a KaK | Bex om ea “Tet = eir: eee | | cern mm Es ows ms ™ = el oe = nie ‘80005005 Notes: 1. Am2130 (Master): BUSY is open-drain output and requires pull-up resistor. Am2140 (Slave): BUSY is an input. | rd

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vox G23 2 fS von rhebehtel 7 Vue G24 = SSSSSFISESSES coo0sers ccDo0ee00 Note: Pin 1 is marked for orientation EE te i rent LOGIC SYMBOL A, CT a YOq-VOn KO > 10 , D> hae. WO tm -/Orm Kr > to ZL} Aon an le A CE. BUSY, INT, BUSY, iNT, Lsoozese Voo = +5:V Power Supply Vss = Ground OO

ORDERING INFORMATION

AMD products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a, Device Number b. Speed Option (if applicable) c. Package Type d. Temperature Range e. Optional Processing AM2130 <0 2 & Bs Leon nocssma

4 TEMPERATURE RANGE

a. DEVICE NUMBER/DESCRIFTION Valid Combinations Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult MSIS sales department to confirm availability of ‘AM2130-10 specific valid combinations, and to obtain additional data on. MSIS's ‘AM2130-12 PC, PCB, DO, standard military grade products. es

MILITARY ORDERING INFORMATION APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) ¢. Device Class. d. Package Type e. Lead Finish amar = iB x | [ ©. LEAD FINISH C= Gols X= 48.in Sidebrazed Ceramic DIP (80 048) ‘¢. DEVICE CLASS 73~ Class B b. SPEED OPTION “7070 ns, =10= 100 ns Tha 120 ne &. DEVICE NUMBER/DESCRIPTION “Am2130/Am2140 1Kx8 DuakPor Static RAM Valid Combinations . Valid Combinations list configurations planned to be supported in volume Valid Combinations for this device. Consult MSIS sales department to confirm availability of AM2190-70 specifi valid combinations, and to obtain additional data on MSIS's ‘AM2i90-10 | standard military grade products. A AMZ130-12 exc - Group A Tests AN2140-10. Group A Tests consist of subgroups 1, 2, 3, 7, 8, 9, 10, 11. AMO140-12 mene vowinine ry vo | a

a PIN DESCRIPTION Am2130 Aoi-Agi Left Port Address (Inputs) TE_ Right Port Chip Enable (Input) These 10 inputs constitute the memory address for the left Operation of this input is identical to GEL except that the port. Ag is the least significant bit position and Ag is the GER input contiols the right port. mast significant postion. A HIGH level on any of these GND (Vg) Ground puts represents a logic 1 at that position and LOW reprosents a logic 0. The sequence of events and related /OoL-/O7, Left Port Input/Output Bus timing for the address inputs during read and write (Input/Output; Three State) operations will be discussed in later sections of this data These eight lines constitute the data bus for the left port. fa sheet. read operation is pertormed using the left port, data from the z . location addressed by the left port address will be available 1 a write operation is performed using (3FF)}, an interupt ‘on these lines. Similarly, to perform a write operation using signal is activated for the right port (see INTR pin the left port, data to be written into the memory must be description) presented on these lines. Tho drivers on the chip to drive If a read operation is performed using (3FE)y, the INTL ‘these lines are enabled only when the CE, is LOW, OE, is signal will be deactivated (see INT, description). LOW and R/W, is HIGH. ‘Agr- Aga Right Port Address (Inputs) 1/OgR-VO7R Right Port Input/Output Bus “These 10 inputs constitute the memory address for the right (Input/Output; Three State) port. Ag is the least significant bit position and Ag is the ‘These eight lines constitute the data bus for the right port. If ‘most significant position. A HIGH level on any of these read operation is performed using the right port, data from inputs represents a logic 1 at that position and LOW the location addressed by the right port address will be represents a logic 0. The sequence of events and related available on these lines. Similarly, to perform a write timing for the address inputs during read and write ‘operation using the right port, data to be written into the operations will be discussed in later sections of this data memory must be presented on these lines. The drivers on sheet. the chip to drive these lines are enabled only when the CER, If a write operation is performed using (3FE)}, an interrupt is LOW, OER is LOW and R/Wa is HIGH. signal is activated for the left port (see INT, pin description). TNT. Left Port Interrupt Flag (Output; Open Drain) It a read operation is performed using (FF), the INTR This open-drain output requires a pul-up resistor for proper signal wil be deactivated (see INTq description). operation, If the right port pertorms any write operation using address (3FE)}, then this output goes LOW. It will BUSY, Leff Port Busy Flag (Output; Open Drain) remain LOW until the left port successfully completes any This open-drain output requires a pull-up resistor for proper read operation using the address (3FE)H. It should be noted operation. A LOW on this output indicates that the on-chip that powering down the ports has no effect on this output. arbitration logic detected a contention between the left and right ports and the rght port is given priority. All lft por NTR Right Port Interrupt Flag (Output; Open Drain) signals must be held stable until a HIGH on this output is This open-drain output requires a pull-up resistor for proper indicated. operation, ifthe left port performs any write operation using address (3FF)}, thon this output goes LOW. It will remain The BUSY, signal generation is a logical function of the left LOW until the right port successfully completes any read and right port address inputs and the GEL and CER inputs. ‘operation using the address (3FF)y. It should be noted that ‘The transient behavior of the BUSY, output is not assured powering down the ports has no effect on this output. while the inputs are changing = DEL Output Enable Left 170 Port (Input) BUSY, Right Port Busy Flag (Output; Open Drain) ‘When this input is HIGH, the left port 1/O bus lines are in This open-drain output requires a pull-up resistor for proper high impedance stato. if this input is LOW and CE, is LOW operation. A LOW on this output indicates that the on-chip and RVW, is HIGH, the left port drivers are enabled and arbitration logic detected a contention between the left and Gata from the location addressed by the Ag. — AgL inputs right ports and the left port is given priority. All right port wil be available on the I/O bus lines of the loft port. It may signals must be held stable until a HIGH on this output is Be of terest ono tha the Oe input has no effect on the indicated. BUSY, or BUSY, or INT, or INTR signals. Even though the ‘The BUSYa signal generation is a logical function of the left left port I/O port drivers are disabled when the F/W input ‘and right port address inputs and the CE, and CER inputs. goes LOW (write operation), it is recommended that the OE, The transient behavior of the BUSYp output is not assured signal be kept HIGH during write operations to the left port. while the inputs are changing. OER Output Enable Right 170 Port (input) CEL Lett Port Chip Enabie (Input) ‘When this input is HIGH, the right port I/O bus fines are in This input must be LOW before any transaction from the left bigh impedance state this put LOW and TER is LOW port and remain LOW for the duration of the transaction. and A/Wp is HIGH, the right port drivers are enabled and When this input goes HIGH, left port logic circuits enter data from the location addressed by the Agr ~ Agr inputs will standby power mode and remain in this mode as long as be avaiable onthe 1/0 bus nes of he ight pot. it maybe ot this input remains HIGH. It should be noted that powering interest to note that the OER input has no effect on the down the left port to standby mode does not affect the INTL BUSY, or BUSYR or INT, or INTR signals. Even though the or INTR outputs. This input going HIGH also initializes the left port I/O port drivers are disabled when the R/Wr input internal arbitration latch. It is recommended that CE, go goes LOW (write operation), it is recommended that the OER \\ HIGH after completing a transaction (see discussion on signal be kept HIGH during write operations to the right port. | arbitration). ee

| F/W. Left Port Read/Write Enable (input) This input is used to specity the right port function to be This input is used to spocity the left port function to be Performed. HIGH indicates a read and LOW indicates a Performed. HIGH indicates a read and LOW indicates. a wnte function wo fenetion When the CER is LOW and the OER is LOW and the R/W er is LOW a i a When the TEL is LOW and the OE, is LOW and the RV is is HIGH, data tom tne eeaton eainaeses by the Aga Aon aoe Sraube on eee Von wee We filles will be available on the 1/Ooa ~1/O7R lines. AS mmentioned i i . eearier, reading from the right port at the location (3F earlier, reading trom the lett port at the location (FE) disables the INT outpat FP disables the INT, output, _ When the TEL is LOW and the R/Wi goes LOW, data Meee ne, GER iS, LOW and the RYWn goes LOW, data Presont on the /Og, - 1/07. lines wil be written into the cath ian AOoR - VOrR lines wil be writen into the meee ann mo,“ pu aoe ‘eaon adorn ty Fae“ ph shea be noted that the write operation is not affected by the OE, input However te eee et aoc OE, read input. However, itis recommended that the OE, input bs hed HIS gen fecommended tha A in held HIGH during a wrte operation. menserbe, eae hela HIGH during a write operation. As montioned earlier: performing a write operation from the left port at the address Beene 2 writ operation from the let port at the address (GFF causes tho INT out to oo een GFE} causes the TNT, output to go LOW. It should be noted that even though R/W, is LOW, writing is |t should be noted that even though R/Wrp is LOW, writing is internally inhibited if the right port is given priority by the intemally inhibited if the left port is given priority by the arbiter. Discussion on arbitration can be found in a later arbiter. Discussion on arbitration can be found in a later section section R/Wr Right Port Read/Write Enable (Input) Voc +5-Volt Power Supply cc Am2140 TNO. alg functionally very similar to the Am2190. The BUSY RIGKY Part Busy Flag (Output; Open Drain) Am2140 differs trom the Am2130 in two signals only If this input is LOW, a write enable signal to the nght side of BUSY, and BUSY. In the case of the Am2140 they are used the memory array is internally disabled. In expanded as inputs and play a signiticant role in expanding the word systems where an Am2130 is used as the master, this input width, is connected to the BUSYg output of the Am2130. BUSY, Leff Bort Busy Flag (Input) If this input is LOW, a write enable signal to the left side of the memory array is internally disabled. In expanced systems where an Am2130 is used as the master, this input 'S connected to the BUSY, output of the Am2130. | 4 | mi 4077984 000008? 805 om Am2130/Am2140 4-95 ee

FUNCTIONAL DESCRIPTION Figure 1 is a conceptual logic diagram of contention arbitration {ogic. it consists of two equality comparators. The left compar- ‘As shown in the block diagram, the Am21G0/AM2140 isa true ator compares the left port address inputs to the delayed Tk. dual port RAM. It consists of a memory array with two version of the right port address. Similarly, the ight compara, exe nddoes decoders and associated logic. This arrange- tor compares the rightport address to the delayed version of se ot ows the accessing of every word in the memory array he left port address. The output of the comparators: is ‘Tom aro independant sources. We cal these sources lett sid° connected to a latch formed by two cross-coupled NANO and right side for convenience. Data accessed by the left-side gates as shown in Figure 1. The chip enable signals, CE, and sadrete inputs appears onthe leftside data ines of the array GE, aro also inputs to ths latch as shown. The BUSY and sega connected 10 tho left-side W/O pins through the BUSY outputs are generated by gating the latch output with Sesociated three-state butters. The enable contol signal for the proper chip enable signal a8 shown. Also note that the these butlers is generated using the R/Wi, CE, and OE. latch outputs are used internally for left and right write inhibit irocte. tthe /O buifers are disabled on the chip, the 1/0 pins signals. For example, if the right side write inhibit signal in Can bo used 2s inputs. Data to be written from the lett port 8 Figure 1 is LOW, writing into the memory does not occur even frosented on these inputs. Writing into the memory aay ffom if the /Wa input of the Am2130 is LOW: the left side is controlled by the leit write enable signal generated on the chip using the R/W and CEL inputs. An ‘The operation of the arbitration circuit can now be explained. Slontical arrangement exists forthe right side also. In addition, Assume that the left port addross had been stable and CE. is eer each arbitration log to give priory to one port over LOW. Both Q and Q' outputs of the latch wil be HIGH Terence in ease ofa contention, and interrupt flag loge. because the output of both comparators is LOW (eoataniee are different). So the BUSY output on both sides is HIGH. Now Contention Arbitration Qasume that the right address changes and becomes equal to ‘Two independent access facies are provided in a dual-port the left address, The rant acivons comparator output goes memory t0 eliminate physical interference between signals, HIGH and the @ output of ne latch goes LOW. Eventually the Towever there are two significant possibiiies of "ogicat" output of the left comparator also apes HIGH, but because of woo wtaronce which are not tolerable: when one port is reading the cross coupling of the "into the gate ‘generating the Q from a location while the other port is writing into the same ‘output, Q output remains HIGH. As soon as the CER input location at the same time, In this case, data received by the goes LOW, BUSYp becomes LOW. Thus, the arbitrator gave (Ceting port may not be predictable. Similarly, consider the _priaity to the left port by inaicaiag 9 Busy signal to the right reach Parnen both pots. write Information into the same port. Thus in this example, the left por the winner and the cae simultanoously, The resutant data that finally ends up right ports the loser in the contention fr he Memory Sooner one momory location may not be valid. These two situations of later the left port wil rishi ansaeton ‘at the contended iF eammonty called contention. The Am2130 has on-chip location and change the addrass, or 1s chip enable will go Togic to detect contention and give priority to one port over the HIGH. Thus when tne contentor © Ot, the Q output of the eer ina true dual-port RAM, simultaneous reading from both _latch will Become HIGH and ‘BUSY a will go HIGH. A similar ports atthe same address does not corrupt the data. Hence, it reasoning can be used lo understand the operation of the left aor onstrued that no contention occurs, However, for the side. It should be clear then. in cases of contention, the arbiter cae of cimplicty and compatibilty with the industry standard __willdecide one port as the winney and he ang port must walt practices, the Am2190 arbitration is based purely on ad- for the winner to complete the see of the memory. The winning cracuce, Hence, in the case of a simultaneous read from both port must indicate to the arbiter tel has completed its ports at the same address, the arbitration logic will sense operation ener by changing the address or making its chip comtention and ave priotty o one of the ports. The other port enable input HIGH. Without such an indication, the arbiter will will receive a busy indication. not remove the busy indication to the losing port. roche LF #4 ponton {} | ‘0 COMPARATOR o oF Lertwne RIGHT RTE BT eee 180007422 1 4-96 Am2130/Am2140 | ms 8077984 oooo0ss 745 me

Read/Write Operations ‘example in Figure 2, Aro is the most significant address bit. Performing read/write operations when there is no contention _ When this signal is LOW and CE input is LOW, the chip enable input of the upper Am2130 goes LOW. Thus, the first 1K is relatively straightforward. The sequence of events for a read elected for beroeoYone. On the other hand. i is listed below, The timing relationships between various __Ocallons are selected for transactions, On the other hand, signals can be found in later sections of this data sheet. ‘Aigis HIGH and GE ts LOW, the chip enable input ofthe lower Am2130 goes LOW selecting the second 1K locations. As 1. Establish HIGH on the R/W and LOW on the CE input of dopicted in the figure, the address inputs of both Am2130 the desired port. devices are bussed together. Similarly, the 1/0 signals are also bussed to create the overall data bus. Also note that the 2 Establish the dested address on the desired port address Ging control signals are connected between the two devices. In this example, we have not used the interrupt outputs. 3. Make the OE input of the desired port LOW. However, it should be noted that depth expansion using 4, The I/O lines of the selected port will contain the data after. —smultiple devices does not change the operation of the the access time has elapsed interrupt outputs. The interrupt output of each device behaves as described before. Hence, the user must decide which 5. Maka the oot enable and chp enable meus HGH to Peet cuput hom hh doves be uae hi ye Performing write operations when there is no contention ig Width Expansion equally straightforward. The sequence of events for a write is The intrinsic width of the data word of the Am2130 is eight listed below. The timing relationships between various signals bits. However, it is possible to realize wider data words ‘can be found in ater sections of this data sheet (multiples of 8) by using multiple devices. The instinctive solution of taking the required number of the devices and 1. Establish LOW on the CE input of the desired port. assigning the data bits 10 individual devices is potentially 2, Establish the desired address on the desired port address. —_unreliabie. As we know, the Am2130 has arbitration logic on lines. the chip, and hence is called the master. When several of these masters are present, device-to-device variations and 3. Establish the desved data on the 1/0 lines of the port. CHher factors may cause one device o ae prony one port 4, Make the R/W input of the port LOW and bring it HIGH while. another device gives priority to the other port. In after the specified amount ot time. essence both ports are busy! This is an undesirable situation . and should not be allowed in operation. The most elegant way 5: Make the CE input HIGH to complete the operation. to avoid the situation is to allow only one device to arbitrate When a read or write operation is initiated by a port and the contention, It is recommended that when expanding the contention from the other port occurs, the implications are width of the data words, the Am2130 be used as the master very simple, The losing port will see its BUSY line go LOW. and a number of Am2140s be used as slave devices. The The port must wait until a HIGH is indicated on the BUSY line. Am2140 does not have the arbitration capability; instead it Thus in this case of contention, the operation did not really accepts the BUSY outputs generated by the Am2130 as start when the por initiated it. Instead, the operation actually _inputs. tarod when the BUSY tne went HIGH. See te miNG Fe 31 concopil gram ola 168i system ing one ‘Am2130 and one Am2140. As can be seen, using master/ Interrupts slave devices avoids external logic for expansion. For the sake Each port has an associated output called interupt. The OY completeness of this discussion, & may be noted mat its interrupt outputs are activated and deactivated by the on-chip finer Possine 1 sapand We WANN Using only. logic when read and write operations occur with a particular lowavor, external logic must be provided to prevent every address location. For dxample, it a write operation is per- Gevice of the system from arbitrating. We want only one device to be the arbitrator. As explained in Figure 1, arbitration formed by the lft port with address (3FF)y, an on-chip latch seat eee contrat of the CE input of the set. This latch drives the INT output LOW. The latch is $37, 8 < pe cleared only when a read operation from the right port using the address (3FF)x takes place. Similarly, if a write operation _Figure 4 shows a conceptual diagram of a 16-bit system using from the right port using the address (FE) occurs, a latch is two Am21308, Device 1 in this figure behaves as the master. set to drive the INT, output LOW. The INT, will go HIGH (latch The external logic shown in the figure ensures that the CE is cleared) only after a read operation from the left port using _input of Device 2 is HIGH if the corresponding BUSY output of the address (3FE)y occurs. As mentioned before. powering Device 1 is LOW. Thus the arbitration logic of Device 2 is down a port to standby mode does not affect these outputs. prevented from taking part in resolving contention. Depth Expansion Using Multiple Am2130s Simultaneous Width and Depth Expansion ‘The Am2130 has an intrinsic storage capacity of 1K bytes. By combining the depth and width expansion schemes dis- However, itis simple to expand the storage capacity by using cussed, it is possible to build systems with greater depth multiple devices. Figure 2 is a conceptual diagram of a 2K byte (multiples of 1K) and wider words (multiples of 8). Figure 5 dual port memory system using two Am2130 devices. The shows a conceptual diagram of a 2Kx16 system. The Principle behind such expansion is obvious: all that needs to _operation of this scheme is understood by suitably combining bbe done is to decode the most significant system address to the explanation of Figure 2 and Figure 3 and hence is not generate the individual CE inputs for the Am2130s. For repeated here, Bm 8077984 0000089 b41 me Am2130/Am2140 4-97 a

4 PR ameiso a Wa

Figure 2. Conceptual Depth Expansion Figure 3. Width Expansion with Master/Slave

TABLE 1. NON-CONTENTION READ/WRITE CONTROL TABLE 2. BUSY ARBITRATION OF ADDRESS CONTENTION TABLE 3. INTERRUPT FLAG

1. if LIV violates taps spec then one of the two ports receives priority, and the remaining port's BUSY Flag goes LOW. However,

a, Petter hase oponlen's 6S parted he Algor i also coding.

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ABSOLUTE MAXIMUM RATINGS (Note 15) OPERATING RANGES (Note 8) Ambient Temperature Temperature (TA). ecsseee ..0 to +70°C with Power Applied scien 755 to + 125°C Supply Voltage (Vcc) ... weennees +45 to +5.5 V ‘Supply Voltage with Respect to Ground -05 to +7.0V Military (M) Devices oe ‘ Temperature (Ta) ceeeseeeeenes BE tO #125°C All Signal Voltages a seas 3.5 to +7.0 V Supply Voltage (Voc) +45 to +55 V Operating ranges define those limits between which the Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality functionality of the device is guaranteed. at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating range unless otherwise specified (for APL Products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) Am2130/Am2140 Parameter Parameter some Seseneton Test Conditions [wn | wax. | a lec Powor Supply Current Voo = Max, TE = Vi. pOerees 170 (Both Ports Active) ‘Outputs Open iM | [|__| Devices [Eee | |» | ‘ee ‘Standby Current Voc * Min. to Max., Devices {Both Pons Standby) te, aw Cn Vin re i ee ic | Standby Current TEL Vi. and TER = Vai or P HU Vit and CE = Viv ma [Va [input tow Vortage [sos foe Vin ‘put HIGH Voltage OO TOutpat LOW Vottage Drain Ouiput LOW Vol ig =4 ma vor lemma [eam Te a So CAPACITANCE (Note 9) Parameter Parameter ‘Symbol Description Test Conditions [Sour | os capstnnee Pf ee | a Notes: See notes following Switching Waveforms. BS 3077984 0000093 O0ec Am2130/Am2140 4-101

SWITCHING CHARACTERISTICS over Operating range unless otherwise specified (for APL Products, Group A, Subgroups 7, 8, 9, 10, 11 are tested unless otherwise noted) varameter parameter [-s | = | -0 | Symbol Deserption [in [ax in [on| in [Max | in. 2a Aden Res Te ee 3] hes Chie Ene coer Tne pepe es] [2 nce oat erate aan tine fo | as} a eps Outpt tow 2 Tine CE 7 ee Output igh 2 Time (Notes 5 89)] 0 | Oo fo] [o)|@| «| [Seu Ton ent e PonerUF Fino ~ ee 9 [0 a WRITE CYCLE (Note 10) ber Chip Enable to End of Wie a a ce 2 oaw ‘acess Vall to En of Wrte 50 Le | [eo | 16 | tow Data Valid to End of Write [30 [ [| [| as] [7 [oy oa Hoists [ro [Tey [fs | 18 [wz | Wite Ended © Ouptintign? [Weiss eo| 0 | Sop elele lop et a] [is {ow [ovo aewe tom tra of Wito [wows set of De] fet pet pe] | BUSY FLAG TIMING (Notes 7 & 14)

2 Tad Gyo Te a [=

2) we Wate Cycle Time i [70 [100 | [as | [32 [ow 5087 we wine ns op pp 2 [tain | BUSY Acoss Tie wats [oe ee pp BURY beste Tne wo Asses [now 8) wo} ae fff po | srr meorens [ee { [= «lel fo] e| vfs [Eaeewmrerrmres oe [Pal fel fal fale 3 [ues [asso Pray Sop Fine a (3 [nis TE We ioe See ET [22 [toni |" Outut Erable to hint Reset Fane [ae ao ae] [3 [wn [acess to itrapt Reset Tme |] a [3 [Tens Top Erie to rtrest Reset Tine tpt ee] Teian See ter lou Sais Weems @™ 8077984 0000094 T4S mM pn 402 ‘am2s90/Am2140

125001 150.00 Pour SUSY 8 NT ren on T own rovoee01 rovozeee Test Loads A and B Test Loads C and D —____Test tests Aang@B Test bonds Cand DO TEST OUTPUT LOADS | Test Load CAP A 5 pF (Note 1) B | 100 pF Cc 50 pF 2) 5 pF (Note 1) Notes: 1. Includes Scope and Jig Capacitance. SWITCHING TEST WAVEFORM AC Test Conditions | GND 10 90 V Input Rise and Fall Times 5 ns i Input Timing Reference | Output Reference Levels Test Output Loas SWITCHING WAVEFORMS KEY TO SWITCHING WAVEFORMS TeRtTO BH 8077984 o000095 985 mm Am2130/Am2140 4-103

SWITCHING WAVEFORMS (Cont'd.) READ CYCLE (Either Side) Address Access cs (Notes 1 & 2) oo * i : | CE and OE-Controlled Access (Notes 1 & 3) wm 3077984 OOOO0%b 411 mso77984 oooooN 813 4-104 Am2130/Am2140

SWITCHING WAVEFORMS (Cont'd.) WRITE CYCLE (Either Side — Note 4) “LN\\* LLL EIT TL ——— e- “LTH XAAAN cara cut X X Xx x x _ _ monwreoance Wro00411 OE-Controlied Data Out aA VAY ELLLLTTIT7 - Ok e— Le | wroove21 WE-Controlied Data Out (OE = Vu) mm 8077984 0000097 758 MM Am2130/Am2140 4-105

SWITCHING WAVEFORMS (Cont'd.) BUSY FLAG TIMING (1 of 2) (Note 12) (Chip Enable Arbitration) SX eX ee a. a CL ol I-@— r@- | Te \\ | © i——® wove CER Valid Last | Xe Xe -e- m /—® +-—- © wrove4a4 CEL Valid Last mM 3077984 o000096 694 4-106 Am2130/Am2140

a SWITCHING WAVEFORMS. (Cont'd.) BUSY FLAG TIMING (2 of 2) (Address Arbitration) WW - = AA a | war VYYV re >EXXKX eee >) DS OC TR, & ADDRp Valid Last ae a 0 ¢ wom ADDR, Valid Last ay <7) Feat For Am2140 Only mm 6077964 9000099 S20 a Am2130/Am2140 4-107

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Notes* 1.R/W is HIGH for Read Cycles. 2, Device is continuously enabled, CE = Vi_, OF = Vit. 3. Addresses valid prior to or coincident with CE transition LOW. 4.11 GE and A/W go HIGH simultaneously, the outputs remain in the high-impedance state. 5, Transition is measured at 1.5 V on the input to VOH - 500 mV and VOL + 500 mV on the outputs using the Load shown in Load A. 6.0&, = CEp = Vu. 7. The BUSY and INT outputs are open drain. A pull-up resistor is required for system operation. For measurement purposes, Load C is used for HIGH-to-LOW transitions; output reference level is 1.5 V. Load D is used for LOW-to-HIGK transitions; output reference level is +500 mV from the output LOW voltage level. 8. For test and correlation purposes, ambient temperature is defined as the instant-on case temperature. 9. This parameter is guaranteed by design but is not 100% tested. 10. Except where indicated, 1/0 pins use Load B. 11. For @ given port to Set or Clear an Interrupt Flag, 1) that port must have priority if addresses match and both TE, = TER = LOW; or 2) Addresses do not match. 42. f the last input valid transition, which would ordinarily cause a match, occurs at the same time that the opposite port address or CE changes to a no-match condition, then BUSY will remain HIGH (..., if there is never a match, then BUSY remains HIGH). 13. For Siave Am2140 only. 14. For Master Am2130 only. 16. Absolute Maximum Ratings are intended for user guidelines and are not tested. * Notes listed correspond to reference made in the following sections: - Operating Ranges = DC Characteristics table = Switching Characteristics table ~ Switching Waveforms @ 6077984 Go0010e 945 ee 4-110 Am2130/Am2140