ALC898 REALTEK | Alldatasheet
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7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC WITH CONTENT PROTECTION DATASHEET Rev. 0.60
13 June 2011
Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com ALC898
7.1+2 Channel High Performance HD Audio Codec With Content Protection ii Rev. 0.60 COPYRIGHT ©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC898 ICs. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary 0.10 2010/06/02 Preliminary release. 0.20 2010/09/24 Update chapter 9.1/9.3 0.21 2011/04/06 Update Pin37 0.50 2011/05/12 Update Pin37 and chapter 9.2/9.3/10 0.60 2011/06/13 Update chapter 9.1/9.3/10.1
7.1+2 Channel High Performance HD Audio Codec With Content Protection iii Rev. 0.60 Table of Contents
7.1+2 Channel High Performance HD Audio Codec With Content Protection iv Rev. 0.60 8.28. V ERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR
7.1+2 Channel High Performance HD Audio Codec With Content Protection v Rev. 0.60 8.40. V ERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 & CONTROL 3 & CONTROL 4 (VERB 8.41. V ERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 & CONTROL 3 & CONTROL 4 (VERB 8.43. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8],
Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...32
7.1+2 Channel High Definition Audio Codec with Content Protection 1 Rev. 0.60 1. General Description The ALC898 is a multi-channel High Definition Audio Codec with Realtek proprietary loss-less content protection technology that protects pre-recorded content while still allowing full-rate audio enjoyment from DVD audio, Blu-rayTM DVD, or HD DVD discs. The ALC898 provides ten DAC channels that simultaneously support 7.1 sound playback, plus 2 channels of independent stereo sound output (multiple streaming) through the front panel stereo outputs. Two stereo ADCs and one stereo digital microphone converter are integrated and can support a microphone array with Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technologies. The ALC898 incorporates Realtek proprietary converter technology to achieve 110dB Signal-to-Noise ratio (SNR) playback (DAC) quality and 104dB SNR recording (ADC) quality, and is designed for Windows Vista premium desktop and laptop systems. All analog I/O are input and output capable, and headphone amplifiers are also integrated at eight analog output ports (port-A to port-H). All analog I/Os can be re-tasked according to user’s definitions. Support for 16/20/24-bit S/PDIF input and output with up to 192kHz sample rate offers easy connection of PCs to consumer electronic products such as digital decoders and speakers. The ALC898 features secondary S/PDIF-OUT output and converter that transport digital audio output to a High Definition Media Interface (HDMI) transmitter. The ALC898 supports host audio from the Intel chipsets, and also from any other HDA compatible audio controller. With various software utilities like environment sound emulation, multiple-band and independent software equalizer, dynamic range compressor and expander, optional Dolby® Digital Live, Dolby® PCEE program and DTS® CONNECT™ , the ALC898 provides the highest sound quality, providing an excellent entertainment package and game experience for PC users.
7.1+2 Channel High Definition Audio Codec with Content Protection 2 Rev. 0.60 2. Features 2.1. Hardware Features High performance DACs with 110dB signal-to-noise ratio(A-weighting) High performance ADCs with 104dB signal-to-noise ration (A-weighting). Meets Microsoft WLP3.x (Windows Logo Program) audio requirements Ten DAC channels support 16/20/24-bit PCM format for 7.1 sound playback, plus 2 channels of concurrent independent stereo sound output (multiple streaming) through the front panel output Three stereo ADCs support 16/20/24-bit PCM format, multiple stereo recording All DACs supports 44.1k/48k/88.2k/96k/192kHz sample rate All ADCs supports 44.1k/48k/88.2k/96k/192kHz sample rate Primary 16/20/24-bit S/PDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample rate Secondary 16/20/24-bit S/PDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample rate 16/20/24-bit S/PDIF-IN supports 32k/44.1k/48k/96k/192kHz sample rate All analog jacks (port-A to port-H) are stereo input and output re-tasking Port-A/B/C/D/E/F/G/H built in headphone amplifiers Port-B/C/E/F with software selectable boost gain (+10/+20/+30dB) for analog microphone input High-quality analog differential CD input Supports external PCBEEP input and built-in digital BEEP generator Software selectable 2.5V/3.2V/4.0V VREFOUT Up to four channels of microphone array input are supported for AEC/BF application Two jack detection pins each designed to detect up to 4 jacks plugging Supports analog GPIO2 to be jack detection for CD input which is used as 9th analog port Supports legacy analog mixer architecture Up to 3 GPIOs (General Purpose Input and Output) for customized applications. GPIO0 and GPIO1 share pin with DMIC-CLK/SPDIF-OUT2 and DMIC-DATA. Supports mono and stereo digital microphone interface (pins shared with GPIO0 and GPIO1) Supports anti-pop mode when analog power LDO-IN is on and digital power is off. Built-in analog LDO. Content Protection for Full Rate loss-less DVD Audio, Blu-rayTM DVD and HD-DVD audio content playback (with selected versions of WinDVD/PowerDVD/TMT) Hardware Zero-Detect output volume control 0.75dB per step output volume and input volume control Supports 3.3V digital core power, 1.5V or 3.3V digital I/O power for HD Audio link, and 5.0V analog power Intel low power ECR compliant and power status control for every analog/digital converter and pin widgets. 48-pin LQFP ‘Green’ package
7.1+2 Channel High Definition Audio Codec with Content Protection 3 Rev. 0.60 2.2. Software Features Meets Microsoft WLP 3.x and future WLP audio requirements WaveRT-based audio function driver for Windows Vista and Windows 7 Direct Sound 3D™ compatible I3DL2 compatible 7.1+2 channel multi-streaming enables concurrent gaming/VoIP Emulation of 26 sound environments to enhance gaming experience Multi bands of software equalizer and tool are provided Voice Cancellation and Key Shifting effect Dynamic range control (expander, compressor and limiter) with adjustable parameters Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application Smart multiple streaming operation HDMI audio driver for AMD platform Dolby® PCEE program™ (optional software feature) DTS® CONNECT™ (optional software feature) SRS® TrueSurround HD (optional software feature) Fortemedia® SAM™ technology for voice processi ng (Beam Forming and Acoustic Echo Cancellation) (optional software feature) Creative® Host Audio program (optional software feature) 3. System Applications Desktop multimedia PCs Laptop PCs
Figure 1. Block Diagram
Pin Complex widgets NID=14h~1Bh are re-tasking IOs. Figure 2. Analog Input/Output Unit
7.1+2 Channel High Definition Audio Codec with Content Protection 6 Rev. 0.60 5. Pin Assignments LINE1-L SURR-L CENTER LFE SPDIF-OUT AVSS2 LDO-OUT2 CD-R CD-GND CD-L LINE1-R MIC2-L LINE2-L SIDE-L SIDE-R EAPD/SPDIFI JDREF SURR-R SENSE A FRONT-L FRONT-R SENSE B LINE2-VREFO MIC2-VREFO MIC1-VREFO-L VREF AVSS1 LDO-OUT1 SDATA-OUT BCLK SDATA-IN SYNC RESET# BEEP LINE2-R MIC2-R MIC1-R MIC1-L PORT-A-L PORT-G-R SPDIF-OUT AVSS2 LDO-OUT2 CD-R CD-GND CD-L PORT-C-R PORT-F-L PORT-E-LEAPD/SPDIFI JDREF SENSE A PORT-D-R PORT-B-VREFO-L PORT-E-VREFO VREF AVSS1 LDO-OUT1 SDATA-OUT BCLK SDATA-IN SYNC RESET# BEEP DVSS DVDD PORT-E-R PORT-F-R PORT-A-R PORT-G-L PORT-H-L PORT-H-R PORT-D-L PORT-F-VREFO PORT-B-R PORT-C-L PORT-B-L DVDD REGREF GPIO1/DMIC-DATA GPIO0/DMIC-CLK/SPDIF-OUT2 DVSS DVDD-IO GPIO2 VRP 123456789 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 GXXXVxXXXXXXX 123456789 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 ALC898 GXXXVxXXXXXXX DVDD-IO LDO-IN LDO-IN MIC1-VREFO-R VRP REGREF GPIO1/DMIC-DATA PORT-B-VREFO-R GPIO0/DMIC-CLK/SPDIF-OUT2 ALC898 SENSE B GPIO2 Figure 3 Pin Assignments * ALC898 is NOT pin compatible with ALC889, pin 3/4/25/29/37/38 are different with ALC889. 5.1. Green Package and Version Identification Location ‘G’ indicates Green package is used. The silicon version and step numbers are shown in the location marked ‘V’ and ‘x’.
Table 1. ALC898 Pin Description
2 General Purpose Input/Output /
4 General Purpose Input/Output /
Analog I/O (PORT –B), default 1st mic input. Analog I/O (PORT –B), default 1st mic input.
7.1+2 Channel High Definition Audio Codec with Content Protection 8 Rev. 0.60 Name Type Pin Description Characteristic Definition LINE1-L I/O 23 Analog input and output with multiple function – left channel Analog I/O (PORT –C), default 1st line input. Recommended to be line level input at rear panel LINE1-R I/O 24 Analog input and output with multiple function – right channel Analog I/O (PORT –C), default 1st line input. Recommended to be line level input at rear panel LDO-OUT1 - 25 Built-in LDO output for mixer & amp Need 10uF capacitor to analog ground and short with Pin38 A VSS1 G 26 Analog ground for mixer & amp Analog GND VREF - 27 0.5*LDO-OUT1 Reference voltage 10uf capacitor to analog ground VREFO-B O 28 Bias voltage for MIC1 (Port-B) Analog Output：2.5V/3.2V/4.0V reference voltage LDO-IN P 29 Built-in LDO input VDD (5V) VREFO-F O 30 Bias voltage for MIC2 (Port-F) Analog Output：2.5V/3.2V/4.0V reference voltage VREFO-E O 31 Bias voltage for LINE2 (Port-E) Analog Output：2.5V/3.2V/4.0V reference voltage VREFO-B(2) O 32 Secondary bias voltage for MIC1 Analog Output：2.5V/3.2V/4.0V reference voltage GPIO2 IO 33 General Purpose Input/Output Power by A VDD Analog Input: Threshold level is 0.5*A VDD, internal pull 50K pull up Analog Output: VOL <0.1*A VDD, VOH >0.9*A VDD SENSE B - 34 Jack Detect for resistor network Co nnect {5.1K, 10K, 20K, 39.2K} with 1% accuracy FRONT-L I/O 35 Analog input and output – left Analog I/O (PORT –D), default front channel output. FRONT-R I/O 36 Analog input and output – right Analog I/O (PORT –D), default front channel output. VRP - 37 Internal voltage for DAC, ADC 100uf polar capacitor to analog ground LDO-OUT2 - 38 Analog power for DAC and ADC Need 10uF capacitor to analog ground and short with Pin25 SURR-L I/O 39 Analog input and output – left Analog I/O (PORT –A), default surround channel. JDREF - 40 Reference for Jack Detect 20K, 1% resistor to AGND SURR-R I/O 41 Analog input and output – right Analog I/O (PORT –A), default surround channel. A VSS2 G 42 Analog ground for DAC & ADC Analog GND CENTER I/O 43 Analog input and output – left Analog I/O (PORT –G), default center channel. LFE I/O 44 Analog input and output – right Analog I/O (PORT –G), default lfe channel. SIDE-L I/O 45 Analog input and output – left Analog I/O (PORT –H), default side channel. SIDE-R I/O 46 Analog input and output – right Analog I/O (PORT –H), default side channel. SPDIF-IN / EAPD I/O 47 S/PDIF Input / External Amplifier Power Down Digital Input: Schmitt trigger (5V tolerance), VIL =0.44*DVDD, VIH =0.56*DVDD Digital Output: VOL <0.1*DVDD, VOH >0.9*DVDD SPDIF-OUT O (*2) Primary S/PDIF out Digital Output: V OL <0.1*DVDD, VOH >0.9*DVDD 10mA@75Ω Output driving Total: 48 Pins *1: Pin 2 and 4 have multiple functions. They are default works as GPIOs, will functions as digital MIC pins when the configuration register of digital MIC pin widget (node ID12h) is enabled, and exclusively functions as secondary S/PDIF-OUT when the configuration register of S/PDIF-OUT2 pin widget (node ID 11h) is enabled.
- High Definition Audio Link Protocol
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol. Figure 4. HDA Link Protocol
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported. Table 3. HDA Signal Definitions Figure 5. Bit Timing
the data stream is always carried on SDO0, the second bit on SDO1 and so forth. is always transmitted on SDO0, and copied on SDO1. Figure 9. Striped Stream on Multiple SDOs
Figure 12. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz.
Table 4. Defined Sample Rate and Transmission Rate Table 5. 48kHz Variable Rate of Delivery Timing Table 6. 44.1kHz Variable Rate of Delivery Timing
7.1+2 Channel High Definition Audio Codec with Content Protection 17 Rev. 0.60 88.2kHz 12 2- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with no sample block. 174.4kHz 12 4- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with no sample block.
7.1+2 Channel High Definition Audio Codec with Content Protection 18 Rev. 0.60 7.3. Reset and Initialization There are two types of reset within an HDA link:
- Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
- Codec Reset. Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events: 1. Link Reset 2. Codec Reset 3. Codec changes its power state (for example, hot docking a codec to an HDA system) 7.3.1. Link Reset A link reset may be caused by 3 events: 1. The HDA controller asserts RST# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA controller 3. Software initiates power management sequences. Figure 13, shows the ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v) Enter ‘Link Reset’: n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state r All link signals driven by controller and codecs should be tri-state by internal pull low resistors Exit from ‘Link Reset’: s If BCLK is re-started for any reason (codec wake-up event, power management, etc.) t Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the 100µsec provides time for the codec PLL to stabilize) u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
4 BCLK 4 BCLK
Figure 13. Link Reset Timing
Figure 14. Codec Initialization Sequence
controls parameters in the codec. Table 7. 40-Bit Commands in 4-Bit Verb Format Table 8. 40-Bit Commands in 12-Bit Verb Format
Table 9. Verbs Supported by the ALC898 (Y=Supported)
Table 10. Parameters in the ALC898 (Y=Supported) software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 11. Solicited Response Format
Table 12. Unsolicited Response Format an unsolicited response was sent. power control. Software can configure whole codec power states through the audio function (NID=01h). Software may have various power states depending on system configuration. Table 14 indicates those nodes that support power management. Table 13. System Power State Definitions D2 Powers are still supplied. All amplifiers and converters (DACs and ADCs) powered down. Codec stops PLL. State maintained and jack-detection/GPI work. D3 (Hot) Powers are still supplied. All amplifiers and converters (DACs and ADCs) powered down. Codec stops PLL. State maintained and jack-detection/GPI work. D3 (Cold) Powers are still supplied. All amplifiers and converters (DACs and ADCs) powered down. Codec stops PLL. State maintained. Jack-detection/GPI work when internal OSC power up. Table 14. Power Controls in NID 01h *1: Jack detection with unsolicited response is issued when the Link Reset occurs in D3 state.
Table 15. Powered Down Conditions
- Supported Verbs and Parameters
not supported by the addressed widget, it will respond with 32 bits of ‘0’. codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget. page 21, for detailed information about supported parameters. Table 16. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 17. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) Note: The Root Node (NID=00h) supports this parameter. Table 18. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 00h is for the first silicon version (A version), 01h is for the second version (B version), etc. Note: The Root Node (NID=00h in the ALC898) supports this parameter.
associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 19. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) Table 20. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) 7:0 Function Group Type. Read as 01h. Note: The Audio Function Group (NID=01h) supports this parameter.
Table 21. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h) 16 Beep Generator, read as 1. 11:8 Input Delay. Read as 0xF. 3:0 Output Delay. Read as 0xF. Note: The Audio Function Group (NID=01h) supports this parameter. Table 22. Parameter – Audio Widget Capa bilities (Verb ID=F00h, Parameter ID=09h)
10 Power Control
9 Digital
4 Format Override
3 AmpParOvr, AMP Param Override
0 Stereo
parameters to provide supported formats if their ‘Format Override’ bit is set. Table 23. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 24. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
2 AC3
1 Float32
0 PCM
Note: Input converters and output converters support this parameter.
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 25. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch)
6 Balanced I/O Pin
5 Input Capable
4 Output Capable
3 Headphone Drive Capable
2 Presence Detect Capable
1 Trigger Required
0 Impedance Sense Capable
Note: Only Pin Complex widgets support this parameter. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 26. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 27. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. Parameters in this node provide audio function widget connection information. Table 28. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
7 Short Form
Table 29. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
31 Extended Power States Supported (EPSS)
30 CLKSTOP
3 D3Sup
2 D2Sup
1 D1Sup
0 D0Sup
Table 30. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h)
0 Benign
Table 31. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h)
31 GPIWake=0
30 GPIUnsol=1
Table 32. Parameter – Volume Knob Capa bilities (Verb ID=F00h, Parameter ID=13h) The total number of steps in the range of the V olume Control Knob (NID=21h), response=0x20. ALC898 does not support Volume Knob, will response 0s to this parameter. Table 33. Verb – Get Connection Select Control (Verb ID=F01h)
7:0 Connection Index Current Settings (Default Value is 00h). Table 34. Verb – Set Connection Select (Verb ID=701h) Table 35. Verb – Get Connection List Entry (Verb ID=F02h) 31:8 Connection List Entry (N+3), (N+2), and (N+1).
7.1+2 Channel High Definition Audio Codec with Content Protection 36 Rev. 0.60 7:0 Connection List Entry (N). Returns 24h (Sum Widget) for N=0~3. Returns 00h for N>3. Codec Response for NID=08h (LINE ADC) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 23h (Sum Widget) for N=0~3 Returns 00h for N>3 Codec Response for NID=09h (MIX ADC) Bit Description 15:8 Connection List Entry (N+3), (N+2), and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 22h (Sum Widget) for N=0~3 Returns 00h for N>3 Codec Response for NID=0Ah (S/PDIF-IN Converter) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3 Returns 00h for N>3 Codec Response for NID=0Bh (Mixer) Bit Description 31:24 Connection List Entry (N+3) Returns 1Bh (Pin Complex – LINE2) for N=0~3 Returns 15h (Pin Complex-SURR) for N=4~7 Returns 00h for N>7 23:16 Connection List Entry (N+2) Returns 1Ah (Pin Complex – LINE1) for N=0~3 Returns 14h (Pin Complex – FRONT) for N=4~7 Returns 00h for N>7 15:8 Connection List Entry (N+1) Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7 Returns 17h (Pin Complex – SIDESURR) for N=8~11 Returns 00h for N>11
7.1+2 Channel High Definition Audio Codec with Content Protection 37 Rev. 0.60 7:0 Connection List Entry (N) Returns 18h (Pin Complex – MIC1) for N=0~3 Returns 1Ch (Pin Complex – CD) for N=4~7 Returns 16h (Pin Complex – CEN/LFE) for N=8~11 Returns 00h for N>11 Codec Response for NID=0Ch (Front Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 02h (Front DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID=0Dh (Surround Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Eh (Cen/LFE Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 04h (Cen/LFE DAC) for N=0~3 Returns 00h for N>3
7.1+2 Channel High Definition Audio Codec with Content Protection 38 Rev. 0.60 Codec Response for NID=0Fh (Side-Surr Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 05h (Front DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID=26h (Fout Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 25h (Fout1 DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID=14h~1Bh (Port-A/B/C/D/E/F/G/H) Bit Description 31:24 Connection List Entry (N+3) Returns 0Fh (Sum Widget NID=0Fh) for N=0~3 Returns 00h for n>3 23:16 Connection List Entry (N+2) Returns 0Eh (Sum Widget NID=0Eh) for N=0~3 Returns 00h for N>3 15:8 Connection List Entry (N+1) Returns 0Dh (Sum Widget NID=0Dh) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 0Ch (Sum Widget NID=0Ch) for N=0~3 Returns 26h (Sum Widget NID=26h) for N=4~7 Returns 00h for N>7
7.1+2 Channel High Definition Audio Codec with Content Protection 39 Rev. 0.60 Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT) Bit Description 31:16 Connection List Entry (N+3) and (N+2) Returns 0000h 15:8 Connection List Entry (N+1) Returns 00h 7:0 Connection List Entry (N) Returns 06h (S/PDIF-OUT converter) for N=0~3 Returns 00h for N>3 Codec Response for NID=11h (Pin Widget: S/PDIF-OUT2) Bit Description 31:16 Connection List Entry (N+3) and (N+2) Returns 0000h 15:8 Connection List Entry (N+1) Returns 00h 7:0 Connection List Entry (N) Returns 10h (S/PDIF-OUT2 converter) for N=0~3 Returns 00h for N>3 Codec Response for NID= 22h/23h (Sum Widget before ADC 08h and ADC 09h) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 15h (Pin Complex-SURR) for N=4~7. Returns 00h for N>7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 0Bh (Sum Widget) for N=8~11. Returns 00h for N>11. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7. Returns 17h (Pin Complex – SIDESURR) for N=8~11. Returns 00h for N>11. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 1Ch (Pin Complex – CD) for N=4~7. Returns 16h (Pin Complex – CEN/LFE) for N=8~11. Returns 00h for N>11.
31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 15h (Pin Complex-SURR) for N=4~7. Returns 12h (Pin Complex- digital MIC) for N=8~11. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 0Bh (Sum Widget) for N=8~11. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7. Returns 17h (Pin Complex – SIDESURR) for N=8~11. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 1Ch (Pin Complex – CD) for N=4~7. Returns 16h (Pin Complex – CEN/LFE) for N=8~11. Table 36. Verb – Get Processing State (Verb ID=F03h) Table 37. Verb – Set Processing State (Verb ID=703h)
Table 38. Verb – Get Coefficient Index (Verb ID=Dh) Table 39. Verb – Set Coefficient Index (Verb ID=5h)
Table 40. Verb – Get Processing Coefficient (Verb ID=Ch) Table 41. Verb – Set Processing Coefficient (Verb ID=4h)
This verb is used to get gain/attenuation settings from each widget. Table 42. Verb – Get Amplifier Gain (Verb ID=Bh)
15 Get Input/Output
13 Get Left/Right
7.1+2 Channel High Definition Audio Codec with Content Protection 44 Rev. 0.60 Codec Response for NID=0Ch~0Fh and 26h (Sum Widget: Front, Surr, Cen/LFE, SIDESURR, Fout Sum) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain. Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’. Output Amplifier Gain [6:0]. 7-bit step value (0~87) specifying the volume from –65.25dB~0dB in 0.75dB steps. Codec Response for NID=14h~17h (Pin Complex: Front/Surr/CenLFE/SIDESURR) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain. Read as 0 Bit-15 is 1 in ‘Get Amplifier Gain. Output Amplifier Mute, 0:Unmute, 1:Mute (NID=14h~17h,Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain. Read as 0’s Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Gain) Codec Response for NID=18h~1Bh (Pin Complex: Front/Surr/CenLFE/SIDESURR/MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain. Read as 0 Bit-15 is 1 in ‘Get Amplifier Gain. Output Amplifier Mute, 0:Unmute, 1:Mute (NID=18h~1Bh,Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain. Input Amplifier Gain [6:0]. 7-bit step value (0~3) specifying the volume from 0dB~30dB in 10dB steps Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Gain) Codec Response for NID=22h and 23h (Sum Widget) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain. Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain . Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Input Amplifier Gain) Codec Response to Other NID Bit Description 31:0 Not supported (returns 00000000h)
This verb is used to set amplifier gain/attenuation in each widget. Table 43. Verb – Set Amplifier Gain (Verb ID=3h)
15 Set Output Amp
14 Set Input Amp
13 Set Left Amp
12 Set Right Amp
7 Mute
Table 44. Verb – Get Converter Format (Verb ID=Ah)
15 Stream Type (TYPE)
14 Sample Base Rate (BASE)
Table 45. Verb – Set Converter Format (Verb ID=2h)
Table 46. Verb – Get Power State (Verb ID=F05h)
10 PS-SettingReset
0: Setting of widgets have been reset during any low power state.
9 PS-ClkStopOk
0: No capability to operate normally with BCLK stop. 1: Operate properly with no BCLK. Only Audio Function Group (NID=01h) supports this setting.
8 PS-Error
Table 47. Verb – Set Power State (Verb ID=705h) PS-Act indicates the actual power state of the referenced node.
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. Table 48. Verb – Set Converter Stream, Channel (Verb ID=706h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. (NID=07h~0Ah). Other widgets will ignore this verb.
Table 49. Verb – Get Pin Widget Control (Verb ID=F07h)
7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit)
6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
Table 50. Verb – Set Pin Widget Control (Verb ID=707h)
unsolicited response to inform software of a real-time event. Table 51. Verb – Get Unsolicited Response Control (Verb ID=F08h)
7 Unsolicited Response is Enabled
Enables a widget to generate an unsolicited response. Table 52. Verb – Set Unsolicited Response Control (Verb ID=708h)
7 Enable Unsolicited Response
Returns the Presence Detect status and the impedance of a device attached to the pin. Table 53. Verb – Get Pin Sense (Verb ID=F09h)
31 Presence Detect Status
The ALC898 does not support hardware impedance detection. This field is read as 0s. Table 54. Verb – Execute Pin Sense (Verb ID=709h)
0 Right (Ring) Channel Select
The ALC898 does not support hardware impedance sensing and will ignore this control.
Table 55. Verb – Get Volume Knob (Verb ID=F0Fh)
7 Direct
is responsible for programming the amplifier appropriately. 1: The volume generated by external HW volume control will directly affect the volume of the amplifier. The ALC898 does not support this Verb. Table 56. Verb – Set Volume Knob (Verb ID=70Fh) is responsible for programming the amplifier appropriately. 1: The volume generated by external HW volume control will directly affect the volume of the amplifier. The ALC898 does not support this Verb.
Reads the 32-bit sticky register for each Pin Widget configured by software. Table 57. Verb – Get Configuration Default (Verb ID=F1Ch)
1Eh and 1Fh, e.g., placement and expected default device. Table 58. Verb – Set Configuration Default Bytes 0, 1, 2, 3 1Fh(S/PDIF-IN), 11h(S/PDIF-OUT2) and 12h(Digital MIC). Other widgets will ignore this verb.
Table 59. Verb – Get BEEP Generator (Verb ID= F0Ah) Table 60. Verb – Set BEEP Generator (Verb ID= 70Ah) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 61. Verb – Get GPIO Data (Verb ID= F15h) Table 62. Verb – Set GPIO Data (Verb ID= 715h)
Table 63. Verb – Get GPIO Enable Mask (Verb ID= F16h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 64. Verb – Set GPIO Enable Mask (Verb ID=716h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 65. Verb – Get GPIO Direction (Verb ID=F17h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 66. Verb – Set GPIO Direction (Verb ID=717h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 67. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 68. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled.
Table 69. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets in the ALC898 to return to their power on default state. Table 70. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
23 Keep Alive Enable
Not supported in ALC898, read as 0’s.
15 Read as 0
7 LEVEL (Generation Level)
6 PRO (Professional or Consumer format)
7.1+2 Channel High Definition Audio Codec with Content Protection 63 Rev. 0.60 NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh/F0Eh/F3Eh/F3Fh NID=10h (S/PDIF-OUT2) Response to ‘Get verb’ – F0Dh/F0Eh/F3Eh/F3Fh Bit Description – SIC (S/PDIF IEC Control) Bit[15:0] 5 /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data
4 COPY (Copyright)
0: Asserted 1: Not asserted
3 PRE (Pre-emphasis)
0: None 1: Filter pre-emphasis is 50/15 microseconds
2 VCFG for Validity Control (control V bit and data in Sub-Frame)
1 V for Validity Control (control V bit and data in Sub-Frame)
0 Digital Enable. DigEn 0: OFF 1: ON NID=0Ah (S/PDIF-IN) Response to ‘Get verb’ - F0Dh/F0Eh Bit Description (part of S/PDIF-IN Channel Status) 31:16 Reserved. Read as 0’s 15 Reserved. Read as 0’s 14:8 CC[6:0] (Category Code) 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data 0: Asserted 1: Not asserted 0: None 1: Filter pre-emphasis is 50/15 microseconds
2 Reserved
1 In‘V’alid. V bit in sub-frame of S/PDIF-IN 0: Data X and Y are valid, or S/PDIF-IN is not locked 1: At least one of data X and Y is invalid 0 Digital Enable. DigEn 0: OFF 1: ON
Table 71. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
7.1+2 Channel High Definition Audio Codec with Content Protection 65 Rev. 0.60 ‘Payload’ in Set Control 1 for NID=06h and 10h (S/PDIF-OUT and S/PDIF-OUT2) 0 Digital Enable. DigEn 0: OFF 1: ON ‘Payload’ in Set Control 2 for NID=06h and 10h (S/PDIF-OUT and S/PDIF-OUT2) Bit Description – SIC (S/PDIF IEC Control) Bit[15:8] 7 Reserved. Read as 0’s 6:0 CC[6:0] (Category Code) ‘Payload’ in Set Control 3 for NID=06h and 10h (S/PDIF-OUT and S/PDIF-OUT2) Bit Description – SIC (S/PDIF IEC Control) Bit[23:16]
7 Keep Alive Enable
0: Disable, S/PDIF output would be disabled in D2/D3 mode 1: Enable, S/PDIF output would be enabled in D2/D3 mode 6:0 Reserved ‘Payload’ in Set Control 4 for NID=06h and 10h (S/PDIF-OUT and S/PDIF-OUT2) Bit Description – SIC (S/PDIF IEC Control) Bit[31:24] 7:0 Reserved ‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7:1 Reserved 0 Digital Enable. DigEn 0: OFF 1: ON ‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7:0 Reserved. Read as 0’s Note: Other widgets will ignore this verb.
Table 72. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) 15:8 Subsystem ID[7:0]. (Default=08h). 7:0 Assembly ID[7:0 ]. (Default=99h). Table 73. Verb – Set Subsystem ID [31:0] (Verb ID=723h, 722h, 721h, 720h)
Table 74. Verb – Get EAPD Control (Verb ID=F0Ch)
2 L-R Swap
The ALC898 does not support swapping left and right channels, read as 0.
1 EAPD Value
0 BTL Enable
ALC898 does not support BTL output, read as 0. Table 75. Verb – Set EAPD Control (Verb ID=70Ch) 7:3 Reserved, written data is ignored. The ALC898 does not support swapping left and right channels, written data is ignored. ALC898 does not support BTL output, written data is ignored.
7.1+2 Channel High Definition Audio Codec with Content Protection 68 Rev. 0.60 Payload in Set Commend for NID=14h (FRONT, port-D) and 1Bh (LINE2, port-E) Codec Response Bit Description 31:0 0’s
- Electrical Characteristics
Table 76. Absolute Maximum Ratings Note*: The digital link power DVDD-IO must be lower than the digital core power DVDD. different LDO-IN should contact Realtek technical support representatives for special testing support. DVDD-IO= 1.5V±5% / 3.3V±5%, DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load. Table 77. Threshold Voltage
Table 78. Digital Filter Characteristics nFs are 48KHz, 96KHz, 192KHz and 44.1KHz, 88.2KHz, 176.4KHz sample rates. nFs are 48KHz, 96KHz, 192KHz and 44.1KHz, 88.2KHz, 176.4KHz sample rates. oThe high pass filter is used to filter out the DC offset generated by analog mismatch in ADC circuitry. DVDD= 3.3V, Tambient=25°C, with 75Ω external load. Table 79. S/PDIF Input/Output Characteristics
Table 80. Link Reset and Initialization Timing
4 BCLK 4 BCLK >= 4 BCLK
Figure 15. Link Reset and Initialization Timing
Table 81. Link Timing Parameters at the Codec Figure 16. Link Signals Timing
Table 82. S/PDIF Output and Input Timing Figure 17. Output and Input Timing
- 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
- 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 83. Analog Performance
7.1+2 Channel High Definition Audio Codec with Content Protection 75 Rev. 0.60 10. Application Circuits To get the best compatibility in hardware design and software driver, any modification should be confirmed with Realtek. Realtek may update the latest application circuits onto our web site (www.realtek.com) without modifying this datasheet 10.1. Desktop System This section shows an example of desktop system has three analog jacks at rear panel has 7.1 channel output and two re-tasking analog jacks at front panel. Analog Port Pin Location Function Description FRONT (Port-D) 35, 36 Rear Panel Front channel line output and amplified output SURR (Port-A) 39, 41 Rear Panel Surround channel line output CENTER/LFE (Port-G) 43, 44 Rear Panel Center and low frequ ency (sub-woofer) channel line output SIDE (Port-H) 45, 46 Rear Panel Side surround channel line output MIC1 (Port-B) 21, 22 Rear Panel Analog microphone input LINE1 (Port-C) 23, 24 Rear Panel Analog line input LINE2 (Port-E) 14, 15 Front Panel Re-tasking jack supports headphone out (default), microphone input and line input MIC2 (Port-F) 16, 17 Front Panel Re-tasking jack supports microphone input (default), line input and headphone output
Figure 18. Filter connection
7.1+2 Channel High Definition Audio Codec with Content Protection 77 Rev. 0.60 For HP-OUT port, R33/R35 should be 33ohm. AUDIO FRONT HEADER MIC2-L MIC2-R LINE2-R LINE2-L MIC2-VREFO LINE2-VREFO MIC2-JD LINE2-JDR41 4.7K R40 4.7K R23 4.7K PRESENCE# Key BAT54A/SOT BAT54A/SOT +C23 100u +C24 100u +C27 100u +C30 100u R35 33 R33 33 R45 22K R46 22K R44 22K R43 22K R28 75 R30 75 GPI to South Bridge +3.3VD J2 CON10A R27 10K R24 4.7K PORT-F-SENSE-RETURN FIO-SENSE PORT-E-SENSE-RETURN FIO-PORT-F-R FIO-PRESENCE# FIO-PORT-F-L L21 FERB C57 100P HD Audio Front Panel I/O Module C58 100P L19 FERB L18 FERB C54 100P C55 100P L20 FERB FIO-SENSE FIO-SENSE PORT-F-SENSE-RETURN KEY PORT-E-SENSE-RETURN FIO-PORT-E-L PORT-E (LINE2) and PORT-F (MIC2) are front panel I/O FIO-PORT-F-L FIO-PORT-E-R JACK 7 FIO-PORT-E (Port-E) FIO-PORT-F-R JACK 8 FIO-PORT-F (Port-F) FIO-PORT-E-R CON10A 10FIO-PORT-E-L
In standby mode the ALC898 turn on all DC bias on all analog input and output ports (NID=14h~1Bh). This is a special application to avoid ‘PoP’ noise while system is in power on and power off transition. Table 84 shows the DC bias state when Standby mode is enabled. Table 84. Standby Mode
7.1+2 Channel High Definition Audio Codec with Content Protection 81 Rev. 0.60 12. Mechanical Dimensions L MILLIMETER INCH SYMBOL MIN TYP MAX MIN TYP MAX A 1.60 0.063 A1 0.05 0.15 0.002 0.006 c 0.09 0.20 0.004 0.008 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 E 9.00 BSC 0.354 BSC E1 7.00BSC 0.276 BSC E2 5.50 0.217 e 0.50 BSC 0.0196 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o L1 1.00 0.0393 TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm LEADFRAME MATERIAL DOC. NO. APPROVE VERSION 02 DWG NO. PKGC-065 CHECK DATE REALTEK SEMICONDUCTOR CORP.
Table 85. Ordering Information