ALC888S-VD_11_05 REALTEK | Alldatasheet
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(PN: ALC888S-VD2-GR) 7.1+2 CHANNEL HD AUDIO CODEC WITH TWO INDEPENDENT SPDIF OUTPUTS DATASHEET Rev. 1.2
31 May 2011
Track ID: JATR-2265-11 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs ii Track ID: JATR-2265-11 Rev. 1.2 COPYRIGHT ©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and soft ware engineer’s general information on the Realtek ALC888S-VD IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary 1.0 2011/03/18 First release. 1.1 2011/03/31 Corrected minor typing errors. 1.2 2011/05/31 Revised Jack Detection pins from two to three Revised Table 87, page 76 (Dynamic Range with –60dB Signal parameters).
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs iii Track ID: JATR-2265-11 Rev. 1.2 Table of Contents
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs iv Track ID: JATR-2265-11 Rev. 1.2 8.28. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 59 8.43. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs v Track ID: JATR-2265-11 Rev. 1.2
TABLE 77. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 1 Track ID: JATR-2265-11 Rev. 1.2 1. General Description The ALC888S-VD provides ten DAC ch annels that simultaneously suppo rt 7.1 channel sound playback, plus 2 channels of independent stereo sound output (multiple streaming) through the front panel stereo outputs. Two stereo ADCs and one stereo digital microphone converter are inte grated and can support a microphone array with Acoustic Echo Cancellati on (AEC), Beam Forming (BF), and Noise Suppression (NS) technologies. All analog I/O are input and output cap able, and headphone amplifiers are also integrated at three analog output ports (port-D/port-E/port-F). All analog I/Os can be re-tasked according to user definitions. Support for 16/20/24-bit SPDIF input and output with up to 192kHz sample rate offers easy connection of PCs to consumer electronic products such as dig ital decoders and speakers. The ALC888S-VD also features secondary SPDIF-OUT out put and converter to transport digital audio out put to a High Definition Media Interface (HDMI) transmitter. The ALC888S-VD supports host audio from the Intel ch ipsets, and also from any other HDA compatible audio controller. With various software utilitie s like environment sound emulation, multiple-band and independent software equalizer, dynamic range compressor and expander, optional Dolby PCEE program, SRS TruSurround HD, SRS Premium Sound, Fortemedia SAM, Creative Host Audio, Synopsys Sonic Focus, DTS Surround Sensation | UltraPC, and DT S Connect licenses, the ALC888S-VD offers the highest sound quality, providing an excellent entertainment package and game experience for PC users. The ALC888S-VD is an upgraded version of the ALC 888S-VC, with lower power consumption. It also features a built-in Low-dropout (LDO) regulator to reduce customer’s external circuit cost.
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 2 Track ID: JATR-2265-11 Rev. 1.2 2. Features 2.1. Hardware Features DACs with 95dB SNR (A-weighting), ADCs with 90dB SNR (A-weighting) Ten DAC channels support 16/20/24-bit PCM format for 7.1 channel sound playback, plus 2 channels of concurrent independent stereo sound output (multiple streaming) through the front panel output Two stereo ADCs support 16/20/24-bit PCM format, multiple stereo recording All DACs supports 44.1k/48k/96k/192kHz sample rate All ADCs supports 44.1k/48k/96k/192kHz sample rate Primary 16/20/24-bit SPDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample rate Secondary 16/20/24-bit SPDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample rate 16/20/24-bit SPDIF-IN supports 44.1k/48k/96k/192kHz sample rate All analog jacks (port-A to port-G) are stereo input and output re-tasking Port-D/E/F built-in headphone amplifiers Port-B/C/E/F with software selectable boost gain (+10/+20/+30dB) for analog microphone input High-quality analog differential CD input Supports external PCBEEP input and built-in digital BEEP generator Software selectable 2.5V/3.2V/4.0V VREFOUT Up to four channels of microphone array input are supported for AEC/BF applications Three jack detection pins; each designed to detect up to 4 jacks Supports legacy analog mixer architecture Up to two GPIOs (General Purpose Input and Output) for customized applications. GPIO0 and GPIO1 share pin with DMIC-CLK and DMIC-DATA Supports mono and stereo digital microphone interface (pins shared with GPIO0 and GPIO1) Supports anti-pop mode when analog power LDO-IN is on and digital power is off 1dB per step output volume and input volume control Supports 3.3V digital core power, 1.5V or 3.3V digital I/O power for HD Audio link, and 5.0V analog power
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 3 Track ID: JATR-2265-11 Rev. 1.2 Intel low power ECR compliant and power status control for each analog/digital converter and pin widget Built-in Low-dropout (LDO) regulator Ultra low power consumption in anti-pop mode 48-pin LQFP ‘Green’ package 2.2. Software Features Meets Microsoft WLP 3.x and future WLP audio requirements WaveRT-based audio function driver for Windows Vista and Windows 7 Direct Sound 3D™ compatible I3DL2 compatible 7.1+2 channel multi-streaming enables concurrent gaming/VoIP Emulation of 26 sound environments to enhance gaming experience Multiband software equalizer and tools provided Voice Cancellation and Key Shifting effect Dynamic range control (expander, compressor, and limiter) with adjustable parameters Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice applications Smart multiple streaming operation HDMI audio driver for AMD platform Optional Dolby PCEE program, SRS TruSurround HD, SRS Premium Sound, Fortemedia SAM, Creative Host Audio, Synopsys Sonic Focus, DTS Surround Sensation | UltraPC, and DTS Connect licenses
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 4 Track ID: JATR-2265-11 Rev. 1.2 3. System Applications Desktop multimedia PCs Notebook PCs
Figure 1. Block Diagram
Pin Complex widgets NID=14h~1Bh are re-tasking IOs. Figure 2. Analog Input/Output Unit
Figure 3. Pin Assignments shown in the location marked ‘V’ and ‘S’.
For a convenient list of ALC888S-VD vs. ALC888S-VC pin differences, see section 6.2, page 10. Table 1. Pin Descriptions Analog I/O (PORT-E-L), default 2nd line input. Analog I/O (PORT-E-R), default 2nd line input. Analog I/O (PORT-F-L), default 2nd mic input.
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 9 Track ID: JATR-2265-11 Rev. 1.2 Name Type Pin Description Characteristic Definition MIC2-R IO 17 Analog Input and Output with Multiple Function (Right) Analog I/O (PORT-F-R), default 2nd mic input. Recommended to be re-tasking port at front panel CD-L I 18 CD Input Left Channel Analog Input: 1.6Vrms of full-scale input CD-GND I 19 CD Input Reference Ground Analog Input: 1.6Vrms of full-scale input CD-R I 20 CD Input Right Channel Analog Input: 1.6Vrms of full-scale input MIC1-L IO 21 Analog Input and Output with Multiple Function (Left) Analog I/O (PORT-B-L), default 1st mic input. Recommended to be microphone input at rear panel MIC1-R IO 22 Analog Input and Output with Multiple Function (Right) Analog I/O (PORT-B-R), default 1st mic input. Recommended to be microphone input at rear panel LINE1-L IO 23 Analog Input and Output with Multiple Function (Left) Analog I/O (PORT-C-L), default 1st line input. Recommended to be line level input at rear panel LINE1-R IO 24 Analog Input and Output with Multiple Function (Right) Analog I/O (PORT-C-R), default 1st line input. Recommended to be line level input at rear panel LDO-OUT1 - 25 Built-In LDO Output for Mixer & Amp Needs 10µF capacitor to analog ground, and short to Pin38 A VSS1 G 26 Analog Ground for Mixer & Amp Analog GND VREF - 27 0.5×LDO-OUT1 Reference V oltage 10µF capacitor to analog ground MIC1-VREFO-L O 28 Bias V oltage for MIC1 (Port-B) Analog Output: 2.5V/3.2V/4.0V reference voltage LDO-IN P 29 Built-In LDO Input VDD (5V) MIC2-VREFO O 30 Bias V oltage for MIC2 (Port-F) Analog Output: 2.5V/3.2V/4.0V reference voltage LINE2-VREFO O 31 Bias V oltage for LINE2 (Port-E) Analog Output: 2.5V/3.2V/4.0V reference voltage MIC1-VREFO-R O 32 Secondary Bias V oltage for MIC1 (Port-B) Analog Output: 2.5V/3.2V/4.0V reference voltage Sense C - 33 Jack Detect for Resistor Network Connector {5.1K, 10K, 20K, 39.2K} with 1% accuracy Sense B - 34 Jack Detect for Resistor Network Connector {5.1K, 10K, 20K, 39.2K} with 1% accuracy FRONT-L IO 35 Analog Input and Output (Left) Analog I/O (PORT-D-L), default front channel output FRONT-R IO 36 Analog Input and Output (Right) Analog I/O (PORT-D-R), default front channel output PIN37-VREFO O 37 Bias V oltage Analog Output: 2.5V/3.2V/4.0V reference voltage LDO-OUT2 - 38 Analog Power for DAC and ADC Needs 10µF capacitor to analog ground, and short to Pin25 SURR-L IO 39 Analog Input and Output (Left) Analog I/O (PORT-A-L), default surround channel JDREF - 40 Reference for Jack Detect 20K, 1% resistor to AGND SURR-R IO 41 Analog Input and Output (Right) Analog I/O (PORT-A-R), default surround channel
SPDIF-OUT when the configuration register of the SPDIF-OUT2 pin widget (node ID 11h) is enabled. Table 2. Pin Differences : ALC888S-VD vs. ALC888S-VC SPDIF-OUT, GPIO, and digital microphone interface. Pin 3(*) REGREF GPIO0/DMIC-CLK Pin 3 is used as reference for the integrated regulator. Pin 29(*) LDO-IN LINE1-VREFO Pin 29 is used as VDD input for the built-in LDO. (*) Please notice external circuit connected to pin3/pin29 if ALC888S-VD is directly mounted on C version layout.
- High Definition Audio Link Protocol
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol. Figure 4. HDA Link Protocol
Table 3. Link Signal Definitions controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported. Table 4. HDA Signal Definitions SDI Codec/Controller Input/Output Serial Data Input from Codec. Figure 5. Bit Timing
the data stream is always carried on SDO0, the second bit on SDO1 and so forth. is always transmitted on SDO0, and copied on SDO1. Figure 9. Striped Stream on Multiple SDOs
Figure 12. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz. blocks are transmitted every 160 frames.
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence AND interleave n empty frames. AND interleave an empty frame between non-empty frames (Table 7, page 19). Table 5. Defined Sample Rate and Transmission Rate Table 6. 48kHz Variable Rate of Delivery Timing N: No sample block in a frame. Y: One sample block in a frame. x: X sample blocks in a frame.
Table 7. 44.1kHz Variable Rate of Delivery Timing
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 20 Track ID: JATR-2265-11 Rev. 1.2 7.3. Reset and Initialization There are two types of reset within an HDA link:
- Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
- Codec Reset. Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events:
- Link Reset
- Codec Reset
- Codec changes its power state (for example, hot docking a codec to an HDA system) 7.3.1. Link Reset A link reset may be caused by 3 events: 1. The HDA controller asserts RST# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ b it in the Global Control Register (GCR) of the HDA controller 3. Software initiates power management sequences. Figure 13, shows the ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v) Enter ‘Link Reset’: n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
4 BCLK 4 BCLK
Figure 13. Link Reset Timing
Figure 14. Codec Initialization Sequence controls parameters in the codec. Table 8. 40-Bit Commands in 4-Bit Verb Format Table 9. 40-Bit Commands in 12-Bit Verb Format
Table 10. Verbs Supported by the ALC888S-VD (Y=Supported) *1: The ALC888S-VD does not support Modem Function, HDMI Function, Vendor Defined Groups, and Power Widgets.
Table 11. Parameters in the ALC888S-VD (Y=Supported) *1: The ALC888S-VD does not support Modem Function, HDMI Function, Vendor Defined Groups, and Power Widgets.
software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 12. Solicited Response Format Table 13. Unsolicited Response Format ‘Valid’ bit to indicate the response is ‘Ready’. Bit 34 is set to indicate that an unsolicited response was sent. (NID=01h). Software may have various power states depending on system configuration. Table 15 indicates those nodes that support power management. Table 14. System Power State Definitions D0 All Power On. Individual DACs and ADCs can be powered up or down as required. D1 All Converters (DACs and ADCs) are Powered Down . State maintained, analog reference stays up. D2 Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down. Codec stops PLL. State maintained. Jack-detection and GPI are powered down. D3 (Hot) Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down. Codec stops PLL. State maintained. Jack-detection/GPI work. D3 (Cold) Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down. Codec stops PLL. State maintained. Jack-detection/GPI work when internal OSC powers up.
Table 15. Power Controls in NID 01h Note 2: Jack detection with unsolicited response is issued when a Link Reset occurs in D3 state. Table 16. Powered Down Conditions LINK Response Powered Down Internal Clock is Stopped. SDATA-IN and SPDIF-OUT are floated with internally pulled low 47K resistors. sequences is supported. All states are maintained if DVDD is supplied. FRONT DAC Powered Down Analog Block and Digital Filter are Powered Down. SURR DAC Powered Down Analog Block and Digital Filter are Powered Down. CEN/LFE DAC Powered Down Analog Block and Digital Filter are Powered Down. SIDESURR DAC Powered Down Analog Block and Digital Filter are Powered Down. FOUT DAC Powered Down Analog Block and Digital Filter are Powered Down. LINE ADC Powered Down Analog Block and Digital Filter are Powered Down. MIX ADC Powered Down Analog Block and Digital Filter are Powered Down. Headphone Driver Powered Down All Headphone Drivers are Powered Down. Mixers Powered Down All Internal Mixer Widgets are Powered Down. The DC reference and VREFOUTx at individual pin complexes are still alive.
- Supported Verbs and Parameters
verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’. codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget. page 22, for detailed information about supported parameters. Table 17. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) 31:16 Vendor ID=10ECh (Realtek’s PCI Vendor ID). Note: The Root Node (NID=00h) supports this parameter. Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 31:24 Reserved. Read as 0’s. 15:8 Revision ID. The vendor’s revision number. 00h is for the first silicon version (A version), 01h is for the second version (B version), etc. 7:0 Stepping ID. The vendor’s stepping number within the given Revision ID. Note: The Root Node (NID=00h in the ALC888S-VD) supports this parameter.
associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) 31:24 Reserved. Read as 0’s. The starting node number in the sequential widgets. For a root node, the total number of function groups in the root node. For a function group, the total number of widget nodes in the function group. Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) 7:0 Function Group Type. Read as 01h. Note: The Audio Function Group (NID=01h) supports this parameter.
Table 22. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h) 31:17 Reserved. Read as 0’s. 16 Beep Generator, Read as 1. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0’s. 11:8 Input Delay. Read as 0xF. 3:0 Output Delay. Read as 0xF. Note: The Audio Function Group (NID=01h) supports this parameter. Table 23. Parameter – Audio Widget Capab ilities (Verb ID=F00h, Parameter ID=09h) 31:24 Reserved. Read as 0’s. 19:16 Delay. Samples delayed between the HDA link and widgets. 15:11 Reserved. Read as 0’s. 8 ConnList. Connection List. 7 UnsolCap. Unsolicited Capable. 6 ProcWidget. Processing Widget. 3 AmpParOvr, AMP Param Override. 2 OutAmpPre. Out AMP Present.
parameters to provide supported formats if their ‘Format Override’ bit is set. Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) 31:21 Reserved. Read as 0’s. 20 B32. 32-bit audio format support. 19 B24. 24-bit audio format support. 18 B20. 20-bit audio format support. 17 B16. 16-bit audio format support. 16 B8. 24-bit audio format support. 15:12 Reserved. Read as 0’s. 11 R12. 384kHz (=8×48kHz) rate support. 10 R11. 192kHz (=4×48kHz) rate support. 8 R9. 96kHz (=2×48kHz) rate support. 7 R8. 88.2kHz (=2×44.1kHz) rate support. 4 R5. 32kHz (=2/3×48kHz) rate support. 2 R3. 16kHz (=1/3×48kHz) rate support. 0 R1. 8kHz (=1/6×48kHz) rate support.
have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Note: Input converters and output converters support this parameter. The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 26. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch) specified as a percentage of LDO-OUT1. 7 L-R Swap. Indicates the capability of swapping the left and right. 6 Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins. 5 Input Capable. ‘1’ indicates this pin complex supports input. 4 Output Capable. ‘1’ indicates this pin complex supports output. 3 Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone. 2 Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in. 1 Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement. ‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type. Note: Only Pin Complex widgets support this parameter.
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 27. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. Indicates which step is 0dB. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 28. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 6:0 Offset. Indicates which step is 0dB.
Parameters in this node provide audio function widget connection information. Table 29. Parameter – Connect List Le ngth (Verb ID=F00h, Parameter ID=0Eh) input, and there is no Connection Select Control (not a MUX widget). Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) 31 Extended Power States Supported (EPSS).
Table 31. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h) 31:16 Reserved. Read as 0’s. 15:8 NumCoeff. Number of Coefficient. Table 32. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h) 31 GPIWake=0. The ALC888S-VD does not support GPIO wake up function. 30 GPIUnsol=1. The ALC888S-VD supports GPIO unsolicited response. 29:24 Reserved. Read as 0’s. 23:16 NumGPIs=00h. No GPI pin is supported. 15:8 NumGPOs=00h. No GPO pin is supported. 7:0 NumGPIOs=02h. Two GPIO pins are supported. Table 33. Parameter – Volume Knob Capa bilities (Verb ID=F00h, Parameter ID=13h) Note: The Volume Control knob (NID=21h) supports this parameter.
Table 34. Verb – Get Connection Select Control (Verb ID=F01h) 7:0 Connection Index Current Settings (Default Value is 00h). 7:0 Connection Index Current Settings (Default Value is 00h). 7:0 Connection Index Current Settings (Default Value is 00h). 31:0 Not Supported (Returns 00000000h). Table 35. Verb – Set Connection Select (Verb ID=701h)
Table 36. Verb – Get Connection List Entry (Verb ID=F02h) 31:8 Connection List Entry (N+3), (N+2), and (N+1). 7:0 Connection List Entry (N). Returns 23h (Sum Widget) for N=0~3. 15:8 Connection List Entry (N+3), (N+2), and (N+1). 7:0 Connection List Entry (N). Returns 22h (Sum Widget) for N=0~3. 31:8 Connection List Entry (N+3), (N+2), and (N+1). 7:0 Connection List Entry (N). Returns 1Fh (SPDIF-IN Pin Widget) for N=0~3.
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 37 Track ID: JATR-2265-11 Rev. 1.2 Codec Response for NID=0Bh (Mixer) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 15h (Pin Complex-SURR) for N=4~7. Returns 00h for N>7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 00h for N>7. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7. Returns 17h (Pin Complex – SIDESURR) for N=8~11. Returns 00h for N>11. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 1Ch (Pin Complex – CD) for N=4~7. Returns 16h (Pin Complex – CEN/LFE) for N=8~11. Returns 00h for N>11. Codec Response for NID=0Ch (Front Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 02h (Front DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Dh (Surround Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3.
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 38 Track ID: JATR-2265-11 Rev. 1.2 Codec Response for NID=0Eh (Cen/LFE Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 04h (Cen/LFE DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Fh (Side-Surr Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 05h (Front DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=26h (Fout Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 25h (Fout1 DAC) for N=0~3. Returns 00h for N>3.
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 39 Track ID: JATR-2265-11 Rev. 1.2 Codec Response for NID=14h (Port-D) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3. Returns 00h for N>3. Codec Response for NID=15h (Port-A) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for N>3. Codec Response for NID=16h (Port-G) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3.
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 40 Track ID: JATR-2265-11 Rev. 1.2 Codec Response for NID=17h (Port-H) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Fh (Sum Widget NID=0Fh) for N=0~3. Returns 00h for N>3. Codec Response for NID=18h~1Bh (Port-B/C/E/F) Bit Description 31:24 Connection List Entry (N+3). Returns 0Fh (Sum Widget NID=0Fh) for N=0~3. Returns 00h for n>3. 23:16 Connection List Entry (N+2). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3. 15:8 Connection List Entry (N+1). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3. Returns 26h (Sum Widget NID=26h) for N=4~7. Returns 00h for N>7. Codec Response for NID=1Eh (Pin Widget: SPDIF-OUT) Bit Description 31:16 Connection List Entry (N+3) and (N+2). Returns 0000h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 06h (SPDIF-OUT converter) for N=0~3. Returns 00h for N>3.
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 41 Track ID: JATR-2265-11 Rev. 1.2 Codec Response for NID=11h (Pin Widget: SPDIF-OUT2) Bit Description 31:16 Connection List Entry (N+3) and (N+2). Returns 0000h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 10h (SPDIF-OUT2 converter) for N=0~3. Returns 00h for N>3. Codec Response for NID=22h (Sum Widget before ADC 09h) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 15h (Pin Complex-SURR) for N=4~7. Returns 12h for N=8~11. Returns 00h for N>11. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 0Bh (Sum Widget) for N=8~11. Returns 00h for N>11. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7. Returns 17h (Pin Complex – SIDESURR) for N=8~11. Returns 00h for N>11. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 1Ch (Pin Complex – CD) for N=4~7. Returns 16h (Pin Complex – CEN/LFE) for N=8~11. Returns 00h for N>11.
31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 15h (Pin Complex-SURR) for N=4~7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 0Bh (Sum Widget) for N=8~11. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7. Returns 17h (Pin Complex – SIDESURR) for N=8~11. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 1Ch (Pin Complex – CD) for N=4~7. Returns 16h (Pin Complex – CEN/LFE) for N=8~11. 31:0 Not Supported (Returns 00000000h). Table 37. Verb – Get Processing State (Verb ID=F03h) 31:0 Not Supported (Returns 00000000h).
Table 38. Verb – Set Processing State (Verb ID=703h) Table 39. Verb – Get Coefficient Index (Verb ID=Dh) 31:16 Reserved. Read as 0’s. 31:0 Not Supported (Returns 00000000h). Table 40. Verb – Set Coefficient Index (Verb ID=5h)
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch) 31:16 Reserved. Read as 0’s. 15:0 Processing Coefficient. 31:0 Not Supported (Returns 00000000h). Table 42. Verb – Set Processing Coefficient (Verb ID=4h)
This verb is used to get gain/attenuation settings from each widget. Table 43. Verb – Get Amplifier Gain (Verb ID=Bh) 3:0 Index[3:0] for Input Source. Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored. 7 Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Mute. Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0]. 7-bit step value (0~46) specifying the volume from –16dB~+30dB in 1.0dB steps. Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute). 7 Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Mute. Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps. Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute).
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 46 Track ID: JATR-2265-11 Rev. 1.2 Codec Response for NID=0Ch~0Fh and 26h (Sum Widget: Front, Surr, Cen/LFE, SIDESURR Sum, Fout) Bit Description 31:8 0’s. 7 Bit 15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Mute. 0: Unmute 1: Mute Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit 15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain). Bit 15 is 1 in ‘Get Amplifier Gain’. Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the volume from –64dB~0dB in 1.0dB steps. Codec Response for NID=02h ~ 05h and 25h (DAC Widget: Front, Surr, Cen/LFE, SIDESURR, Fout DAC) Bit Description 31:8 0’s. 7 Bit 15 is 0 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute). Bit 15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute). 6:0 Bit 15 is 0 in ‘Get Amplifier Gain. Read as 0’s (No Output Amplifier Mute). Bit 15 is 1 in ‘Get Amplifier Gain. Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the volume from –64dB~0dB in 1dB steps. Codec Response for NID=14h~17h (Pin Complex: Front/Surr/CenLFE/SIDESURR) Bit Description 31:8 0’s. 7 Bit 15 is 0 in ‘Get Amplifier Gain’. Read as 0. Bit 15 is 1 in ‘Get Amplifier Gain’. Output Amplifier Mute. 0: Unmute 1: Mute (NID=14h~17h, Default=1) 6:0 Bit 15 is 0 in ‘Get Amplifier Gain’. Read as 0’s. Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain). Codec Response for NID=18h~1Bh (Pin Complex: MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0’s. 7 Bit 15 is 0 in ‘Get Amplifier Gain. Read as 0. Bit 15 is 1 in ‘Get Amplifier Gain. Output Amplifier Mute: 0: Unmute 1: Mute (NID=18h~1Bh, Default=1) 6:0 Bit 15 is 0 in ‘Get Amplifier Gain. Input Amplifier Gain [6:0]. 7-bit step value (0~3) specifying the volume from 0dB~30dB in 10dB steps. Bit 15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Gain).
Bit 15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute). 6:0 Bit 15 is 0 in ‘Get Amplifier Gain. Read as 0 (No Input Amplifier Gain). Bit 15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Input Amplifier Gain). 31:0 Not Supported (Returns 00000000h). This verb is used to set amplifier gain/attenuation in each widget. Table 44. Verb – Set Amplifier Gain (Verb ID=3h) ‘1’ indicates output amplifier gain will be set. ‘1’ indicates input amplifier gain will be set. ‘1’ indicates left amplifier gain will be set. ‘1’ indicates right amplifier gain will be set. 11:8 Index Offset (for Input Amplifiers on Sum Widgets and Selector Widgets). A 7-bit step value specifying the amplifier gain.
Table 45. Verb – Get Converter Format (Verb ID=Ah) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV).
Table 46. Verb – Set Converter Format (Verb ID=2h) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV).
Table 47. Verb – Get Power State (Verb ID=F05h) 5:4 PS-Act. Actual Power State [1:0]. (NID=01h), PS-Act is always equal to PS-Set. 1:0 PS-Set. Set Power State [1:0]. PS-Set controls the current power setting of the referenced node. 31:0 Not Supported (Returns 00000000h). Table 48. Verb – Set Power State (Verb ID=705h) 5:4 PS-Act. Actual Power State [1:0]. PS-Act indicates the actual power state of the referenced node. 1:0 PS-Set. Set Power State [1:0].
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 31:0 Not Supported (Returns 00000000h). Table 50. Verb – Set Converter Stream, Channel (Verb ID=706h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. (NID=08h~0Ah). Other widgets will ignore this verb.
Table 51. Verb – Get Pin Widget Control (Verb ID=F07h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O Unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O Unit). 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O Unit). 2:0 VrefEn (Vrefout Enable Control). 31:0 Not Supported (Returns 00000000h).
Table 52. Verb – Set Pin Widget Control (Verb ID=707h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O Unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O Unit). 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O Unit). 2:0 VrefEn (Vrefout Enable Control). unsolicited response to inform software of a real-time event. Table 53. Verb – Get Unsolicited Response Control (Verb ID=F08h) 7 Unsolicited Response is Enabled. 3:0 Assigned Tag for Unsolicited Response. The tag[3:0] is assigned by software to determine which widget generates unsolicited responses. 31:0 Not Supported (Returns 00000000h).
Enables a widget to generate an unsolicited response. Table 54. Verb – Set Unsolicited Response Control (Verb ID=708h) 7 Enable Unsolicited Response. 3:0 Tag for Unsolicited Response. Returns the Presence Detect status and the impedance of a device attached to the pin. Table 55. Verb – Get Pin Sense (Verb ID=F09h) The ALC888S-VD does not support hardware impedance detection. This field is read as 0s. 31:0 Not Supported (Returns 00000000h).
Table 56. Verb – Execute Pin Sense (Verb ID=709h) 0 Right (Ring) Channel Select. The ALC888S-VD does not support hardware impedance sensing and will ignore this control. Table 57. Verb – Get Volume Knob (Verb ID=F0Fh) 1: The volume generated by external HW volume control will directly affect the volume of the amplifier. Note: The ALC888S-VD does not support Volume Knob Widget and will ignore this verb and respond with 0’ s.
Table 58. Verb – Set Volume Knob (Verb ID=70Fh) 1: The volume generated by external HW volume control will directly affect the volume of the amplifier. Note: The ALC888S-VD does not support Volume Knob Widget and will ignore this verb and respond with 0’ s.
Reads the 32-bit sticky register for each Pin Widget configured by software. Table 59. Verb – Get Configuration Default (Verb ID=F1Ch) 31:0 32-Bit Configuration Information for Each Pin Widget. Default value for each pin widget.
Table 60. Default Configuration in Chip (14h~1Ch) Table 61. Default Configuration in Chip (1Dh~12h)
1Eh, and 1Fh, e.g., placement and expected default device. Table 62. Verb – Set Configuration Default Bytes 0, 1, 2, 3 (SPDIF-IN), 11h (SPDIF-OUT2), and 12h (Digital MIC). Other widgets will ignore this verb. Table 63. Verb – Get BEEP Generator (Verb ID= F0Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255×4)=47Hz. The highest tone is 48kHz/(1×4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Table 64. Verb – Set BEEP Generator (Verb ID= 70Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255×4)=47Hz. The highest tone is 48kHz/(1×4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 65. Verb – Get GPIO Data (Verb ID= F15h) 7:3 GPIO[7:2] Data. Not supported in the ALC888S-VD. The value written (output) or sensed (input) on the corresponding pin if it is enabled.
Table 66. Verb – Set GPIO Data (Verb ID= 715h) 7:3 GPIO[7:2] Output Data. Not supported in the ALC888S-VD. The value written determines the value driven on a pin that is configured as an output pin. Table 67. Verb – Get GPIO Enable Mask (Verb ID= F16h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 68. Verb – Set GPIO Enable Mask (Verb ID=716h) 7:3 GPIO[7:2] Enable Mask. Not supported in the ALC888S-VD. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 69. Verb – Get GPIO Direction (Verb ID=F17h) 7:3 GPIO[7:2] Direction Control. Not supported in the ALC888S-VD. 2:0 GPIO[1:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 70. Verb – Set GPIO Direction (Verb ID=717h) 7:3 GPIO[7:2] Direction Control. Not supported in the ALC888S-VD. 2:0 GPIO[1:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 71. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) 7:3 GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC888S-VD. 2:0 GPIO[1:0] Unsolicited Enable Mask. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 72. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) 7:3 GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC888S-VD. 2:0 GPIO[1:0] Unsolicited Enable Mask. Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled. Table 73. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets in the ALC888S-VD to return to their power on default state.
Table 74. Verb – Get Digital Converter Control 1, 2, 3, 4 (Verb ID=F0Dh, F0Eh, F3Eh, F3Fh) 22:20 Reserved. Read as 0’s. Not supported in ALC888S-VD, read as 0’s. 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (Control V Bit and Data in Sub-Frame). 1 V for Validity Control (Control V Bit and Data in Sub-Frame). 31:15 Reserved. Read as 0’s. 14:8 CC[6:0] (Category Code).
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 66 Track ID: JATR-2265-11 Rev. 1.2 NID=0Ah (SPDIF-IN) Response to ‘Get verb’ - F0Dh/F0Eh Bit Description (part of SPDIF-IN Channel Status) 7 LEVEL (Generation Level). 6 PRO (Professional or Consumer Format). 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data Type). 0: PCM data 1: AC3 or other digital non-audio data 4 COPY (Copyright). 0: Asserted 1: Not asserted 3 PRE (Pre-Emphasis). 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 Reserved. 1 Invalid. V Bit in Sub-Frame of SPDIF-IN. 0: Data X and Y are valid, or SPDIF-IN is not locked 1: At least one of data X and Y is invalid 0 Digital Enable (DigEn). 0: OFF 1: ON Codec Response for Other NID Bit Description 31:0 0’s.
Table 75. Verb – Set Digital Converter Control 1, 2, 3, 4 (Verb ID=70Dh, 70Eh, 73Eh, 73Fh) 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (Control V Bit and Data in Sub-Frame). 1 V for Validity Control (Control V Bit and Data in Sub-Frame). 6:0 CC[6:0] (Category Code).
Note: Other widgets will ignore this verb. Table 76. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) 31:16 Subsystem ID[23:8] (Default=10ECh). 15:8 Subsystem ID[7:0] (Default=08h). 7:0 Assembly ID[7:0] (Default=88h).
Table 77. Verb – Set Subsystem ID [31:0] Table 78. Verb – Get EAPD Control (Verb ID=F0Ch) 2 L-R Swap. The ALC888S-VD does not support swapping left and right channels. Read as 0. 0 Bridge Tied Load (BTL) Enable. The ALC888S-VD does not support BTL output. Read as 0.
Table 79. Verb – Set EAPD Co ntrol (Verb ID=70Ch for Set) 7:3 Reserved. Written Data is Ignored. 2 L-R Swap. The ALC888S-VD does not support swapping left and right channels, written data is ignored. 0 Bridge Tied Load (BTL) Enable. The ALC888S-VD do es not support BTL output. Written data is ignored.
- Electrical Characteristics
Table 80. Absolute Maximum Ratings *: The digital link power DVDD-IO must be lower than the digital core power DVDD. AVDD should contact Realtek technical support representatives for special testing support. DVDD-IO= 1.5V±5%/3.3V±5%, DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load. Table 81. Threshold Voltage
Table 82. Digital Filter Characteristics DVDD=3.3V, Tambient=25°C, with 75Ω external load. Table 83. SPDIF Input/Output Characteristics
Table 84. Link Reset and Initialization Timing
4 BCLK 4 BCLK >= 4 BCLK
Figure 15. Link Reset and Initialization Timing
Table 85. Link Timing Parameters at the Codec Figure 16. Link Signals Timing
Table 86. SPDIF Output and Input Timing Note 1: Bit parameters for 48kHz sample rate of SPDIF-OUT. Note 2: Bit parameters for 48kHz sample rate of SPDIF-IN. Figure 17. Output and Input Timing The ALC888S-VD does not support test mode or Automatic Test Equipment (ATE) mode.
- 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
- 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 87. Analog Performance
(www.realtek.com) without modifying this datasheet. the rear panel, and with two re-tasking analog jacks on the front panel. Table 88. Desktop System FRONT (Port-D) 35, 36 Rear Panel Front Channel Line Output and Amplified Output. SURR (Port-A) 39, 41 Rear Panel Surround Channel Line Output. CENTER/LFE (Port-G) 43, 44 Rear Panel Center and Low Frequency (Sub-Woofer) Channel Line Output. SIDE (Port-H) 45, 46 Rear Panel Side Surround Channel Line Output. MIC1 (Port-B) 21, 22 Rear Panel Analog Microphone Input. LINE1 (Port-C) 23, 24 Rear Panel Analog Line Input.
Figure 18. Filter Connection
Figure 19. Front Panel Header and Front Panel Module Connection
power off transition stages. Table 89 shows the DC bias state when Standby mode is enabled. Table 89. Standby Mode
7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 83 Track ID: JATR-2265-11 Rev. 1.2 12. Mechanical Dimensions L MILLIMETER INCH SYMBOL MIN TYP MAX MIN TYP MAX A1 0.05 - 0.15 0.002 - 0.006 c 0.09 - 0.20 0.004 - 0.008 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 E 9.00 BSC 0.354 BSC E1 7.00BSC 0.276 BSC E2 5.50 0.217 e 0.50 BSC 0.0196 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm LEADFRAME MATERIAL DOC. NO. APPROVE VERSION 02 DWG NO. PKGC-065 CHECK DATE REALTEK SEMICONDUCTOR CORP.
Table 90. Ordering Information Note: See page 7 for ‘Green’ package and version identification.