ALC888H-GR

ALC888 REALTEK | Alldatasheet

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(ALC888-GR, ALC888DD-GR, ALC888H-GR, ALC888-VA2-GR, ALC888-VC2-GR) 7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC DATASHEET Rev. 1.4

07 April 2008

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

7.1+2 Channel High Definition Audio Codec ii Track ID: JATR-1076-21 Rev. 1.4 COPYRIGHT ©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC888 Audio Codec ICs. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2006/4/25 First release. 1.1 2007/2/5 Update section 12 Ordering Information, page 72. Correct ADC support data in section 2.1 Hardware Features, page 2. 1.2 2007/3/6 Add part ALC888-V A2-GR in section 12 Ordering Information, page 72. 1.3 2007/11/21 Add part ALC888-VC-GR in section 12 Ordering Information, page 72. 1.4 2008/04/07 Update ALC888 version C part numbe r in section 12 Ordering Information, page 72.

7.1+2 Channel High Definition Audio Codec iii Track ID: JATR-1076-21 Rev. 1.4 Table of Contents

7.1+2 Channel High Definition Audio Codec iv Track ID: JATR-1076-21 Rev. 1.4 8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 51 8.41. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR

7.1+2 Channel High Definition Audio Codec v Track ID: JATR-1076-21 Rev. 1.4

TABLE 57. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 51 TABLE 72. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR

7.1+2 Channel High Definition Audio Codec 1 Track ID: JATR-1076-21 Rev. 1.4 1. General Description The ALC888 audio codecs are high-performance 7.1+2 Channel High Definition audio codecs providing ten DAC channels that simultaneously support 7.1 sound playback, plus 2 channels of independent stereo sound output (multiple streaming) through the front panel stereo outputs. The ALC888 integrates two stereo ADCs that can support a stereo microphone, and feature Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology. The ALC888 audio codecs incorporates Realtek proprietary converter technology to achieve good playback and recording quality, and meets the latest WLP3.10 (Windows Logo Program) requirements. The ALC888-VC meets requirements in the future Windows Logo Program (WLP), which will be effective from 01 June 2008. The ALC888-VC conforms to Intel’s Audio Codec low power state white paper and is ECR compliant. The enhanced functions and new features are listed in section 2.2 ALC888-VC-GR Specific Features, page 3. All analog IO are input and output capable, and headphone amplifiers are also integrated at each analog output. All analog IOs can be re-tasked according to user’s definitions, or automatically switched depending on the connected device type. Support for 16/20/24-bit S/DPIF input and output functions with sampling rate of up to 192kHz, offers easy connection of PCs to high-quality consumer electronic products such as digital decoders and mini disk device. The ALC888 audio codecs support host audio controller from the Intel ICH series chipset, and also from any other HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent software utilities like environment sound emulation, multiple bands of software equalizer and dynamic range control, optional Dolby ® Digital Live, DTS® CONNECT™, and Dolby ® Home Theater programs, the ALC888 audio codecs provides an excellent home entertainment package and game experience for PC users. Note: ALC888 model differences are listed in section 12 Ordering Information, page 72.

7.1+2 Channel High Definition Audio Codec 2 Track ID: JATR-1076-21 Rev. 1.4 2. Features 2.1. Hardware Features „ High-performance DACs with 97dB SNR (A-Weighting), ADCs with 90dB SNR (A-Weighting) „ Meets premium performance requirements for Microsoft WLP 3.10 „ ALC888 Ver.C meets future WLP performance requirements (effective from 01 June 2008) „ Ten DAC channels support 7.1 sound playback, plus 2 channels of independent stereo sound output (multiple streaming) through the front panel output „ Two stereo ADCs support one stereo microphone and one legacy mixer recording simultaneously „ All DACs support independent 16/20/24-bit, 44.1k/48k/96k/192kHz sample rate „ All ADCs support independent 16/20-bit, 44.1k/48k/96k sample rate „ All ADCs support independent 16/20/24-btt, 44.1k/48k/96k/192kHz sample rate (ALC888 Ver.C) „ 16/20/24-bit S/PDIF-OUT supports 44.1k/48k/96k/192kHz sample rate „ 16/20/24-bit S/PDIF-OUT supports 44.1k/48k/88.2k/96k/192kHz sample rate (ALC888 Ver.C) „ 16/20/24-bit S/PDIF-IN supports 44.1k/48k/96k/192kHz sample rate „ Up to four channels of microphone array input are supported for AEC/BF application „ High-quality analog differential CD input „ Supports external PCBEEP input and built-in digital BEEP generator „ Software selectable 2.5V/3.75V VREFOUT „ Two jack detection pins each designed to detect up to 4 jacks „ Supports legacy analog mixer architecture „ Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain „ Software selectable boost gain (+10/+20/+30dB) for analog microphone input „ All analog jacks are stereo input and output re-tasking for analog plug & play „ Built-in headphone amplifiers for each re-tasking jack

7.1+2 Channel High Definition Audio Codec 3 Track ID: JATR-1076-21 Rev. 1.4 „ Two GPIOs (General Purpose Input and Output) for customized applications „ Supports anti-pop mode when analog power AVDD is on and digital power is off. „ Supports stereo digital microphone interface for improved voice quality „ 48-pin LQFP ‘Green’ package 2.2. ALC888-VC-GR Specific Features „ Integrated high-pass filter to cancel DC offset generated from digital microphone „ Supports low voltage IO (1.5V~3.3V) for HDA Link „ Intel low power ECR compliant, supports power status control for each analog converter and pin widget, supports jack detection and wake-up event in D3 mode „ PCBEEP pass-through function is supported when the ALC888 version C is in D3 mode 2.3. Software Features „ Meets Microsoft WLP 3.10 and future WLP audio requirements „ WaveRT-based audio function driver for Windows Vista „ EAX™ 1.0 & 2.0 compatible „ Direct Sound 3D™ compatible „ A3D™ compatible „ I3DL2 compatible „ Emulation of 26 sound environments to enhance gaming experience „ Multi-band software equalizer and related tools are provided „ Voice Cancellation and Key Shifting effect „ Dynamic range control (expander, compressor and limiter) with adjustable parameters „ Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience „ Provides 10-foot GUI for easy menu navigation on Windows Media Center

7.1+2 Channel High Definition Audio Codec 4 Track ID: JATR-1076-21 Rev. 1.4 „ Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application „ Smart multiple streaming operation „ HDMI audio driver for AMD platform „ Dolby® PCEE program™ (optional software feature) „ DTS® CONNECT™ (optional software feature) „ SRS® TrueSurround HD (optional software feature) „ Fortemedia® SAM™ technology for voice processi ng (Beam Forming and Acoustic Echo Cancellation) (optional software feature) „ Creative® Host Audio program (optional software feature) „ Voice recognition and Realtek proprietary API (SkyTel) is supported (Optional software feature) 3. System Applications „ Desktop multimedia PCs „ Notebook PCs „ Information appliances (IA) e.g., set-top box

Figure 1. Block Diagram

Pin Complex widgets NID=14h~1Bh are re-tasking IOs. Figure 2. Analog Input/Output Unit

Figure 3. Pin Assignments ‘0’, which is the first stepping of the ALC888-VC.

Table 1. Digital I/O Pins Table 2. Analog I/O Pins

Table 3. Filter/Reference/NC Table 4. Power/Ground

1. High Definition Audio Link Protocol

with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol. Figure 4. HDA Link Protocol

Table 5. Link Signal Definitions BCLK 24.0MHz bit clock sourced from the HDA controller and connecting to all codecs. controller and connects to all codecs. least one SDO. To extend outbound bandwidth, multiple SDOs may be supported. rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID. HDA controller and connects to all codecs. Table 6. HDA Signal Definitions Figure 5. Bit Timing

the data stream is always carried on SDO0, the second bit on SDO1 and so forth. is always transmitted on SDO0, and copied on SDO1. Figure 9. Striped Stream on Multiple SDOs

Figure 12. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz. blocks are transmitted every 160 frames. rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence AND interleave n empty frames. AND interleave an empty frame between non-empty frames (Table 9, page 18).

Table 7. Defined Sample Rate and Transmission Rate Table 8. 48kHz Variable Rate of Delivery Timing

Table 9. 44.1kHz Variable Rate of Delivery Timing

7.1+2 Channel High Definition Audio Codec 19 Track ID: JATR-1076-21 Rev. 1.4 7.3. Reset and Initialization There are two types of reset within an HDA link:

• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events: 1. Link Reset 2. Codec Reset 3. Codec changes its power state (for example, hot docking a codec to an HDA system) 7.3.1. Link Reset A link reset may be caused by 3 events: 1. The HDA controller asserts RST# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA controller 3. Software initiates power management sequences. Figure 13, page 20, shows the ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v) Enter ‘Link Reset’: n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state r All link signals driven by controller and codecs should be tri-state by internal pull low resistors

4 BCLK 4 BCLK

Figure 13. Link Reset Timing

Figure 14. Codec Initialization Sequence

controls parameters in the codec. Table 10. 40-Bit Commands in 4-Bit Verb Format Table 11. 40-Bit Commands in 12-Bit Verb Format software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 12. Solicited Response Format Table 13. Unsolicited Response Format

the System Power State Definitions. Note that only the ALC888-VC supports Wake-Up events when in low power mode. states depending on system configuration. Table 14. System Power State Definitions D0 All power on. Individual DACs and ADCs can be powered up or down as required. reference is off (D1 + analog reference off). D3 (Hot) Power still supplied. The codec stops the internal clock. State is maintained. D3 (Cold) All power removed. State lost. Table 15. Power Controls in NID 01h

Table 16. Powered Down Conditions

1. Exit latency (D3 to D0 transfer) < 10ms.
2. Audio pop/click suppression during D3 and D0 transition < -65dBV.
3. Supports Jack detection in D3 state.
4. D3 functions with or without the BITCLK

no BITCLK is present, the ALC888-VC drives the SDI high in order to wake up the system.

1. Supported Verbs and Parameters

not supported by the addressed widget, it will respond with 32 bits of ‘0’. page 22, to get detailed information about supported parameters. Table 17. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) Note: The Root Node (NID=00h) supports this parameter. Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 00h is for ALC888 version A, 01h is for ALC888 version B, 02h is for ALC888-VC, etc. Note: The Root Node (NID=00h in the ALC888) supports this parameter.

associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) Note: The Audio Function Group (NID=01h) supports this parameter.

Table 22. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h) 31:17 Reserved. Read as 0’s. 16 Beep Generator. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0’s. Note: The Audio Function Group (NID=01h) supports this parameter. Table 23. Parameter – Audi o Widget Capabilities (Verb ID=F00h, Parameter ID=09h) 31:24 Reserved. Read as 0’s. 19:16 Delay. Samples delayed between the HDA link and widgets. 15:11 Reserved. Read as 0’s. 8 ConnList. Connection List. 7 UnsolCap. Unsolicited Capable. 6 ProcWidget. Processing Widget. 3 AmpParOvr, AMP Param Override. 2 OutAmpPre. Out AMP Present.

parameters to provide supported formats if their ‘Format Override’ bit is set. Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) 31:21 Reserved. Read as 0’s. 20 B32. 32-Bit Audio Format Support. 19 B24. 24-Bit Audio Format Support. 18 B20. 20-Bit Audio Format Support. 17 B16. 16-Bit Audio Format Support. 16 B8. 24-Bit Audio Format Support. 15:12 Reserved. Read as 0’s. 11 R12. 384kHz (=8*48kHz) Rate Support. 10 R11. 192kHz (=4*48kHz) Rate Support. 8 R9. 96kHz (=2*48kHz) Rate Support. 7 R8. 88.2kHz (=2*44.1kHz) Rate Support. 4 R5. 32kHz (=2/3*48kHz) Rate Support. 2 R3. 16kHz (=1/3*48kHz) Rate Support. 0 R1. 8kHz (=1/6*48kHz) Rate Support.

have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Note: Input converters and output converters support this parameter. The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 26. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch) 31:16 Reserved. Read as 0’s. specified as a percentage of A VDD. 7 L-R Swap. Indicates the capability of swapping the left and rights. 6 Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins. 5 Input Capable. ‘1’ indicates this pin complex supports input. 4 Output Capable. ‘1’ indicates this pin complex supports output. 3 Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone. 2 Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in. 1 Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement. ‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type. Note: Only Pin Complex widgets support this parameter.

their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 27. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. Indicates which step is 0dB. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 28. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 6:0 Offset. Indicates which step is 0dB.

Parameters in this node provide audio function widget connection information. Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) input, and there is no Connection Select Control (not a MUX widget). Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) Table 31. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h) 31:16 Reserved. Read as 0’s. 15:8 NumCoeff. Number of Coefficient.

Table 32. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h) Only the ALC888-VC-GR supports GPIO wake up functions. The ALC888 supports GPIO unsolicited response. 29:24 Reserved. Read as 0’s. Three GPIO pins are supported. Table 33. Parameter – Volume Knob Capab ilities (Verb ID=F00h, Parameter ID=13h) Note: The ALC888 does not support volume knob and will respond with 0s to this parameter.

Table 34. Verb – Get Connection Select Control (Verb ID=F01h) 7:0 Connection Index Currently Set (Default value is 00h). 7:0 Connection Index Currently Set (Default value is 00h). 31:0 Not Supported (returns 00000000h). Table 35. Verb – Set Connection Select (Verb ID=701h)

Table 36. Verb – Get Connection List Entry (Verb ID=F02h) 31:8 Connection List Entry (N+3), (N+2) and (N+1). 7:0 Connection List Entry (N). Returns 23h (Sum Widget) for N=0~3. Returns 00h for N>3. 15:8 Connection List Entry (N+3), (N+2) and (N+1). 7:0 Connection List Entry (N). Returns 22h (Sum Widget) for N=0~3. Returns 00h for N>3. 31:8 Connection List Entry (N+3), (N+2) and (N+1). 7:0 Connection List Entry (N). Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3. Returns 00h for N>3. 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 15h (Pin Complex-SURR) for N=4~7. Returns 00h for N>7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 00h for N>7. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7. Returns 17h (Pin Complex – SIDESURR) for N=8~11. Returns 00h for N>11. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 1Ch (Pin Complex – CD) for N=4~7. Returns 16h (Pin Complex – CEN/LFE) for N=8~11. Returns 00h for N>11.

7.1+2 Channel High Definition Audio Codec 35 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=0Ch (Front Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 02h (Front DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Dh (Surround Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Eh (Cen/LFE Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 04h (Cen/LFE DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Fh (Side-Surr Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 05h (Front DAC) for N=0~3. Returns 00h for N>3.

7.1+2 Channel High Definition Audio Codec 36 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=26h (Fout Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 25h (Fout1 DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=14h~1Bh (Port-A to port-H) Bit Description 31:24 Connection List Entry (N+3). Returns 0Fh (Sum Widget NID=0Fh) for N=0~3. Returns 00h for n>3. 23:16 Connection List Entry (N+2). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3. 15:8 Connection List Entry (N+1). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3. Returns 26h (Sum Widget NID=26h) for N=4~7. Returns 00h for N>7. Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT) Bit Description 31:16 Connection List Entry (N+3) and (N+2). Returns 0000h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 06h (S/PDIF-OUT converter) for N=0~3. Returns 00h for N>3. Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 15h (Pin Complex-SURR) for N=4~7. Returns 00h for N>7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 0Bh (Sum Widget) for N=8~11. Returns 00h for N>11.

15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7. Returns 17h (Pin Complex – SIDESURR) for N=8~11. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 1Ch (Pin Complex – CD) for N=4~7. Returns 16h (Pin Complex – CEN/LFE) for N=8~11. 31:0 Not Supported (returns 00000000h). Table 37. Verb – Get Processing State (Verb ID=F03h) 31:0 Not Supported (returns 00000000h). Table 38. Verb – Set Processing State (Verb ID=703h)

Table 39. Verb – Get Coefficient Index (Verb ID=Dh) 31:16 Reserved. Read as 0’s. 31:0 Not Supported (returns 00000000h). Table 40. Verb – Set Coefficient Index (Verb ID=5h)

Table 41. Verb – Get Processing Coefficient (Verb ID=Ch) 31:16 Reserved. Read as 0’s. 15:0 Processing Coefficient. 31:0 Not Supported (returns 00000000h). Table 42. Verb – Set Processing Coefficient (Verb ID=4h)

This verb is used to get gain/attenuation settings from each widget. Table 43. Verb – Get Amplifier Gain (Verb ID=Bh) 3:0 Index[3:0] for Input Source. Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored. 7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –16.5B~+30dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute). 7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).

7.1+2 Channel High Definition Audio Codec 41 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, Cen/LFE, SIDESURR Sum) Bit Description 31:8 0’s. 7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –46.5dB~0dB in 1.5dB steps. Codec Response for NID=14h~1Bh (Pin Complex: Front/Surr/CenLFE/SIDESURR/MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0’s. 7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0:Unmute 1:Mute (NID=14h~1Bh,Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0’s. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). Codec Response to Other NID Bit Description 31:0 Not Supported (returns 00000000h).

This verb is used to set amplifier gain/attenuation in each widget. Table 44. Verb – Set Amplifier Gain (Verb ID=3h) 1: Indicates output amplifier gain will be set. 1: Indicates input amplifier gain will be set. 1: Indicates left amplifier gain will be set. 1: Indicates right amplifier gain will be set. 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets). A 7-bit step value specifying the amplifier gain.

Table 45. Verb – Get Converter Format (Verb ID=Ah) Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC, S/PDIF-OUT). 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV). The ALC888 does not support Divisor. Always read as 000b. 31:0 Not Supported (returns 00000000h).

Table 46. Verb – Set Converter Format (Verb ID=2h) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV).

Table 47. Verb – Get Power State (Verb ID=F05h) 5:4 PS-Act. Actual Power State [1:0]. (NID=01h), PS-Act is always equal to PS-Set. 1:0 PS-Set. Set Power State [1:0]. PS-Set controls the current power setting of the referenced node. 31:0 Not Supported (returns 00000000h). Table 48. Verb – Set Power State (Verb ID=705h) 5:4 PS-Act. Actual Power State [1:0]. PS-Act indicates the actual power state of the referenced node. 1:0 PS-Set. Set Power State [1:0].

Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 31:0 Not Supported (returns 00000000h). Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. (NID=08h~0Ah). Other widgets will ignore this verb.

Table 50. Verb – Get Pin Widget Control (Verb ID=F07h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit). 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit). 2:0 VrefEn (Vrefout Enable Control). 31:0 Not Supported (returns 00000000h).

Table 51. Verb – Set Pin Widget Control (Verb ID=707h) ‘Pin Control’ in command [7:0] for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 1Fh. 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit). 2:0 VrefEn (Vrefout Enable Control).

unsolicited response to inform software of a real-time event. Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h) 7 Unsolicited Response is Enabled. 3:0 Assigned Tag for Unsolicited Response. The tag[3:0] is assigned by software to determine which widget generates unsolicited responses. 31:0 Not Supported (returns 00000000h). Enables a widget to generate an unsolicited response. Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h) 7 Enable Unsolicited Response. 3:0 Tag for Unsolicited Response.

Returns the Presence Detect status and the impedance of a device attached to the pin. Table 54. Verb – Get Pin Sense (Verb ID=F09h) The ALC888 does not support hardware impedance detection. This field is read as 0s. 31:0 Not Supported (returns 00000000h). Table 55. Verb – Execute Pin Sense (Verb ID=709h) 0 Right (Ring) Channel Select. The ALC888 does not support hardware impedance sensing and will ignore this control.

Reads the 32-bit sticky register for each Pin Widget configured by software. Table 56. Verb – Get Configuration Default (Verb ID=F1Ch) 31:0 32-bit configuration info rmation for each pin widget. 1Eh~1Fh such as placement and expected default device. Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3 Note: Supported by Pin Widget NID=14h~1Bh, 1Eh and 1Fh. Other widgets will ignore this verb.

Table 58. Verb – Get BEEP Generator (Verb ID= F0Ah) times the number specified in F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input. Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah) times the number specified in F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 60. Verb – Get GPIO Data (Verb ID= F15h) 7:3 GPIO[7:3] Data. Not supported in the ALC888. The value written (output) or sensed (input) on the corresponding pin if it is enabled. Table 61. Verb – Set GPIO Data (Verb ID= 715h) 7:3 GPIO[7:3] output Data. Not supported in the ALC888. The value written determines the value driven on a pin that is configured as an output pin.

Table 62. Verb – Get GPIO Enable Mask (Verb ID= F16h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h) 7:3 GPIO[7:3] Enable Mask. Not supported in the ALC888. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 64. Verb – Get GPIO Direction (Verb ID=F17h) 7:3 GPIO[7:3] Direction Control. Not supported in the ALC888. 2:0 GPIO[2:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 65. Verb – Set GPIO Direction (Verb ID=717h) 7:3 GPIO[7:3] Direction Control. Not supported in the ALC888. 2:0 GPIO[2:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) 7:3 GPIO[7:3] Unsolicited Enable Mask. Not supported in the ALC888. 2:0 GPIO[2:0] Unsolicited Enable Mask. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) 7:3 GPIO[7:3] Unsolicited Enable Mask. Not supported in the ALC888. 2:0 GPIO[2:0] Unsolicited Enable Mask. Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled. Table 68. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets in the ALC888 to return to their power on default state.

Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh) 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 31:16 Reserved. Read as 0’s. 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type).

1 In‘V’alid. V bit in sub-frame of S/PDIF-IN. Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame).

6:0 CC[6:0] (Category Code). Note: Other widgets will ignore this verb. Table 71. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)

Table 72. Verb – Set Subsystem ID [31:0] Table 73. Verb – Get/Set EAPD Enable (VID=70Ch/F0Ch) [31:0] 2 L-R Swap. The ALC888 does not support left and right channel swapping. Read as 0. 0 BTL Enable. The ALC888 does not support BTL output. Read as 0.

1. Electrical Characteristics

Table 74. Absolute Maximum Ratings *: The digital link power DVDD-IO must be lower than the digital core power DVDD. AVDD should contact Realtek technical support representatives for special testing support. DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load. Table 75. Threshold Voltage

Table 76. Digital Filter Characteristics DVDD= 3.3V, Tambient=25°C, with 75Ω external load. Table 77. S/PDIF Input/Output Characteristics

Table 78. Link Reset and Initialization Timing

4 BCLK 4 BCLK >= 4 BCLK

Figure 15. Link Reset and Initialization Timing

Table 79. Link Timing Parameters at the Codec Figure 16. Link Signals Timing

Table 80. S/PDIF Output and Input Timing Note 1: Bit parameters for 48kHz sample rate of S/PDIF-OUT. Note 2: Bit parameters for 48kHz sample rate of S/PDIF-IN. Figure 17. Output and Input Timing The ALC888 does not support codec test mode or Automatic Test Equipment (ATE) mode.

• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz

Table 81. Analog Performance

ALC883. A board designed for the ALC888 series or ALC883 can use the ALC888-VC directly. (www.realtek.com.tw) without modifying this datasheet. Figure 18. Filter Connection (ALC888, ALC888-VC, LQFP-48)

compatible with current HD Audio front panel cable. Figure 19. Onboard Front Panel Header Connection

Figure 20. Jack Connection on Rear Panel

45 R258 100

75 R270

Figure 21. S/PDIF Input/Output Connection

7.1+2 Channel High Definition Audio Codec 71 Track ID: JATR-1076-21 Rev. 1.4 11. Mechanical Dimensions L MILLIMETER INCH SYMBOL MIN TYP MAX MIN TYP MAX A1 0.05 - 0.15 0.002 - 0.006 c 0.09 - 0.20 0.004 - 0.008 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 E 9.00 BSC 0.354 BSC E1 7.00BSC 0.276 BSC E2 5.50 0.217 e 0.50 BSC 0.0196 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm LEADFRAME MATERIAL DOC. NO. APPROVE VERSION 02 DWG NO. PKGC-065 CHECK DATE REALTEK SEMICONDUCTOR CORP.

Table 82. Ordering Information Note 1: See page 7 for ‘Green’ package and version identification. sales representatives or agents.