ALC883-GR_07 REALTEK | Alldatasheet
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7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC DATASHEET Rev. 1.3
15 June 2007
Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw ALC883-GR ALC883DD-GR
7.1+2 Channel High Definition Audio Codec ii Track ID: JATR-1076-21 Rev. 1.3 COPYRIGHT ©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC883 Series Audio Codec ICs. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary 1.0 2005/08/02 First release. 1.1 2005/08/22 Update section 2.1 Hardware Features, page 2, section 9.1.1 Absolute Maximum Ratings, page 61, and section Error! Reference source not found. Error! Reference source not found., page Error! Bookmark not defined.. 1.2 2006/04/03 Add a note to section 9.1.1 Absolute Maximum Ratings, page 61. Update Table 4, page 8, and Table 77, page 65. Revised section Error! Reference source not found. Error! Reference source not found., page Error! Bookmark not defined.. 1.3 2007/06/15 Update section 2.1 Hardware Features, page 2 (the ADCs support 16-bit and 20-bit format, and the ALC883 meets WLP3.09 performance requirements).
7.1+2 Channel High Definition Audio Codec iii Track ID: JATR-1076-21 Rev. 1.3 Table of Contents
7.1+2 Channel High Definition Audio Codec iv Track ID: JATR-1076-21 Rev. 1.3 8.26. V ERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR
7.1+2 Channel High Definition Audio Codec v Track ID: JATR-1076-21 Rev. 1.3
Table 28. Parameter – Amplifier Capabilities (V erb ID=F00h, Output Amplifier Parameter ID=12h) ...29
Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3
7.1+2 Channel High Definition Audio Codec 1 Track ID: JATR-1076-21 Rev. 1.3 1. General Description The ALC883* series 7.1+2 Channel High Definition Audio (HDA) codecs are compliant with Microsoft’s UAA (Universal Audio Architecture). The ALC883 series provide 10 DAC channels that simultaneously support 7.1 sound playback, plus 2 channels of independent stereo sound output (multiple streaming) through the front panel stereo output. Flexible mixing, mute, and fine gain control functions provide a complete integrated audio solution for home entertainment PCs. The ALC883 series also integrates two stereo ADCs that can support a stereo microphone with Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously. All analog IOs are input and output capable, and headphone amplifiers are also integrated at each analog output. All analog IOs can be re-tasked according to user’s definitions, or automatically switched depending on the connected device type. The ALC883 supports 16/20/24 S/PDIF input and output to offer easy connection of PCs to high quality consumer electronic products such as digital decoders and speakers. The ALC883 series supports host/soft audio from the Intel ICH series chipset, and also from any other HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and renowned software utilities like Karaoke mode, environment emulation, software equalizer, HRTF 3D positional audio, and optional Dolby® Digital Live and DTS® Connect™ , the ALC883 series provides an excellent entertainment package and game experience for PC users. *Note: The ALC883 series covers all products listed in section 12 Ordering Information, page 70.
7.1+2 Channel High Definition Audio Codec 2 Track ID: JATR-1076-21 Rev. 1.3 2. Features 2.1. Hardware Features High-performance DACs with 95dB SNR (A-Weighting), ADCs with 85dB SNR (A-Weighting) Meets performance requirements for Microsoft WLP 3.09 premium desktop and mobile PCs Ten DAC channels support 16/20/24-bit PCM format for 7.1 sound playback, plus 2 channels of independent stereo sound output (multiple streaming) through the front panel output Two stereo ADCs support 16/20-bit PCM format, one for stereo microphone, one for legacy mixer recording All DACs supports 44.1K/48K/96K/192kHz sample rate All ADCs support 44.1K/48K/96K sample rate 16/20/24-bit S/PDIF-OUT supports 44.1K/48K/96/192kHz sample rate 16/20/24-bit S/PDIF-IN supports 44.1K/48K/96 sample rate Up to four channels of microphone array input are supported for AEC/BF application High-quality analog differential CD input Supports external PCBEEP input and built-in digital BEEP generator Software selectable 2.5V/3.75V VREFOUT Two jack detection pins each designed to detect up to 4 jacks Reserve analog mixer architecture for backward compatibility with AC'97 Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain All analog jacks are stereo input and output re-tasking for analog plug & play Built-in headphone amplifiers for each re-tasking jack Two GPIOs (General Purpose Input/Output) for customized applications Pin compatible with the ALC880 and ALC882 Enhanced S/PDIF-IN circuitry ensures compatibility with consumer DVD players 48-pin LQFP ‘Green’ package
7.1+2 Channel High Definition Audio Codec 3 Track ID: JATR-1076-21 Rev. 1.3 2.2. Software Features Meets Microsoft WLP 3.09 audio requirements EAX™ 1.0 & 2.0 compatible Direct Sound 3D™ compatible A3D™ compatible I3DL2 compatible HRTF 3D Positional Audio Emulation of 26 sound environments to enhance gaming experience 10 Band Software Equalizer Voice Cancellation and Key Shifting in Karaoke mode Realtek Media Player Enhanced Configuration Panel to improve user experience Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application ALC883DD-GR features Dolby® Digital Live and DTS® Connect™ 3. System Applications Desktop multimedia PCs Entertainment PCs for digital home application Information appliances (IA) e.g., set-top box
Figure 1. Block Diagram
Pin Complex widgets NID=14h~1Bh are re-tasking IO. Figure 2. Analog Input/Output Unit
24 LINE1-R
Figure 3. Pin Assignments in the location marked ‘VV’.
Table 1. Digital I/O Pins Table 2. Analog I/O Pins
Table 3. Filter/Reference Table 4. Power/Ground
- High Definition Audio Link Protocol
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol. Figure 4. HDA Link Protocol
Table 5. Link Signal Definitions BCLK 24.0MHz bit clock sourced from the HDA controller and connecting to all codecs. controller and connects to all codecs. extend outbound bandwidth, multiple SDOs may be supported. controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported. BCLK. SDI can be driven by the controller to initialize the codec’s ID. controller and connects to all codecs. Table 6. HDA Signal Definitions Figure 5. Bit Timing
stream data is always carried on SDO0, the second bit on SDO1 and so forth. is always transmitted on SDO0, and copied on SDO1. Figure 9. Stripped Stream on Multiple SDOs
Figure 12. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz.
Table 7. Defined Sample Rate and Transmission Rate Table 8. 48kHz Variable Rate of Delivery Timing
Table 9. 44.1kHz Variable Rate of Delivery Timing
7.1+2 Channel High Definition Audio Codec 18 Track ID: JATR-1076-21 Rev. 1.3 7.3. Reset and Initialization There are two types of reset within an HDA link:
- Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
- Codec Reset. Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events: 1). Link Reset 2). Codec Reset 3). Codec changes its power state (for example, hot-docking a codec to an HDA system) 7.3.1. Link Reset A link reset may be caused by 3 events: 1). The HDA controller asserts RST# for any reason (power up, or PCI reset) 2). Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA controller 3). Software initiates power management sequences. Figure 13, page 19, shows the ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v) Enter ‘Link Reset’: n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset o As the controller completes the current frame, it does not signal the normal 8-Bit frame SYNC at the end of the frame p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
4 BCLK 4 BCLK
Figure 13. Link Reset Timing
Figure 14. Codec Initialization Sequence controls parameters in the codec. Table 10. 40-Bit Commands in 4-Bit Verb Format Table 11. 40-Bit Commands in 12-Bit Verb Format
software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 12. Solicited Response Format Table 13. Unsolicited Response Format an unsolicited response was sent. state changes in widgets are driven by software. Table 14 shows the System Power State Definitions. individual power control to supply fine-grained power control. Table 14. System Power State Definitions
Table 15. Power Controls in NID 01h Table 16. Powered Down Conditions
- Supported Verbs and Parameters
verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’. page 20, to get detailed information about supported parameters. Table 17. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) Note: The Root Node (NID=00h) supports this parameter. Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 15:8 Revision ID. The vendor’s revision number. 00h is for the first silicon version, 01h is for the second version, etc. Note: The Root Node (NID=00h in the ALC883 series) supports this parameter.
associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) Note: The Audio Function Group (NID=01h) supports this parameter.
Table 22. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h)
16 Beep Generator
Note: The Audio Function Group (NID=01h) supports this parameter. Table 23. Parameter – Audi o Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
10 Power Control
9 Digital
4 Format Override
3 AmpParOvr, AMP Param Override
0 Stereo
own parameters to provide supported formats if their ‘Format Override’ bit is set. Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
2 AC3
1 Float32
0 PCM
Note: Input converters and output converters support this parameter.
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 26. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch)
6 Balanced I/O Pin
5 Input Capable
4 Output Capable
3 Headphone Drive Capable
2 Presence Detect Capable
1 Trigger Required
0 Impedance Sense Capable
Note: Only Pin Complex widgets support this parameter.
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 27. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 28. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
Parameters in this node provide audio function widget connection information. Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
7 Short Form
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
3 D3Sup
2 D2Sup
1 D1Sup
0 D0Sup
Table 31. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h)
0 Benign
Table 32. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h)
31 GPIWake=0
30 GPIUnsol=1
Table 33. Parameter – Volume Knob Capab ilities (Verb ID=F00h, Parameter ID=13h)
7 Delta
Note: In devices without volume knob support, the ALC883 will respond with 0s to this parameter.
Table 34. Verb – Get Connection Select Control (Verb ID=F01h) Table 35. Verb – Set Connection Select (Verb ID=701h)
Table 36. Verb – Get Connection List Entry (Verb ID=F02h)
7.1+2 Channel High Definition Audio Codec 34 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=0Bh (Mixer) Bit Description 31:24 Connection List Entry (N+3) Returns 1Bh (Pin Complex – LINE2) for N=0~3 Returns 15h (Pin Complex-SURR) for N=4~7 Returns 00h for N>7 23:16 Connection List Entry (N+2) Returns 1Ah (Pin Complex – LINE1) for N=0~3 Returns 14h (Pin Complex – FRONT) for N=4~7 Returns 00h for N>7 15:8 Connection List Entry (N+1) Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 1Dh (Pin Complex – PCBEEP) for N=4~7 Returns 17h (Pin Complex – SIDESURR) for N=8~11 Returns 00h for N>11 7:0 Connection List Entry (N) Returns 18h (Pin Complex – MIC1) for N=0~3 Returns 1Ch (Pin Complex – CD) for N=4~7 Returns 16h (Pin Complex – CEN/LFE) for N=8~11 Returns 00h for N>11 Codec Response for NID=0Ch (Front Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 02h (Front DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID=0Dh (Surround Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3
7.1+2 Channel High Definition Audio Codec 35 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=0Dh (Surround Sum) Bit Description 7:0 Connection List Entry (N) Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Eh (Cen/Lfe Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 04h (Cen/Lfe DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID=0Fh (Side-Surr Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 05h (Front DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID=26h (Fout Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3
7.1+2 Channel High Definition Audio Codec 36 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=26h (Fout Sum) Bit Description 7:0 Connection List Entry (N) Returns 25h (Fout1 DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID=14h~1Bh (Port-A to port-H) Bit Description 31:24 Connection List Entry (N+3) Returns 0Fh (Sum Widget NID=0Fh) for N=0~3 Returns 00h for n>3 23:16 Connection List Entry (N+2) Returns 0Eh (Sum Widget NID=0Eh) for N=0~3 Returns 00h for N>3 15:8 Connection List Entry (N+1) Returns 0Dh (Sum Widget NID=0Dh) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 0Ch (Sum Widget NID=0Ch) for N=0~3 Returns 26h (Sum Widget NID=26h) for N=4~7 Returns 00h for N>7 Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT) Bit Description 31:16 Connection List Entry (N+3) and (N+2) Returns 0000h 15:8 Connection List Entry (N+1) Returns 00h 7:0 Connection List Entry (N) Returns 06h (S/PDIF-OUT converter) for N=0~3 Returns 00h for N>3 Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs) Bit Description 31:24 Connection List Entry (N+3) Returns 1Bh (Pin Complex – LINE2) for N=0~3 Returns 15h (Pin Complex-SURR) for N=4~7 Returns 00h for N>7 23:16 Connection List Entry (N+2) Returns 1Ah (Pin Complex – LINE1) for N=0~3 Returns 14h (Pin Complex – FRONT) for N=4~7 Returns 0Bh (Sum Widget) for N=8~11 Returns 00h for N>11
Table 37. Verb – Get Processing State (Verb ID=F03h) Table 38. Verb – Set Processing State (Verb ID=703h)
Table 39. Verb – Get Coefficient Index (Verb ID=Dh) Table 40. Verb – Set Coefficient Index (Verb ID=5h)
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch) Table 42. Verb – Set Processing Coefficient (Verb ID=4h)
This verb is used to get gain/attenuation settings from each widget. Table 43. Verb – Get Amplifier Gain (Verb ID=Bh)
15 Get Input/Output
13 Get Left/Right
7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute, 1: Mute
7.1+2 Channel High Definition Audio Codec 41 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, Cen/Lfe, SIDESURR Sum) Bit Description 31:8 0’s Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. (No Input Amplifier Gain) Bit-15 is 1 in ‘Get Amplifier Gain’:Output Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –46.5dB~0dB in 1.5dB steps Codec Response for NID=14h~1Bh (Pin Complex: Front/Surr/CenLfe/SIDESURR/MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0’s
7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute, 0:Unmute, 1:Mute (NID=14h~1Bh,Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0’s Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain) Codec Response to Other NID Bit Description 31:0 Not supported (returns 00000000h)
This verb is used to set amplifier gain/attenuation in each widget. Table 44. Verb – Set Amplifier Gain (Verb ID=3h)
15 Set Output Amp
14 Set Input Amp
13 Set Left Amp
12 Set Right Amp
7 Mute
Table 45. Verb – Get Converter Format (Verb ID=Ah) Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/Lfe, Side-Surr, Fout DAC, S/PDIF-OUT).
15 Stream Type (TYPE)
14 Sample Base Rate (BASE)
Table 46. Verb – Set Converter Format (Verb ID=2h)
Table 47. Verb – Get Power State (Verb ID=F05h)
Table 48. Verb – Set Power State (Verb ID=705h) PS-Act indicates the actual power state of the referenced node. Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. (NID=08h~0Ah). Other widgets will ignore this verb. Table 50. Verb – Get Pin Widget Control (Verb ID=F07h)
7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit)
6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
Table 51. Verb – Set Pin Widget Control (Verb ID=707h)
7 H-Phn Enable
6 Out Enable
unsolicited response to inform software of a real-time event. Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h)
7 Unsolicited Response is Enabled
Enable a widget to generate an unsolicited response. Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h)
7 Enable Unsolicited Response
Returns the Presence Detect status and the impedance of a device attached to the pin. Table 54. Verb – Get Pin Sense (Verb ID=F09h)
31 Presence Detect Status
The ALC883 does not support hardware impedance detect. This field is read as 0s. Table 55. Verb – Execute Pin Sense (Verb ID=709h)
0 Right (Ring) Channel Select
Reads the 32-bit sticky register for each Pin Widget configured by software. Table 56. Verb – Get Configuration Default (Verb ID=F1Ch) 1Eh~1Fh such as placement and expected default device. Note: Supported by Pin Widget NID=14h~1Bh, 1Eh and 1Fh. Other widgets will ignore this verb.
Table 58. Verb – Get BEEP Generator (Verb ID= F0Ah) Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 60. Verb – Get GPIO Data (Verb ID= F15h) Table 61. Verb – Set GPIO Data (Verb ID= 715h)
Table 62. Verb – Get GPIO Enable Mask (Verb ID= F16h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 64. Verb – Get GPIO Direction (Verb ID=F17h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 65. Verb – Set GPIO Direction (Verb ID=717h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled.
Table 68. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets in the ALC883 series to return to their power on default state. Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
7 LEVEL (Generation Level)
6 PRO (Professional or Consumer format)
4 COPY (Copyright)
3 PRE (Pre-emphasis)
2 VCFG for Validity Control (control V bit and data in Sub-Frame)
1 V for Validity Control (control V bit and data in Sub-Frame)
7.1+2 Channel High Definition Audio Codec 58 Track ID: JATR-1076-21 Rev. 1.3 NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0]) NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0]) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 0 Digital Enable. DigEn 0: OFF 1: ON NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Dh) NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Eh) Bit Description (part of S/PDIF-IN Channel Status) 31:16 Reserved. Read as 0’s 15 Reserved. Read as 0’s 14:8 CC[6:0] (Category Code) 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data 0: Asserted 1: Not asserted 0: None 1: Filter pre-emphasis is 50/15 microseconds
2 Reserved
1 In‘V’alid. V bit in sub-frame of S/PDIF-IN 0: Data X and Y are valid, or S/PDIF-IN is not locked 1: At least one of data X and Y is invalid 0 Digital Enable. DigEn 0: OFF 1: ON Codec Response for Other NID Bit Description 31:0 0’s
Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
7.1+2 Channel High Definition Audio Codec 60 Track ID: JATR-1076-21 Rev. 1.3 ‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7 Reserved. Read as 0’s 6:0 CC[6:0] (Category Code) ‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7:1 Reserved 0 Digital Enable. DigEn 0: OFF 1: ON ‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7:0 Reserved. Read as 0’s Note: Other widgets will ignore this verb.
- Electrical Characteristics
Table 71. Absolute Maximum Ratings different AVDD should contact Realtek technical support representatives for special testing support. DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load. Table 72. Threshold Voltage
Table 73. Digital Filter Characteristics DVDD= 3.3V, Tambient=25°C, with 75Ω external load. Table 74. S/PDIF Input/Output Characteristics
Table 75. Link Reset and Initialization Timing
4 BCLK 4 BCLK >= 4 BCLK
Figure 15. Link Reset and Initialization Timing
Table 76. Link Timing Parameters at the Codec Figure 16. Link Signals Timing
Table 77. S/PDIF Output and Input Timing Figure 17. Output and Input Timing The ALC883 series does not support codec test mode or Automatic Test Equipment (ATE) mode.
- 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
- 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz, 0dB attenuation
Table 78. Analog Performance
7.1+2 Channel High Definition Audio Codec 67 Track ID: JATR-1076-21 Rev. 1.3 10. Application Circuits Designers are suggested to contact Realtek to get the latest application circuits. To get the best compatibility in hardware design and software driver, any modifications of application circuits should be confirmed by Realtek. Realtek may update the latest application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet.
7.1+2 Channel High Definition Audio Codec 68 Track ID: JATR-1076-21 Rev. 1.3 11. Mechanical Dimensions L See the Mechanical Dimensions notes on the next page.
7.1+2 Channel High Definition Audio Codec 69 Track ID: JATR-1076-21 Rev. 1.3 11.1. Mechanical Dimensions Notes MILLIMETER INCH SYMBOL MIN TYP MAX MIN. TYP MAX A 1.60 0.063 A1 0.05 0.15 0.002 0.006 c 0.09 0.20 0.004 0.008 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 E 9.00 BSC 0.354 BSC E1 7.00BSC 0.276 BSC E2 5.50 0.217 e 0.50 BSC 0.0196 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o L1 1.00 0.0393 TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm LEADFRAME MATERIAL DOC. NO. APPROVE VERSION 02 DWG NO. PKGC-065 CHECK DATE REALTEK SEMICONDUCTOR CORP.
Table 79. Ordering Information Note 1: See page 6 for Green package and version identification. sales representatives or agents.