ALC663

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(PN: ALC663-GR)

5.1 CHANNEL HIGH DEFINITION AUDIO CODEC

Rev. 1.0

23 April 2008

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

5.1 Channel High Definition Audio Codec ii Track ID: JATR-1076-21 Rev. 1.0 COPYRIGHT ©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular pu rpose. Realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark, of Realte k Semiconductor Corporation. Other na mes mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and soft ware engineer’s general information on the Realtek ALC663 Audio Codec IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the productio n of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2008/04/23 First release.

5.1 Channel High Definition Audio Codec iii Track ID: JATR-1076-21 Rev. 1.0 Table of Contents

5.1 Channel High Definition Audio Codec iv Track ID: JATR-1076-21 Rev. 1.0 8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 53 8.40. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR [7:0])

5.1 Channel High Definition Audio Codec v Track ID: JATR-1076-21 Rev. 1.0

TABLE 61. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)53 TABLE 75. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR

5.1 Channel High Definition Audio Codec 1 Track ID: JATR-1076-21 Rev. 1.0 1. General Description The ALC663 is a 5.1 Channel High Definition Audi o Codec designed for Microsoft Windows systems. It meets the current WLP3.10 (Windows Logo Program ) and future WLP requirements that become effective from 01 June 2008. Featuring three stereo DACs, two st ereo ADCs, legacy analog input to analog output mixing, one stereo digital microphone converter, and two independent S/PDIF output converters, the ALC663 provides a fully integrated audio solution for multimedia desktop and mobile PCs, and ultra mobile devices. The ALC663 integrates two ster eo ADCs and one stereo digita l microphone converter to support simultaneous analog microphone recording and digital microphone recording, and features Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) for voice applications. Multiple analog IO (e xcept MONO, PCBEEP, and HP-OUT) are input and output capable, and provide headphone amplifiers. Four linear headphone amplifie rs are integrated to drive earphones on port-A, port-D, port-E and port-F. The fifth headphone amp lifier on port-I (HPOUT) is designed to drive an earphone without the need for external DC blocki ng capacitors, reducing pop noise and enhancing sound quality. The ALC663 provides two independent S/PDIF output s and supports 16/20/24-bit S/DPIF output with a sampling rate of up to 192kHz, offering easy connec tion of PCs to high quality consumer electronic products such as digital decoders and speakers. In addition to the standard (primary) S/PDIF output function, the ALC663 features another independent (secondary) S/PDIF-OUT output and converters that transport digital audio output to a High Definition Media Interface (HDMI) transmitter (becoming more common in high-end PCs). In addition to the audio functions, the ALC663 supports enhanced power management. Its power management design conforms to Intel’s Audio Codec low power state white paper and is ECR compliant, reducing power consumption when the audio function is not being used, and offering jack detection wake-up when the system is in power down state so as to extend battery life fo r mobile systems without sacrificing audio features. The ALC663 supports host audio controller from the In tel ICH series chipset, and also from any other HDA compatible audio controller. With software ut ilities like Karaoke mode, environment emulation, multi-band software equalizer, dynamic range compressor and extender, optional Dolby ® Digital Live, DTS® CONNECT ™ , Dolby ® Home Theater, and SRS ® programs, the ALC663 provides an excellent home entertainment package and game experience for PC users.

5.1 Channel High Definition Audio Codec 2 Track ID: JATR-1076-21 Rev. 1.0 2. Features 2.1. Hardware Features „ Meets performance and function requirements for Microsoft WLP 3.10, and stricter performance requirements for future WLP effective from 01 June 2008 „ Six DAC channels support 16/20/24-bit PCM format for 5.1 sound playback „ Four-channel stereo ADC supports 16/20/24-bit PCM format „ All DACs support independent 44.1k/48k/96k/192kHz sample rate „ All ADCs support independent 44.1k/48k/96k/192kHz sample rate „ Two independent S/PDIF outputs support 16/20/24-bit format and 44.1k/48k/88.2k/96k/192kHz rate „ All analog jack ports except MONO, BEEP-IN and HP-OUT are stereo input and output re-tasking „ Supports line level mono output „ Supports analog PCBEEP input, and features an integrated digital BEEP generator „ Stereo digital microphone input supported for AEC/BF application „ Supports legacy analog mixer architecture „ Built-in five headphone amplifiers on port-A and port-D, port-E, port-F and port-I. „ Headphone amplifier on port-I (HP-OUT) is designed to drive output without external DC blocking capacitors „ Software selectable 2.5V and 3.2V reference output for microphone bias „ Software selectable boost gain (+10/+20/+30dB) for analog microphone input „ Two jack detection pins; each supports detection of up to 4 jacks „ Supports two GPIO (General Purpose Input/Output) pins (pin sharing with digital microphone interface) „ Supports EAPD (External Amplifier Power Down) control for external amplifier „ Supports anti-pop mode when analog power AVDD is on and digital power is off „ Supports 1.5V~3.3V scalable I/O for HD Audio link

5.1 Channel High Definition Audio Codec 3 Track ID: JATR-1076-21 Rev. 1.0 „ 48-pin LQFP ‘Green’ package „ Jack detection function is supported when device is in power down mode (D3) „ Supports primary SPDIF-OUT jack detection when CEN/LFE output is not enabled (customized RCA/optical transmitter with normal open switch is required) „ Independent secondary S/PDIF converter and pin to output digital stream to HDMI transmitter „ Intel low power ECR compliant, supports power status control for each analog converter and pin widgets, supports jack detection and wake up event in D3 mode 2.2. Software Features „ Meets Microsoft WLP 3.10 and future WLP audio requirements „ WaveRT-based audio function driver for Windows Vista „ EAX™ 1.0 & 2.0 compatible „ Direct Sound 3D™ compatible „ A3D™ compatible „ I3DL2 compatible „ Emulation of 26 sound environments to enhance gaming experience „ Multi-band software equalizer and related tools are provided „ Voice Cancellation and Key Shifting effect „ Dynamic range control (expander, compressor and limiter) with adjustable parameters „ Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience „ Provides 10-foot GUI for easy menu navigation on Windows Media Center „ Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application „ Smart multiple streaming operation „ HDMI audio driver for AMD platform „ Dolby® PCEE program™ (optional software feature)

5.1 Channel High Definition Audio Codec 4 Track ID: JATR-1076-21 Rev. 1.0 „ DTS® CONNECT™ (optional software feature) „ SRS® TrueSurround HD (optional software feature) „ Fortemedia® SAM™ technology for voice processi ng (Beam Forming and Acoustic Echo Cancellation) (optional software feature) 3. System Applications „ Desktop and mobile multimedia PCs „ Ultra mobile devices

Figure 1. Block Diagram

Figure 2. Pin Assignments shown in the location marked ‘V’ and ‘S’.

Table 1. Digital I/O Pins Shared with the digital MIC input data. SPDIFO1 O 48 S/PDIF Output 1 Output has 12 mA@75Ω driving capability. SPDIFO2 O 45 S/PDIF Output 2 Output has 12 mA@75Ω driving capability. Table 2. Analog I/O Pins

Table 3. Filter/Reference Table 4. Power/Ground

1. High Definition Audio Link Protocol

with a 48kHz frame rate. Figure 3 shows the basic concept of the HDA link protocol. Figure 3. HDA Link Protocol

Table 5. Link RESET# BCLK 24.0MHz bit clock sourced from the HDA controller and connecting to all codecs. controller and connects to all codecs. SDO. To extend outbound bandwidth, multiple SDOs may be supported. controller. The controller must support at least one SDI. Up to a maximum of 15 SDI’s can be supported. BCLK. SDI can be driven by the controller to initialize the codec’s ID. HDA controller and connects to all codecs. Table 6. HDA Signal Definitions BCLK Controller Output Global 24.0MHz bit clock. SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal. SDO Controller Output Serial data output from controller. RESET# Controller Output Global active low reset signal. Figure 4. Bit Timing

stream data is always carried on SDO0, the second bit on SDO1 and so forth. is always transmitted on SDO0, and copied on SDO1. Figure 8. Striped Stream on Multiple SDOs

Figure 11. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz. blocks are transmitted every 160 frames.

rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames. AND interleave an empty frame between non-empty frames (Table 9 , page 17). Table 7. Defined Sample Rate and Transmission Rate Table 8. 48kHz Variable Rate of Delivery Timing

Table 9. 44.1kHz Variable Rate of Delivery Timing

5.1 Channel High Definition Audio Codec 18 Track ID: JATR-1076-21 Rev. 1.0 7.3. Reset and Initialization There are two types of reset within an HDA link:

• Link Reset Generated by assertion of the RESET# signal. All codecs return to their power-on state
• Codec Reset Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events:
• Link Reset
• Codec Reset
• Codec changes its power state, e.g., hot docking a codec to an HDA system 7.3.1. Link Reset A link reset may be caused by any of the following three events: 1. The HDA controller asserts RESET# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ b it in the Global Control Register (GCR) of the HDA controller 3. Software initiates power management sequences . Figure 12, page 19, shows the ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v) Enter ‘Link Reset’: n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset o As the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low q The controller asserts the RESET# signal to low, and enters the ‘Link Reset’ state r All link signals driven by controller and codecs should be tri-state by internal pull-low resistors

4 BCLK 4 BCLK

Figure 12. Link Reset Timing

Figure 13. Codec Initialization Sequence controls parameters in the codec. Table 10. 40-Bit Commands in 4-Bit Verb Format Table 11. 40-Bit Commands in 12-Bit Verb Format

Table 12. Supported Commands *1: The ALC663 does not support Modem/HDMI/Vendor groups and Power State widgets.

Table 13. Supported Parameters *1: The ALC663 does not support Modem/HDMI/Vendor groups and Power State widgets.

software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 14. Solicited Response Format Table 15. Unsolicited Response Format several null commands received in frames between Function Group Reset verbs.

The ALC663 is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B compliant.

1. D3 state power < 30mW (without PC-Beep pa ss-through Function, with PC-Beep pass-through

Function, the criteria is 60mW.

1. Exit latency (D3 to D0 transfer) < 10ms.
2. Audio pop/click suppression during D3 and D0 transition < -65dBV.
3. Supports Jack detection in D3 state.
4. D3 functions with or without the BITCLK

Figure 14. Resume From External Event (Wake-Up Event)

individual power control to supply fine-grained power control. Table 16. System Power State Definitions D0 All power on. Individual DACs and ADCs can be powered up or down as required. reference is off (D1 + analog reference off). D3 Power still supplied. The codec stops the internal clock. State is maintained. D3 (No BitCLK) Power still supplied, BITC LK stopped, and Reset in low state. Table 17. Power Controls in NID 01h Table 18. Powered Down Conditions Front DAC powered down Analog block and digital filter are powered down. Surr DAC powered down Analog block and digital filter are powered down. CEN/LFE DAC powered down Analog block and digital filter are powered down. ADC 08h powered down Analog block and digital filte r are powered down. Data on SDATA-IN is quiet. ADC 09h powered down Analog block and digital filte r are powered down. Data on SDATA-IN is quiet. Headphone Driver powered down All headphone drivers are powered down. VREFOUTx at individual pin complexes are still alive.

1. Supported Verbs and Parameters

not supported by the addressed widget, it will respond with 32 bits of ‘0’. codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget. page 20, to get detailed information about supported parameters. Table 19. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 20. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) 31:16 Vendor ID=10ECh (Realtek’s PCI vendor ID). Note 1: The Root Node (NID=00h) supports this parameter. Table 21. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 31:24 Reserved. Read as 0’s. 15:8 Revision ID. The vendor’s revision number. Note: 00h indicates ALC663 silicon. 7:0 Stepping ID. The vendor’s stepping number within the given Revision ID. Note: The Root Node (NID=00h) supports this parameter.

associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 22. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) 31:24 Reserved. Read as 0’s. 7:0 Total Number of Nodes. For a root node, this is the total number of function groups in the root node. For a function group, this is the total number of widget nodes in the function group. Table 23. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) 0: Unsolicited response is not supported by this function group. 1: Unsolicited response is supported by this function group. Table 24. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h) 31:17 Reserved. Read as 0’s. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0’s. 11:8 Input Delay. Number of samples delay from analog input to HDA link. 3:0 Output Delay. Number of samples delay from HDA link to analog output.

Table 25. Parameter – Audio Widget Capa bilities (Verb ID=F00h, Parameter ID=09h) 31:24 Reserved. Read as 0’s. 19:16 Delay. Samples delayed between the HDA link and widgets. 15:12 Reserved. Read as 0’s. 8 ConnList. Connection List. 7 UnsolCap. Unsolicited Capable. 6 ProcWidget. Processing Widget. 3 AmpParOvr (AMP Param Override). 2 OutAmpPre (Out AMP Present). 1 InAmpPre (In AMP Present). There are amplifiers (Gain Control) in individual ADCs and Mixer widgets.

own parameters to provide supported formats if their ‘Format Override’ bit is set. Table 26. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) 31:21 Reserved. Read as 0’s. 20 B32. 32-bit audio format support. 19 B24. 24-bit audio format support. 18 B20. 20-bit audio format support. 17 B16. 16-bit audio format support. 16 B8. 8-bit audio format support. 15:12 Reserved. Read as 0’s. 11 R12. 384kHz (=8*48kHz) rate support. 10 R11. 192kHz (=4*48kHz) rate support. 8 R9. 96kHz (=2*48kHz) rate support. 7 R8. 88.2kHz (=2*44.1kHz) rate support. 4 R5. 32kHz (=2/3*48kHz) rate support. 2 R3. 16kHz (=1/3*48kHz) rate support. 0 R1. 8kHz (=1/6*48kHz) rate support.

have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 27. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Note: Input converters and output converters support this parameter. The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 28. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch) 31:16 Reserved. Read as 0’s. specified as a percentage of A VDD. 6 Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins. 5 Input Capable. ‘1’ indicates this pin complex supports input. 4 Output Capable. ‘1’ indicates this pin complex supports output. 3 Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone. 2 Presence Detect Capable. ‘1’ indicat es this pin complex can detect whether there is a device plugged in. 1 Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement. ‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type. Note: Only Pin Complex widgets support this parameter.

their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 29. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. Indicates which step is 0dB. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 30. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) steps. ‘0’ indicates 0.25dB steps. ‘127’ indicates 32dB steps. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 6:0 Offset. Indicates which step is 0dB.

Parameters in this node provide audio function widget connection information. Table 31. Parameter – Connect List Le ngth (Verb ID=F00h, Parameter ID=0Eh) input, and there is no Connection Select Control (not a MUX widget). Table 32. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) 31 Extended Power States Supported (EPSS).

2 D2Sup

1 D1Sup

0 D0Sup

Table 33. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h) 31:16 Reserved. Read as 0’s. 15:8 NumCoeff. Number of Coefficient. Table 34. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h) 31 GPIWake=0. The ALC663 does not support GPIO wake-up function. 30 GPIUnsol=1. The ALC663 supports GPIO unsolicited response. 29:24 Reserved. Read as 0’s. 23:16 NumGPIs=00h. No GPI pin is supported. 15:8 NumGPOs=00h. No GPO pin is supported. 7:0 NumGPIOs=02h. Two GPIO pins are supported. Table 35. Parameter – Volume Knob Capa bilities (Verb ID=F00h, Parameter ID=13h) The number of steps in the range of the V olume Control Knob. Note: The ALC663 does not support volume knob and will respond with 0s to this parameter.

Table 36. Verb – Get Connection Select Control (Verb ID=F01h) 7:0 Connection Index Currently Set (Default value is 00h). 7:0 Connection Index Currently Set (Default value is 00h). 7:0 Connection Index Currently Set (Default value is 00h). 7:0 Connection Index Currently Set (Default value is 00h). 7:0 Connection Index Currently Set (Default value is 00h). 31:0 Not Supported (returns 00000000h).

Table 37. Verb – Set Connection Select (Verb ID=701h) Table 38. Verb – Get Connection List Entry (Verb ID=F02h) 31:8 Connection List Entry (N+3), (N+2), and (N+1). 7:0 Connection List Entry (N). Returns 23h (Sum Widget) for N=0~3. Returns 00h for N>3. 31:8 Connection List Entry (N+3), (N+2), and (N+1). 7:0 Connection List Entry (N). Returns 22h (Sum Widget) for N=0~3. Returns 00h for N>3. 31:24 Connection List Entry (N+3). Return 1Bh (Pin Complex – LINE2) for N=0~3. Return 16h (Pin Complex – Cen/Lfe) for N=4~7. Return 00h for N>7. 23:16 Connection List Entry (N+2). Return 1Ah (Pin Complex – LINE1) for N=0~3. Return 15h (Pin Complex – SURR) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 19h (Pin Complex – MIC2) for N=0~3. Return 14h (Pin Complex –FRONT) for N=4~7. Return 00h for N>7. 7:0 Connection List Entry (N). Return 18h (Pin Complex – MIC1) for N=0~3. Return 1Dh (Pin Complex –PCBEEP) for N=4~7. Return 00h for N>7.

5.1 Channel High Definition Audio Codec 36 Track ID: JATR-1076-21 Rev. 1.0 Codec Response for NID=0Ch (Front Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 02h (Front DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Dh (Surround Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Eh (Cen/Lfe Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 04h (Cen/Lfe DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Fh (MONO Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 02h (Front DAC) for N=0~3. Returns 00h for N>3.

5.1 Channel High Definition Audio Codec 37 Track ID: JATR-1076-21 Rev. 1.0 Codec Response for NID=14h (FRONT, Port-D) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 0Dh (Sum Widget NID=0Dh) for N=0~3. Return 00h. 7:0 Connection List Entry (N). Return 0Ch (Sum Widget NID=0Ch) for N=0~3. Return 00h for N>3. Codec Response for NID=15h (SURR, Port-A) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 0Dh (Sum Widget NID=0Dh) for N=0~3. Return 00h. 7:0 Connection List Entry (N). Return 0Ch (Sum Widget NID=0Ch) for N=0~3. Return 00h for N>3. Codec Response for NID=16h (CEN/LFE, Port-G) Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3. 7:0 Connection List Entry (N). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3. Codec Response for NID=17h (MONO, Port-H) Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3. 7:0 Connection List Entry (N). Returns 0Fh (Sum Widget NID=0Fh) for N=0~3. Returns 00h for N>3. Codec Response for NID=18h (MIC1, Port-B) Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3. 7:0 Connection List Entry (N). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3.

5.1 Channel High Definition Audio Codec 38 Track ID: JATR-1076-21 Rev. 1.0 Codec Response for NID=19h (MIC2, Port-F) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 0Eh (Sum Widget NID=0Eh) for N=0~3. Return 00h for N>3. 15:8 Connection List Entry (N+1). Return 0Dh (Sum Widget NID=0Dh) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 0Ch (Sum Widget NID=0Ch) for N=0~3. Return 00h for N>3. Codec Response for NID=1Ah (LINE1, Port-C) Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1). Returns 000000h for n>3. 7:0 Connection List Entry (N). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for N>3. Codec Response for NID=1Bh (LINE2, Port-E) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 0Eh (Sum Widget NID=0Eh) for N=0~3. Return 00h for N>3. 15:8 Connection List Entry (N+1). Return 0Dh (Sum Widget NID=0Dh) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 0Ch (Sum Widget NID=0Ch) for N=0~3. Return 00h for N>3. Codec Response for NID=21h (HP-OUT, Port-I) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 0Eh (Sum Widget NID=0Eh) for N=0~3. Return 00h for N>3. 15:8 Connection List Entry (N+1). Return 0Dh (Sum Widget NID=0Dh) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 0Ch (Sum Widget NID=0Ch) for N=0~3. Return 00h for N>3. Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT1) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Returns 000000h. 7:0 Connection List Entry (N). Returns 06h (S/PDIF-OUT1 Converter) for N=0~3. Returns 00h for N>3.

5.1 Channel High Definition Audio Codec 39 Track ID: JATR-1076-21 Rev. 1.0 Codec Response for NID=11h (Pin Widget: S/PDIF-OUT2) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Returns 000000h. 7:0 Connection List Entry (N). Returns 10h (S/PDIF-OUT2 Converter) for N=0~3. Returns 00h for N>3. Codec Response for NID=22h (Sum Widget) Bit Description 31:24 Connection List Entry (N+3). Return 1Bh (Pin Complex – LINE2) for N=0~3. Return 16h (Pin Complex – CEN/LFE) for N=4~7. Return 00h for N>7. 23:16 Connection List Entry (N+2). Return 1Ah (Pin Complex – LINE1) for N=0~3. Return 15h (Pin Complex-SURR) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 19h (Pin Complex – MIC2) for N=0~3. Return 14h (Pin Complex – FRONT) for N=4~7. Return 12h (DMIC-1/2) for N=8~11. Return 00h for N>11. 7:0 Connection List Entry (N). Return 18h (Pin Complex – MIC1) for N=0~3. Return 1Dh (Pin Complex – PCBEEP) for N=4~7. Return 0Bh (Mixer) for N=8~11. Return 00h for N>11. Codec Response for NID=23h (Sum Widget) Bit Description 31:24 Connection List Entry (N+3). Return 1Bh (Pin Complex – LINE2) for N=0~3. Return 16h (Pin Complex – CEN/LFE) for N=4~7. Return 00h for N>7. 23:16 Connection List Entry (N+2). Return 1Ah (Pin Complex – LINE1) for N=0~3. Return 15h (Pin Complex-SURR) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 19h (Pin Complex – MIC2) for N=0~3. Return 14h (Pin Complex – FRONT) for N=4~7. Return 00h for N>11. 7:0 Connection List Entry (N). Return 18h (Pin Complex – MIC1) for N=0~3. Return 1Dh (Pin Complex – PCBEEP) for N=4~7. Return 0Bh (Mixer) for N=8~11. Return 00h for N>11. Codec Response for Other NID Bit Description 31:0 Not Supported (returns 00000000h)

Table 39. Verb – Get Processing State (Verb ID=F03h) 31:0 Not Supported (returns 00000000h). Table 40. Verb – Set Processing State (Verb ID=703h) Table 41. Verb – Get Coefficient Index (Verb ID=Dh) 31:16 Reserved. Read as 0’s. 31:0 Not Supported (returns 00000000h).

Table 42. Verb – Set Coefficient Index (Verb ID=5h) Table 43. Verb – Get Processing Coefficient (Verb ID=Ch) 31:16 Reserved. Read as 0’s. 15:0 Processing Coefficient. 31:0 Not Supported (returns 00000000h). Table 44. Verb – Set Processing Coefficient (Verb ID=4h)

This verb is used to get gain/attenuation settings from each widget. Table 45. Verb – Get Amplifier Gain (Verb ID=Bh) 3:0 Index[3:0] for Input Source. Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored. 7 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Mute). Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the volume from –64B~0dB in 1dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –16.5B~+30dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute). Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –16.5B~+30dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute).

5.1 Channel High Definition Audio Codec 43 Track ID: JATR-1076-21 Rev. 1.0 Codec Response for NID=0Bh (MIXER Sum Widget) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain ’. Input Amplifier Mute. 0: Unmute; 1: Mute (Default for all Index) Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Ga in’. Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute). Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, Cen/Lfe, MONO) Bit Description 31:8 0’s. 7 Bit-15 is 0 in ‘Get Amplifier Gain’. I nput Amplifier Mute. 0: Unmute; 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain). Codec Response for NID=14h, 15h, 16h, 17h and 21h (Pin Widget: FRONT/SURR/CEN/MONO/HP-OUT) Bit Description 31:8 0’s. 7 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Mute). Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0:Unmute; 1:Mute (Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain). Codec Response for NID=18h, 19h, 1Ah and 1Bh (Pin Widget: MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0’s. 7 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Mute). Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0:Unmute; 1:Mute (Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Ga in’. Input Amplifier Gain [6:0]. Specifying the boost from 0dB/10dB/20dB/30dB in 10dB per step (Default=0, 0dB). Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain). Codec Response for NID=22h (Sum Widget) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain ’. Input Amplifier Mute. 0: Unmute; 1: Mute (Default=1 for all index) Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain).

Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain). 31:0 Not Supported (returns 00000000h). This verb is used to set amplifier gain/attenuation in each widget. Table 46. Verb – Set Amplifier Gain (Verb ID=3h) 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets).

Table 47. Verb – Get Converter Format (Verb ID=Ah) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV). Not supported. Always read as 000b. Table 48. Get Converter Format Support

31:0 Not Supported (returns 00000000h). Table 49. Verb – Set Converter Format (Verb ID=2h) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV).

(see section 7.5 Power Management , page 24). Table 50. Verb – Get Power State (Verb ID=F05h) 31:11 Reserved. Read as 0’s. 5:4 PS-Act. Actual Power State [1:0]. (NID=01h), PS-Act is always equal to PS-Set. 1:0 PS-Set. Set Power State [1:0]. PS-Set controls the current power setting of the referenced node. 31:0 Not Supported (returns 00000000h).

Table 51. Verb – Set Power State (Verb ID=705h) 5:4 PS-Act. Actual Power State [1:0]. PS-Act indicates the actual power state of the referenced node. 1:0 PS-Set. Set Power State [1:0]. Table 52. Verb – Get Converter Stream, Channel (Verb ID=F06h) The link stream used by the converter. 0000b is unused, 0001b is stream 1, etc. 31:0 Not Supported (returns 00000000h).

Table 53. Verb – Set Converter Stream, Channel (Verb ID=706h) 7:4 Set Stream[3:0]. The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. well as n+1 for its left and right channel. Table 54. Verb – Get Pin Widget Control (Verb ID=F07h) Note: Only NID=14h, 15h, 19A, 1Bh and 21h support headphone amplifier. 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit). Note: NID= 1Dh (PCBEEP) do not support output and are always read 0. 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit). Note: NID=1Eh (1st S/PDIF-OUT) and 11h (2nd S/PDIF-OUT) do not support output and is always read 0. 2:0 VrefEn (Vrefout Enable Control). 31:0 Not Supported (returns 00000000h).

Table 55. Verb – Set Pin Widget Control (Verb ID=707h) Note: Only NID=14h, 15h, 19A, 1Bh, and 21h support headphone amplifier. 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit). Note: NID= 1Dh (PCBEEP) do not support output and are always read 0. 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit). st S/PDIF-OUT) and 11h (2nd S/PDIF-OUT) do not support output and is always read 0. 2:0 VrefEn (Vrefout Enable Control).

unsolicited response to inform software of a real-time event. Table 56. Verb – Get Unsolicited Response Control (Verb ID=F08h) 7 Unsolicited Response is Enabled. 3:0 Assigned Tag for Unsolicited Response. The tag[3:0] is assigned by software to determine which widget generates unsolicited responses. 31:0 Not Supported (returns 00000000h). Enable a widget to generate an unsolicited response. Table 57. Verb – Set Unsolicited Response Control (Verb ID=708h) 5:0 Tag for Unsolicited Responses.

Returns the Presence Detect status and the impedance of a device attached to the pin. Table 58. Verb – Get Pin Sense (Verb ID=F09h) The ALC663 does not support hardware impedance detect. This field is read as 0s. 31:0 Not Supported (returns 00000000h). Table 59. Verb – Execute Pin Sense (Verb ID=709h) 0 Right (Ring) Channel Select. The ALC663 does not support hardware impedance detect and will ignore this control bit.

Read the 32-bit sticky register for each Pin Widget configured by software. Table 60. Verb – Get Configuration Default (Verb ID=F1Ch/F1Dh/F1Eh/F1Fh) 31:0 32-bit configuration info rmation for each pin widget. device) for the Pin Widgets NID=0B~0Fh, 10h, 11h, 1Fh, 20h, and 12h. Table 61. Verb – Set Configuration Default Bytes 0, 1, 2, 3

Table 62. Verb – Get BEEP Generator (Verb ID= F0Ah) 7:0 Frequency Divider, F[7:0]. F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Table 63. Verb – Set BEEP Generator (Verb ID= 70Ah) 7:0 Frequency Divider, F[7:0]. F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except BEEP generator (NID=01h) will ignore this verb.

Table 64. Verb – Get GPIO Data (Verb ID= F15h) The value written (output) or sensed (input) on the corresponding pin if it is enabled. Table 65. Verb – Set GPIO Data (Verb ID= 715h) The value written determines the value driven on a pin that is configured as an output pin.

Table 66. Verb – Get GPIO Enable Mask (Verb ID= F16h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 67. Verb – Set GPIO Enable Mask (Verb ID=716h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 68. Verb – Get GPIO Direction (Verb ID=F17h) 1:0 GPIO[1:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 69. Verb – Set GPIO Direction (Verb ID=717h) 1:0 GPIO[1:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 70. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) 1:0 GPIO[1:0] Unsolicited Enable Mask. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 71. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) 1:0 GPIO[1:0] Unsolicited Enable Mask. Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled.

Table 72. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh) 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame).

Table 73. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)

7 LEVEL (Generation Level)

6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 6:0 CC[6:0] (Category Code).

Table 74. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) 31:16 Subsystem ID[23:8] (Default=10ECh). 15:8 Subsystem ID[7:0] (Default=06h). 7:0 Assembly ID[7:0] (Default=63h). Table 75. Verb – Set Subsystem ID [31:0]

Table 76. Verb – Get EAPD Control (Verb ID=F0Ch) 2 L-R Swap. The ALC663 does not support swapping left and right channels. Read as 0. 0 BTL Enable. The ALC663 does not support BTL output. Read as 0. Table 77. Verb – Set EAPD Control (Verb ID=70Ch) 2 L-R Swap. The ALC663 does not support swapping left and right channels. Read as 0. Note: Only one physical logic for the EAPD signal. 0 BTL Enable. The ALC663 does not support BTL output. Read as 0.

Table 78. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets to return to their power-on default state.

1. Electrical Characteristics

Table 79. Absolute Maximum Ratings *: The digital link power DVDD-IO must be lower than the digital core power DVDD. AVDD should contact Realtek technical support representatives for special testing support. DVDD=3.3V±5%, Tambient=25°C, with 50pF external load. Table 80. Threshold Voltage

DVDD= 3.3V, Tambient=25°C, with 75Ω external load. Table 81. S/PDIF Output Characteristics Table 82. Digital Filter Characteristics

Table 83. Link Reset and Initialization Timing

4 BCLK 4 BCLK >= 4 BCLK

Figure 15. Link Reset and Initialization Timing

Table 84. Link Timing Parameters at the Codec Figure 16. Link Signal Timing

Table 85. S/PDIF Output Timing Figure 17. Output Timing Codec test mode and Automatic Test Equipment (ATE) mode are not supported.

• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW: 10Hz~22kHz

Table 86. Analog Performance *1: The higher edge of magnitudes for DAC and ADC are -0.6dB@20,000Hz.

The ALC663 is NOT pin compatible with the ALC662, ALC88x, and ALC26x series HD Audio Codecs. (www.realtek.com.tw) without modifying this datasheet. Figure 18. Filter Connection

Figure 19. Onboard Front Panel Header Connection and Front Panel I/O

5.1 Channel High Definition Audio Codec 73 Track ID: JATR-1076-21 Rev. 1.0 11. Mechanical Dimensions L SYMBOL MILLIMETER INCH MIN TYP MAX MIN TYP MAX A1 0.05 - 0.15 0.002 - 0.006 c 0.09 - 0.20 0.004 - 0.008 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 E 9.00 BSC 0.354 BSC E1 7.00 BSC 0.276 BSC E2 5.50 0.217 e 0.50 BSC 0.0196 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm LEADFRAME MATERIAL DOC. NO. APPROVE VERSION 02 DWG NO. PKGC-065 CHECK DATE REALTEK SEMICONDUCTOR CORP.

Table 87. Ordering Information Note 1: See page 6 for Green package and version identification.