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Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect for Mobile Devices Datasheet Rev. 0.93 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect ii Rev. 0.93 COPYRIGHT ©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC5642 Audio Codec IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect iii Rev. 0.93
REVISION HISTORY
Revision Release Date Summary 0.9 2013/1/24 First release for version F. 0.91 2013/4/1 Modify power sequence 0.92 2013/11/02 Modify pin descriptions 0.93 2014/5/2 Add PR24 register description
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect iv Rev. 0.93 Table of Contents
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect v Rev. 0.93
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect vi Rev. 0.93
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect vii Rev. 0.93
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect viii Rev. 0.93 List of Tables
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect ix Rev. 0.93
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect x Rev. 0.93
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect xi Rev. 0.93
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 1 Rev. 0.93 1. General Description The ALC5642 is a high performance, low power, dual I2S interface audio CODEC with embedded low power Voice DSP. Dual I2S interface can connect to different devices and let the ALC5642 to be an Audio Hub. Each device can pass through the Audio Hub and then perform as input or output application. Asynchronous Sample Rate Converter (ASRC) provides independent and asynchronous connections to different processors, such as an application processor, baseband processor or wireless transceiver(BT). Stereo Class-D speaker amplifiers provide 1.5W per channel into 8Ω or 2.5W per channel into 4Ω with a 5V supply, with excellent PSRR and low EMI. A mono differential earpiece amplifier is also provided, providing output from any DAC or Analog-in. The ALC5642 features an ultra low power cap-free headphone amplifier. It consumes only less than 5mW power during playback, providing mobile system longer battery life under headphone listening mode. The integrated DRC(Dynamic Range Controller) and 7-band parametric Equalizer provide further digital sound processing capability of audio playback paths. The DRC in ALC5642 continuously monitors the DAC output level. When the power level is low, it increases the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. It ensures the maximum/consistent signal amplitude without producing audio clipping and speaker damage. The 7-band parametric Equalizer contains 7 independent filters with programmable gain, center frequency and bandwidth to tailor the frequency characteristics of embedded speaker system according to user preferences. For microphone recording, the DRC in ALC5642 can be used as AGC(Auto Gain Controller) to maintain a constant recording volume. Besides, a dynamic wind reduction filter is built in on recording path. The filter can detect the level of wind noise and on/off dynamically to keep the recording quality. ALC5642 embedded a low power wideband voice processor. The voice processor provides exceptional noise suppression, echo cancellation and beam forming under low power consumption. It combines 8/16 kHz sampling rate and 75MIPS digital signal processing to achieve high fidelity/dual-mic and non-stationary wideband performance. SounzRealTM digital sound effect technology is configurable to provide better listening experience. OminiSound EXP TM expands the sound field of embedded stereo speaker. BassBack EXPTM and TruBass EXP TM bring LFE(low frequency effect) to listeners without subwoofer needed. OmniHeadphone EXPTM provides broader sound field when wearing headphone. TruTreble EXPTM adds processed harmonic tones at high frequency, bringing more melody and details for music listening. ALC5642 only requires two voltage supplies and consume ultra low power, making it ideal for mobile devices.
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 2 Rev. 0.93 2. Features Analog Features: Digital-to-Analog Converter with 100dBA SNR Analog-to-Digital Converter with 94dBA SNR Differential analog microphone inputs with boost pre-amplifiers and low noise microphone bias +20/+24/+30/+35/+40/+44/+50/+52 dB microphone boost gain MIC input to ADC with 50dB boost gain, SNR > 66dBA and THD+N < -65dB Adjustable MICBIAS (0.9*MICVDD or 0.75*MICVDD) Stereo line inputs Line input to ADC with 0dB gain, SNR >= 94dBA, THD+N <= -83dB Stereo line outputs DAC to line output with 0dB gain, SNR >= 100dBA, THD+N <= -86dB Stereo/Mono BTL (Bridge-Tied-Load) Class-D amplifier 650mW/CH (SPKVDD=3.6V, THD+N < = 1%, 8Ohm Load) 500mW/CH (SPKVDD=3.6V, THD+N < = 0.1%, 8Ohm Load) 1.2W/CH (SPKVDD=5.0V, THD+N < = 1%, 8Ohm Load) 2.5W/CH (SPKVDD=5.0V, THD+N < = 10%, 4Ohm Load) 2.1W/CH (SPKVDD=5.0V, THD+N < = 1%, 4Ohm Load) Stereo Cap-Free headphone amplifier with ultra low power consumption for playback 20mW/CH (AVDD=CPVDD=1.8V, THD+N <= -80dB, 16Ohm Load and 32Ohm Load) Playback power consumption <= 5mW (AVDD=VBVDD=CPVDD=1.8V, 16Ohm, With I2S Clock, Playback Silence) Playback power consumption <= 13mW (AVDD=VBVDD=CPVDD=1.8V, 16Ohm, With I2S Clock, Playback 1mW/CH) Mono differential receiver amplifier 50mW/CH (AVDD=CPVDD=1.8V, THD+N <= -70dB, 16Ohm Load, BTL mode) Audio jack insert/combo jack detection Inside PLL can receiver wide range clock input
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 3 Rev. 0.93 Digital Features: Two 24bit/8kHz ~ 192kHz I2S/PCM interface for each mono DAC and stereo DAC Two 24bit/8kHz ~ 192kHz I2S/PCM interface for stereo ADC I2C control interface Two digital microphone interface support Asynchronous sample rate converter (ASRC) for each interface Programmable register table with two sequencers 7-bands flexible equalizer (EQ) for DAC path or ADC path Enhanced DRC(Dynamic Range Control)/AGC(Auto Gain Control) with compression function for DAC path or ADC path Dynamic wind noise reduction filter Zero detection and soft volume for pop noise suppression Speaker amplifier DC term self-test function for speaker protection SounzRealTM audio sound processing OmniHeadphone EXP TM OminiSound EXP TM TruTreble EXPTM BassBack EXPTM TruBass EXPTM 2.1-Ch Generator from 2-Ch Track Dipole Speaker Voice sound processing Voice Communication Enhancement Voice Recognition Enhancement Far Field Pick-Up Technology 3. System Application Smart Phones Tablet
- Function Block and Mixer Path
Figure 1. Block Diagram
Figure 2. Audio Mixer Path
Figure 3. Digital Mixer Path
Figure 4. Pin Assignments
Table 1. Digital I/O Pins
Table 2. Analog I/O Pins
Table 3. Filter/Reference Table 4. Power/Ground Digital power for digital core. connected to external 1.2V power.
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 11 Rev. 0.93 7. Function Description 7.1. Power There are different power types in ALC5642. DBVDD is for digital I/O power, DCVDD is for digital core power, AVDD and DACREF are for analog power, CPVDD is for charge pump power, MICVDD is for MICBIAS power and SPKVDD is for speaker amplifier power. The power supplier limit condition are DBVDD ≧ DCVDD and SPKVDD ≧ MICVDD > AVDD = DACREF = CPVDD, AVDD ≧ DCVDD, and for the best performance, our design setting is shown as below. Table 5. Power Supply for Best Performance Power DBVDD DCVDD AVDD DACREF CPVDD MICVDD SPKVDD *1.2V DCVDD can be generated by internal LDO or supplied by external 1.2V power. To prevent all power down leakage, there are two settings for power supply. At these conditions, the leakage will be smaller. First setting is to power on all power pin. Second setting is to only power on SPKVDD and others are removed. The detail setting is shown as following table. Table 6. Power Supply Condition for Power Down Leakage Power DBVDD DCVDD AVD D DACREF CPVDD MICVDD SPKVDD Setting-1 Supplied Supplied (or N/A)* Supplied Supplied Supplied Supplied (or N/A)* Supplied Setting-2 N/A N/A N/A N/A N/A N/A Supplied Setting-3 Supplied Supplied (or N/A)* Supplied Supplied Supplied Supplied (or N/A)* N/A “*” means DCVDD or MICVDD can be supplied by internal LDO and need to turn off when into power down mode.
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 12 Rev. 0.93 7.2. Power Supply On/Off Sequence To prevent pop noise and make sure function work normally, following power on and off sequence are recommended. Case1: For SPKVDD is from battery: Power On Sequence: (Sequentially turn on power pins) 1. Pull LDO1_EN pin (Pin#44) to DGND (digital ground) 2. SPKVDD power supply on 3. DCVDD power supply on (This step is required if DCVDD is supplied by external 1.2V power. This step and Step 5 are exclusive.) 4. DBVDD/AVDD/DACREF/CPVDD=1.8V power supply on 5. DBVDD power supply on (This step is required if DBVDD is supplied higher than 1.8V) 6. MICVDD power supply on (This step is required if MICVDD is supplied by external power) 7. Pull LDO1_EN pin (Pin#44) to DBVDD (This step is required if DCVDD is generated by internal LDO. This step and step 3 are exclusive. If DCVDD is supplied by external 1.2V, LDO1_EN must be pulled low.) 8. Initialize voice DSP and codec of ALC5642. 9. Power down voice DSP of ALC5642. (Write 0x0400’h to register MX-C6 ’h) Power Off Sequence: (Sequentially turn off power pins) 1. Power down voice DSP of ALC5642. (Write 0x0400’h to register MX-C6 ’h) 2. Power down all Codec function (Write 0x0000’h to register MX-00’h) 3. Pull LDO1_EN pin (Pin#44) to DGND (If internal LDO is used to generate DCVDD) 4. MICVDD power supply off (If MICVDD is supplied by external power) 5. DBVDD power supply off (This step is required if DBVDD is supplied higher than 1.8V) 6. DBVDD/AVDD/DACREF/CPVDD power supply off 7. DCVDD power supply off (If DCVDD is supplied by external power) 8. SPKVDD power supply off
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 13 Rev. 0.93 Case2: For SPKVDD is from PMIC: Power On Sequence: (Sequentially turn on power pins) 1. Pull LDO1_EN pin (Pin#44) to DGND (digital ground) 2. DCVDD power supply on (This step is required if DCVDD is supplied by external 1.2V power. This step and Step 5 are exclusive.) 3. DBVDD/AVDD/DACREF/CPVDD=1.8V power supply on 4. DBVDD power supply on (This step is required if DBVDD is supplied higher than 1.8V) 5. MICVDD power supply on (This step is required if MICVDD is supplied by external power) 6. SPKVDD power supply on 7. Pull LDO1_EN pin (Pin#44) to DBVDD (This step is required if DCVDD is generated by internal LDO. This step and step 3 are exclusive. If DCVDD is supplied by external 1.2V, LDO1_EN must be pulled low.) 8. Initialize voice DSP and codec of ALC5642. 9. Power down voice DSP of ALC5642. (Write 0x0400’h to register MX-C6 ’h) Power Off Sequence: (Sequentially turn off power pins) 1. Power down voice DSP of ALC5642. (Write 0x0400’h to register MX -C6 ’h) 2. Power down all Codec function (Write 0x0000’h to register MX-00’h) 3. Pull LDO1_EN pin (Pin#44) to DGND (If internal LDO is used to generate DCVDD) 4. SPKVDD power supply off 5. MICVDD power supply off (If MICVDD is supplied by external power) 6. DBVDD power supply off (This step is required if DBVDD is supplied higher than 1.8V) 7. DBVDD/AVDD/DACREF/CPVDD power supply off 8. DCVDD power supply off (If DCVDD is supplied by external power)
Figure 5. Power On/Off Sequence
There are 2 types of reset operation: power on reset (POR) and register reset. Table 7. Reset Operation control registers and logic. power on reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip. Table 8. Power-On Reset Voltage
- When DCVDD is supplied 1.2V
When MX -00h is wrote, all registers become to default value.
clock of each block and setup each divider. accuracy and keep audio performance under clock source asynchronous. device. The ratio of BCLK and LRCK can set by register – MX -73. Figure 6. Audio Clock Tree
source of the PLL can be set to MCLK, BCLK1 or BCLK2 by setting register. The S/W driver can set up the PLL to output a frequency to match the requirement of system clock. Table 10. Clock Setting Table for 48K (Unit: MHz) Table 11. Clock Setting Table for 44.1K (Unit: MHz)
Table 12. The relative of SYSCLK/BCLK/LRCK
registers need to set for this mode as shown at Table 13. Table 13. Register Settings for ASRC Function on Master Mode
Table 14. Register Settings for ASRC Function on Slave Mode
The ALC5642 provides 4-channel analog DAC s for playback and 2-channel analog ADC s for recording. interface, maybe two channels for one I2S interface or mono channel for one I2S interface. ADC can be powered down separately by setting pow_adc_l (MX-61[2]) and pow_adc_r (MX-61[1]). Figure 15. 4-Channel Recording Path
output, mono output or line output. vol_mono_dacl (MX-1A[15:8] and vol_mono_dacr (MX-1A[7:0]). Figure 16. 4-Channel Playback Path
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 27 Rev. 0.93 7.6.3. Mixers The ALC5642 has digital and analog mixers build-in. Output mixer - OUTMIXL/R The stereo analog mixer can do mixing for DAC output and analog input. The mixer output is mainly for headphone output and line output. Each input path has it’s mute control to the mixer block in MX -4D ~ MX -52. pow_outmixl and pow_outmixr can be used to power on/off OUTMIXL/R Speaker mixer – SPKMIXL/R The stereo analog mixer can do mixing for OUTMIX output, DAC output and analog input. The mixer output is for speaker output. Each input path has it’s mute control to the mixer block in MX -46 and MX-47. pow_spkmixl and pow_spkmixr can be used to power on/off SPKMIXL/R. Speaker_Out mixer – SP OM IXL/R The stereo analog mixer can do mixing for from speaker volume, DAC and analog input. The mixer output is direct to speaker output. Each input path has it’s mute control to the mixer block in MX -48 and MX-49. LINE_Out mixer – LO UT MIX The stereo analog mixer can do mixing for analog input and DAC output. The mixer output is for line-out output for drive external amplifier. Each input has individual mute control to the mixer block in MX -53. pow_lout can be used to power on/off LOUT MIX. Record mixer – RECMIXL/R The stereo analog mixer can do mixing for analog input and OUTMIX output. The mixer output is for ADC input. Each input path has it’s mute control to the mixer block in MX -3B ~ MX-3E. pow_recmixl and pow_recmixr can be used to power on/off RECMIXL/R. HP mixer – HPOMIXL/R The stereo analog mixer can do mixing for headphone volume and DAC output. The mixer output directly output to external headphone device. Each input path has it’s mute control to the mixer block in MX-45. Digital mixer There are ten digital mixers in ALC5642. Four digital mixers are assigned for ADC recording. These four mixers can mix analog line input, analog microphone input and digital microphone input then output to I2S interface to other device. Another four digital mixers are assigned DAC playback. These mixers can mix digital data from I2S interface or ADC data from external analog signal. The mixed data is output to analog DAC and output port to drive external device. The other two mixers are use for DA-AD processing. The incoming data from two I2S interfaces (DACDAT) uses these two mixers to do mixing and output to I2S interface (ADCDAT).
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 28 Rev. 0.93 7.7. Analog Audio Input Port The ALC5642 has two types analog input ports: microphone input and line input. IN1P/N The IN1P/N is a microphone type input port. The input port can be configured to differential input or single-ended input by MX-0D[7]. The microphone input port has its microphone bias and microphone boost. The low noise microphone bias can improve recording performance and enhance recording quality. Build-in short current detection scheme can be used for switch detection. Multi-steps microphone boost gain set by sel_bst1 (MX-0D[15:12]) is easy to use for microphone application. Pow_bst1 can be used to power down the MIC1 boost and pow_micbias1 can be used to power down the microphone bias 1. IN2P/N The IN2P/N is a dual type input port: microphone input and line input. Microphone input can be configured to differential input or single-ended input by MX-0E[6]. Multi-steps microphone boost gain set by sel_bst2 (MX-0E[11:8]) is easy to use for microphone application. Pow_bst2 can be used to power down the MIC2 boost. As line input, it has volume control for tuning by MX-0F[12:8] and MX -0F[4:0]. IN3P/N The IN3P/N is a microphone type input port. Microphone input can be configured to differential input or single-ended input by MX-0D[6]. Multi-steps microphone boost gain set by sel_bst3 (MX-0D[11:8]) is easy to use for microphone application. Pow_bst3 can be used to power down the MIC3 boost. The port is pin share with MONOP and MONON. If as IN3P/N port needs power down MONOP/N. And if as MONOP/N port needs power down IN3P/N.
The speaker output of ALC5642 is a stereo BTL output with Class-D type amplifier. ratio setting can be controlled by fbgain_clsd (MX-8D[15:12]). -46.5dB with 1.5dB/step controlled by MX -01. SPKVOLL and SPKVOLR. The pow_clsd (MX-61[0]) can be used to power on/off SPO_L/R_P/N. Figure 17. Stereo BTL Speaker Output
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 30 Rev. 0.93 HPO_L/R The headphone output of ALC5642 is a stereo output with cap-free type headphone amplifier. It does not need to connect external capacitor and can connect to earphone device directly. The headphone output source can mix from output mixer (OUTMIX) or DAC by setting MX-45. The front stage of headphone output has volume control and gain control. The volume range is from +12dB to -46.5dB with 1.5dB/step by MX-02. En_l_hp and en_r_hp (MX-63[7/6]) can be used to power on/off Headphone Amplifier, and pow_hpo_voll and pow_hpo_volr (MX-66[11/10]) can be used to power on/off headphone volume control. In addition, pow_pump_hp (MX-8E[3]) can be used to power on/off charge pump circuit for Headphone Amplifier. MONO_P/N The mono output is a differential output with Class-AB type amplifier. The mono output source can be mixed from analog input, OUTVOL and DAC output by setting MX-4C[15:11]. The front stage of mono output has gain control for attenuation, the gain control is 0dB or -6dB by MX -4C[10]. Line_OUT_L/R The output type is line type output. The output is a stereo single ended output. The input can be selected from OUTVOL or DAC output by setting MX-53[15:12]. The front stage of LOUT output has gain control for attenuation. The gain control is 0dB or -6dB by MX -53[11].
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 31 Rev. 0.93 7.9. Multi-Function Pins There are five multi-function pins in ALC5640. For different functions in each pins are controlled by register. You need to set the right register settings for each multi-function pins by your application. GPIO1/IRQ – Pin 40 The pin default is GPIO function. If want to change to IRQ output, write MX-C0[15] to 1’b that will switch to IRQ function. GPIO2/DMIC_SCL – Pin 41 The pin default is GPIO function. If want to change to DMIC clock output, write MX-C0[14] to 1’b that will switch to DMIC clock output function. IN1P/DMIC1_DAT – Pin 5 The pin default is DMIC1 data input function. In DMIC1 data input function, need to set these register settings: 1. Power down IN1P – MX -64[15] = 0’b 2. Mute IN1 to each analog mixer - (RECMIXL/RECMIXR/OUTMIXL/OUTMIXR/SPOLMIX/SPORMIX/MONOMIX). 3. Set IN1 as single-end mode – MX -FA[9] = 1’b In IN1P microphone input function, need to power down DMIC interface – MX75[15] = 0’b. IN1N/DMIC2_DAT/JD1 – Pin 6 The pin default is DMIC1 data input function. In DMIC2 data input function, need to set these register settings: 1. Power down IN1N – MX -64[15] = 0’b 2. Mute IN1 to each analog mixer - (RECMIXL/RECMIXR/OUTMIXL/OUTMIXR/SPOLMIX/SPORMIX/MONOMIX). 3. Set IN1 as single-end mode – MX -FA[9] = 1’b In IN1N microphone input function, need to power down DMIC interface – MX75[15] = 0’b. In JD1 jack detection function, need to set these register settings: 1. Power down IN1N – MX -64[15] = 0’b 2. Mute IN1 to each analog mixer - (RECMIXL/RECMIXR/OUTMIXL/OUTMIXR/SPOLMIX/SPORMIX/MONOMIX). 3. Set IN1 as single-end mode – MX -FA[9] = 1’b 4. Enable JD1 as jack detection source – MX -BB[15:13] = 010’b
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 32 Rev. 0.93 IN2N/JD2 – Pin 8 In IN2N microphone input function, need to disable JD2 jack detection function – MX -BB[15:13] = 000’b and MX-FB[8] = 0’b. In JD2 jack detection function, need to set these register settings: 1. Power down IN2N – MX -64[12] = 0’b 2. Mute IN2 to each analog mixer - (RECMIXL/RECMIXR/OUTMIXR). 3. Set IN2 as single-end mode – MX -FA[8] = 1’b 4. Enable JD2 as jack detection source – MX -BB[15:13] = 011’b Enable JD2 as extra jack detection source – MX -FB[8] = 1’b
return to the target level, need to set the pre-gain to achieve. Figure 20. DRC/AGC for Playback/Recording Mode
the input signal will be boosted to target level. Figure 21. DRC/AGC for Noise Gate Mode
prevent the signal is too small. Table 15. Ration Gain Table for SPKVDD and AVDD Figure 22. Ratio Gain Behavior for SPKVDD and AVDD
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 37 Rev. 0.93 7.12. SounzReal Sound Effect The Realtek’s SounzReal sound effect is composed of: OmniHeadphone OmniSound Dipole Speaker MP3 Enhancement BassBack BassBoost 7.13. Equalizer Block The equalizer block cascades 7 bands of equalizer to tailor the frequency characteristics of embedded speaker system according to user preferences and to emulate environment sound. The 7 bands equalizer includes two high pass filter, four band pass filter and one low pass filter. One high pass filter cascaded in the front end is used to drop low frequency tone, The tone has a large amplitude and may damage a mini speaker. The high pass filter can be used to adjust Treble strength with gain control. One low pass filter with gain control can adjust the Bass strength. Four bands of bi-quad band pass filters are used to emulate environment sounds, e.g., ‘Pub’, ‘Live’, ‘Rock’,… etc.. The gain, center frequency and bandwidth of each filter are all programmable. 7.14. Dynamic Wind Noise Reduction Filter The wind filter is implemented by a high pass filter equalizer. The wind filter is mainly for ADC recording used. The cut-off freqnecy of wind filter is programmable and is varied accroding to different sample rate. The filter is used to remove DC offset at normal condition, and to remove wind noise at application mode. The wind filter builds in auto detection scheme. When wind noise is higher than the threshold, the filter will be turn-on. When wind noise is lower than the threshold, the filter will be turn-off. This scheme will keep recording quality and also remove wind noise. Wind filter setting procedure: Step1: Disable wind noise detection if needed – PR -6C[15] Step2: Disable wind filter – MX -D3[15] Step3: Select target sample rate – MX -D3[14:12] and MX-D3[10:8] Step3: Fine tune wind filter Fc – PR -6E[11:6] Step4: Enable wind filter – MX -D3[15] Step5: Enable wind noise detection if needed – MX -D3[15]
The following table (Table 13.) is shown the Fc with sample rate selection. Table 16. Sample Rate with filter coefficient for Wind Filter
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 39 Rev. 0.93 PR -6E[11:6] n L & R Channel Sample Rate Setting 8K 16K 32K 44.1K 48K
drain structure. The input has built-in spike filter and can remove less than 50ns spike at SCL and SDA. Table 17. Address Setting (0x38h) Figure 23. Data Transfer Over I2C Control Interface
Table 18. Write WORD Protocol Table 19. Read WORD Protocol
pins – JD1 and JD2. The JD1 and JD2 share pins with IN1N and IN2N. Figure 24. GPIO Function Block
GPIO will output a flag as interrupt signal. Figure 25. IRQ Function Block
status – sta_jd2_internal – MX -FB[11] is dedicated for JD2 pin. And the enable control is by MX-FB[8]. together for these two status. Figure 26. JD Source Selection
- Select JD source: use JD1 as JD source. MX-BB[15:13] = 010’b
- Set wanted behavior by JD action – HP & SPK auto switch when JD is trigger.
- When JD status is low, HP_OUT is mute and SPK is un-mute.
When JD status is low go high, HP is un-mute and SPK is mute. path first. The register control of MX-BB[11:6] is only do mute/un-mute function for HP and SPK.
ALC5642 detailed Power Management control registers are supported in MX -61h, 62h, 63h, 64h and 65h. Each particular block will only be active when each bit MX -61h, 62h, 63h, 64h, and 65h is set to enable. Figure 27. Power Management
The Programmable Register Array is used for continuing executing register set by one register command. The Table 17 shown as programmable register table with two sequencers. Table 20. Programmable Register Table
- Set Programmable Register Table
- Enable Programmable Register Function (MX-CA[7])
- Check Sequencer-1/2 finished or not?
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 47 Rev. 0.93 7.19. Voice DSP Function The embedded voice DSP is a low power and high performance voice processor. It provides Acoustic Echo Cancellation (AEC), Beam Forming, Far Field Pick-Up (FFP), Noise Suppression (NS) and Voice Recognition (VR). Acoustic Echo Cancellation: The voice DSP suppresses echo effectively under all occasions, and the performance of which could be easily optimized for different types of acoustics set-up and applications ranging from mobile phones to tablet computers. Not only during periods of far-end single-talk are the echo returns completely absent on the upstream signal, the AEC performs robustly under prolonged double talk periods and provides full-duplex conversations without any cut-off, drop-out, howling, voice level pumpings, and annoying echoes. Noise Suppression: The voice DSP incorporates state-of-the-art digital signal processing technology that reduces both stationary noise and non-stationary noises. Stationary noise reduction is applied on both downstream and upstream signals and is highly effectively against hums, fan-noises, tones, and other pseudo-stationary noises. Stationary noise reduction is applicable in both 1-microphone and 2-microphone systems. For the upstream signal, any user system that deploys a 2-microphone signal front-end input could take advantage of the voice DSP 2-microphone non-stationary noise suppression and further improve the user experience by removing café noise, interfering background music and conversations, and other directional interference sounds. Far-Field Pickup: The far-field voice pick up technology that combines intelligent gain and signal dynamics control with sophisticated noise reduction to allow varying levels of microphone voice input to appear steady and stay at a comfortable range for the far-end listener. This feature allows user systems to perform end-to-end conferencing or voice-recording with the near-end talker speaking at varying distances within a 5 meters radius area from the microphone without any echoes, fade-outs, or severe intelligibility losses.
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 48 Rev. 0.93 Beam Forming: Not only could the voice DSP dual microphone input signal processing could provide directional talker voice pickup when used in handset close-talk mode, the technology has been extended to hands-free applications such that the voice pick-up in hands-free operations. Directional voice pickup in hands-free mode improves the voice quality of microphone input by reducing unnecessary pick-ups on room reverberations and background noises. Voice Recognition Enhancement: With a combination of highly effective AEC, NS, FFP, and directional input, the voice DSP has shown effectiveness in improving voice-recognition during severe background noise situations. The main critical improvement is to filter or block out the background noise to improve the voice hit rate in voice recognition engine under noisy occasion.
ALC5642 register map as shown as following and accessing unimplemented registers, will return a 0. Table 21. Register Map
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 50 Rev. 0.93 Type Name Description Register Address Reset State Power Management Management- I2S & DAC & ADC & Class-D Power Control MX -61h 0x0000’h Ma nagement-
2 Digital Filter Power Control MX -62h 0x0000’h
VREF & MBias & LOUTMIX & Mono & HP & LDO2 Power Control MX -63h 0x00C0’h Management- MICBST & MICBIAS Power Control MX -64h 0x0000’h Management- OUTMIX & SPKMIX & RECMIX Power Contr ol MX -65h 0x0000’h Management- SPOVOL & OUTVOL & HPOVOL & INVOL Power Control MX -66h 0x0000’h PR Register PR Index PR Register Index MX -6Ah 0x0000’h PR Data PR Register Data Mx -6Ch 0x0000’h Digital Interface I2S1 Port Ctrl I2S-1 Interface Control MX -70h 0x8000’h I2S2 Port Ctrl I2S-2 Interface Control MX -71h 0x8000’h ADC/DAC Clock-1 ADC/DAC Clock Control-1 MX -73h 0x1110’h ADC/DAC Clock-2 ADC/DAC Clock Control-2 MX -74h 0x0C00’h Digital MIC DMIC Digital Microphone Control MX -75h 0x1D00’h Global Clock Global Clock Global Clock Control MX -80h 0x0000’h PLL-1 PLL Control-1 MX -81h 0x0000’h PLL-2 PLL Control-2 MX -82h 0x0000’h ASRC-1 ASRC Control-1 MX -83h 0x0000’h ASRC-2 ASRC Control-2 MX -84h 0x0000’h ASRC-3 ASRC Control-3 MX -85h 0x0008’h AS RC -6 ASRC Control-4 MX -89h 0x0000’h ASRC-7 ASRC Control-5 MX -8Ah 0x0000’h SPK Amp Class-D Class-D OC Control MX -8Ch 0x0228’h Class-D Class-D Ratio Gain & Mode Control MX -8Dh 0xA800’h HP Amp HP HP Output De-Pop Control 1 MX -8Eh 0x0004’h HP Output De-Pop Control 2 MX -8Fh 0x1100’h HP Control MX -D6h 0x0400’h SPK Amp PV Detection SPKVDD Detection Control MX -92h 0x0000’h MICBIAS MICBIAS MICBIAS Control MX -93h 0x3000’h EQ EQ -1 EQ Control-1 MX -B0h 0x2000’h EQ -2 EQ Control-2 MX -B1h 0x0000’h EQ -Parameter EQ Low Pass Filter – a1 PR -A0h 0x1C10 ’h EQ -Parameter EQ Low Pass Filter – H0 PR -A1h 0x01F4’h EQ -Parameter EQ Band Pass Filter 1 – a1 PR -A2h 0xC5E9 ’h EQ -Parameter EQ Band Pass Filter 1 – a2 PR -A3h 0x1A98 ’h EQ -Parameter EQ Band Pass Filter 1 – H0 PR -A4h 0x1D2C ’h EQ -Parameter EQ Band Pass Filter 2 – a1 PR -A5h 0xC882 ’h EQ -Parameter EQ Band Pass Filter 2 – a2 PR -A6h 0x1C10 ’h EQ -Parameter EQ Band Pass Filter 2 – H0 PR -A7h 0x01F4’h EQ -Parameter EQ Band Pass Filter 3 – a1 PR -A8h 0xE904 ’h EQ -Parameter EQ Band Pass Filter 3 – a2 PR -A9h 0x1C10 ’h EQ -Parameter EQ Band Pass Filter 3 – H0 PR -AAh 0x01F4’h EQ -Parameter EQ Band Pass Filter 4 – a1 PR -ABh 0xE904 ’h EQ -Parameter EQ Band Pass Filter 4 – a2 PR -ACh 0x1C10 ’h
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 51 Rev. 0.93 Type Name Description Register Address Reset State EQ -Parameter EQ Band Pass Filter 4 – H0 PR -ADh 0x01F4’h EQ -Parameter EQ High Pass Filter 1 – a1 PR -AEh 0x1C10 ’h EQ -Parameter EQ High Pass Filter 1 – H0 PR -AFh 0x01F4’h EQ -Parameter EQ High Pass Filter 2 – a1 PR -B0h 0x2000’h EQ -Parameter EQ High Pass Filter 2 – a2 PR -B1h 0x0000’h EQ -Parameter EQ High Pass Filter 2 – H0 PR -B2h 0x2000’h DRC/AGC DR C/AGC-1 DR C/AGC Control-1 MX -B4h 0x2206’h DR C/AGC-2 DR C/AGC Control-2 MX -B5h 0x1F00’h DR C/AGC-3 DR C/AGC Control-3 MX -B6h 0x0000’h Jack Detection JD-1 Jack Detection Control-1 MX- BBh 0x0000’h JD-2 Jack Detection Control-2 MX -BCh 0x0000’h IRQ IRQ-1 IRQ Control-1 MX -BDh 0x0000’h IRQ-2 IRQ Control-2 MX -BEh 0x0000’h Flag Status Status GPIO & Internal Status MX -BFh 0x0000’h GPIO GPIO-1 GPIO Control-1 MX -C0h 0x0400’h GPIO-2 GPIO Control-2 MX -C2h 0x0000’h Voice DSP DSP R/W Voice DSP Access Control - Address MX -C4h 0x0000’h DSP R/W Voice DSP Access Control - Data MX -C5h 0x0000’h DSP Ctrl Voice DSP Control MX -C6h 0x2000’h Register Array Control-1 Register Array Control-1 MX -C8h 0x0000’h Control-2 Register Array Control-2 MX -C9h 0x0000’h Control-3 Register Array Control-3 MX -CAh 0x0000’h Control-4 Register Array Control-4 MX -CBh 0x0000’h Control-5 Register Array Control-5 MX -CCh 0x0000’h SounzReal Sound Effect BassBack BassBack Control MX -CFh 0x0013’h TruTreble TruTreble Control-1 MX -D0h 0x0680’h TruTreble TruTreble Control-2 MX -D1h 0x1C17’h OmniHeadpho ne OmniHeadphone Control MX -D2h 0x8C00’h OmniSound OmniSound Control PR -63h 0x3737’h Dipole SPK Dipole Speaker Control PR -75h 0x5000’h Wind Filter Control-1 Wind Filter Control – Enable/Disable, Sample Rate MX -D3h 0xA A20’h Control-2 Wind Detector Enable Control PR -6Ch 0x1AC5’h Control-3 Wind Detector Parameter Control PR -6Dh 0x00C0’h Control-4 Wind Filter Control - Fc PR -6Eh 0x3019’h Control-5 Wind Detector Parameter Control PR -6Fh 0x4096’h Control-6 Wind Detector Parameter Control PR -70h 0xC0BE’h Control-7 Wind Detector Parameter Control PR -73h 0x0000’h SVOL & ZCD SVOL & ZCD Soft Volume and ZCD Control MX -D9h 0x0809’h General Control General Control 1 MX -FAh 0x3400’h General Control 2 MX -FBh 0x0000’h General Control 3 MX -FCh 0x0001’h Digital I/O driving Control PR -3Ah 0x4002’h ADC/DAC RESET Control PR -3Dh 0x2400’h Digital Path Control PR -3Fh 0x0000’h Vendor ID ID Vendor ID MX -FEh 0x10EC’h
Table 22. MX-00h: S/W Reset Note: Writes to this register will reset all registers to their default values. Table 23. MX-01h: Speaker Output Control
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 53 Rev. 0.93 Port Name Bits Read/Write Reset State Description V ol_spor 5:0 R /W 8’h Right Speaker Channel Volume Control (SPKVOLR) 00’h: +12dB 08’h: 0dB 27’h: -46.5dB, with 1.5dB/step Volume Table DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 0 0 12 16 10 -12 32 20 -36 1 1 10.5 17 11 -13.5 33 21 -37.5 2 2 9 18 12 -15 34 22 -39 3 3 7.5 19 13 -16.5 35 23 -40.5 4 4 6 20 14 -18 36 24 -42 5 5 4.5 21 15 -19.5 37 25 -43.5 6 6 3 22 16 -21 38 26 -45 7 7 1.5 23 17 -22.5 39 27 -46.5 8 8 0 24 18 -24 9 9 -1.5 25 19 -25.5
10 A -3 26 1A -27
11 B -4.5 27 1B -28.5
12 C -6 28 1C -30
13 D -7.5 29 1D -31.5
14 E -9 30 1E -33
15 F -10.5 31 1F -34.5
Table 24. MX-02h: Headphone Output Control
Table 25. MX-03h: LINE Output Control
Table 26. MX-04h: MONO Output Control
Table 27. MX-0Dh: IN1/3 Input Control
Table 28. MX-0Eh: IN2 Input Control Table 29. MX-0Fh: INL & INR Volume Control
Table 30. MX-19h: DACL1/R1 Digital Volume
Table 31. MX-1Ah: DACL2/R2 Digital Volume
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 61 Rev. 0.93 15 F -60 68 44 -40.125 121 79 -20.25 174 AE -0.375 227 E3 16 10 -59.625 69 45 -39.75 122 7A -19.875 175 AF 0 228 E4 17 11 -59.25 70 46 -39.375 123 7B -19.5 176 B0 229 E5 18 12 -58.875 71 47 -39 124 7C -19.125 177 B1 230 E6 19 13 -58.5 72 48 -38.625 125 7D -18.75 178 B2 231 E7 20 14 -58.125 73 49 -38.25 126 7E -18.375 179 B3 232 E8 21 15 -57.75 74 4A -37.875 127 7F -18 180 B4 233 E9 22 16 -57.375 75 4B -37.5 128 80 -17.625 181 B5 234 EA 23 17 -57 76 4C -37.125 129 81 -17.25 182 B6 235 EB 24 18 -56.625 77 4D -36.75 130 82 -16.875 183 B7 236 EC 25 19 -56.25 78 4E -36.375 131 83 -16.5 184 B8 237 ED 26 1A -55.875 79 4F -36 132 84 -16.125 185 B9 238 EE 27 1B -55.5 80 50 -35.625 133 85 -15.75 186 BA 239 EF 28 1C -55.125 81 51 -35.25 134 86 -15.375 187 BB 240 F0 29 1D -54.75 82 52 -34.875 135 87 -15 188 BC 241 F1 30 1E -54.375 83 53 -34.5 136 88 -14.625 189 BD 242 F2 31 1F -54 84 54 -34.125 137 89 -14.25 190 BE 243 F3 32 20 -53.625 85 55 -33.75 138 8A -13.875 191 BF 244 F4 33 21 -53.25 86 56 -33.375 139 8B -13.5 192 C0 245 F5 34 22 -52.875 87 57 -33 140 8C -13.125 193 C1 246 F6 35 23 -52.5 88 58 -32.625 141 8D -12.75 194 C2 247 F7 36 24 -52.125 89 59 -32.25 142 8E -12.375 195 C3 248 F8 37 25 -51.75 90 5A -31.875 143 8F -12 196 C4 249 F9 38 26 -51.375 91 5B -31.5 144 90 -11.625 197 C5 250 FA 39 27 -51 92 5C -31.125 145 91 -11.25 198 C6 251 FB 40 28 -50.625 93 5D -30.75 146 92 -10.875 199 C7 252 FC 41 29 -50.25 94 5E -30.375 147 93 -10.5 200 C8 253 FD 42 2A -49.875 95 5F -30 148 94 -10.125 201 C9 254 FE 43 2B -49.5 96 60 -29.625 149 95 -9.75 202 CA 255 FF 44 2C -49.125 97 61 -29.25 150 96 -9.375 203 CB 45 2D -48.75 98 62 -28.875 151 97 -9 204 CC 46 2E -48.375 99 63 -28.5 152 98 -8.625 205 CD 47 2F -48 100 64 -28.125 153 99 -8.25 206 CE 48 30 -47.625 101 65 -27.75 154 9A -7.875 207 CF 49 31 -47.25 102 66 -27.375 155 9B -7.5 208 D0
Table 32. MX-1Bh: DACL2/R2 Mute/Un-Mute Control Table 33. MX-1Ch: Stereo ADC Digital Volume Control
Table 34. MX-1Dh: Mono ADC Digital Volume Control
Table 35. MX-1Eh: ADC Digital Boost Gain Control
Table 36. MX-27h: Stereo ADC Digital Mixer Control Table 37. MX-28h: Mono ADC Digital Mixer Control
Table 38. MX-29h: Stereo ADC to DAC Digital Mixer Control
15 R/W 1’h Mute Control for Stereo ADC Left Channel to DAC
7 R/W 1’h Mute Control for Stereo ADC Right Channel to DAC
Table 39. MX-2Ah: Stereo DAC Digital Mixer Control
13 R/W 0’h Gain Control for DACL1 to Stereo DAC Left Mixer
11 R/W 0’h Gain Control for DACL2 to Stereo DAC Left Mixer
5 R/W 0’h Gain Control for DACR1 to Stereo DAC Right Mixer
3 R/W 0’h Gain Control for DACR2 to Stereo DAC Right Mixer
Table 40. MX-2Bh: Mono DAC Digital Mixer Control
Table 41. MX-2Ch: DAC Digital Mixer Control
Table 42. MX-2Dh: Voice DSP Path Control 1
Table 43. MX-2Eh: Voice DSP Path Control 2
Table 44. MX-2Fh: Interface DAC/ADC Data Control Table 45. MX-3Bh: RECMIXL Control 1
Table 46. MX-3Ch: RECMIXL Control 2
Table 47. MX-3Dh: RECMIXR Control 1
Table 48. MX-3Eh: RECMIXR Control 2
Table 49. MX-45h: HPOMIX Control Table 50. MX-46h: SPKMIXL Control
Table 51. MX-47h: SPKMIXR Control
Table 52. MX-48h: SPOLMIX Control
Table 53. MX-49h: SPORMIX Control Table 54. MX-4Ah: SPOL/RMIX Gain Control
Table 55. MX-4Ch: MONOMIX Control
13 R/W 1’h Mute Control for OUTVOLR to MONOMIX
12 R/W 1’h Mute Control for OUTVOLL to MONOMIX
Table 56. MX-4Dh: OUTMIXL Control 1
Table 57. MX-4Eh: OUTMIXL Control 2
Table 58. MX-4Fh: OUTMIXL Control 3
Table 59. MX-50h: OUTMIXR Control 1
Table 60. MX-51h: OUTMIXR Control 2
Table 61. MX-52h: OUTMIXR Control 3 Table 62. MX-53h: LOUTMIX Control
Table 63. MX-61h: Power Management Control 1
Table 64. MX-62h: Power Management Control 2
15 R/W 0’h Stereo ADC Digital Filter Power Control
14 R/W 0’h Mono ADC_L Digital Filter Power Control
13 R/W 0’h Mono ADC_R Digital Filter Power Control
Table 65. MX-63h: Power Management Control 3
Table 66. MX-64h: Power Management Control 4
Table 67. MX-65h: Power Management Control 5 Table 68. MX-66h: Power Management Control 6
Table 69. MX-6Ah: Private Register Index Table 70. MX-6Ch: Private Register Data Table 71. MX-70h: I2S1 Digital Interface Control
Table 72. MX-71h: I2S2 Digital Interface Control
Table 73. MX-73h: ADC/DAC Clock Control 1
Table 74. MX-74h: ADC/DAC Clock Control 2
Table 75. MX-75h: Digital Microphone Control
Table 76. MX-80h: Global Clock Control Table 77. MX-81h: PLL Control 1
Table 78. MX-82h: PLL Control 2 Table 79. MX-83h: ASRC Control 1
Table 80. MX-84h: ASRC Control 2
4 R /W 0’h Automatically Detect I2S1 Input Sample Rate
3 R /W 0’h Automatically Detect I2S2 Input Sample Rate
Table 81. MX-85h: ASRC Control 3 Table 82. MX-89h: ASRC Control 4
Table 83. MX-8Ah: ASRC Control 5 Table 84. MX-8Ch: Class-D Amp OC Control
Table 85. MX-8Dh: Class-D Amp Output Control Table 86. MX-8Eh: HP Amp Control 1
Table 87. MX-8Fh: HP Amp Control 2 Table 88. MX-92h: SPKVDD Detection Control
Table 89. MX-93h: MICBIAS Control
Table 90. MX-B0h: EQ Control 1 sta_hpf2 6 R 0’h EQ High Pass Filter (HPF2) Status. This bit is set if overflow had ever occurred. sta_hpf1 5 R 0’h EQ High Pass Filter (HPF1) Status. This bit is set if overflow had ever occurred. sta_bpf4 4 R 0’h EQ Band-4 (BP4) Status. This bit is set if overflow had ever occurred. sta_bpf3 3 R 0’h EQ Band-3 (BP3) Status. This bit is set if overflow had ever occurred. sta_bpf2 2 R 0’h EQ Band-2 (BP2) Status. This bit is set if overflow had ever occurred. sta_bpf1 1 R 0’h EQ Band-1 (BP1) Status. This bit is set if overflow had ever occurred. sta_lpf 0 R 0’h EQ Low Pass Filter (LPF) Status. This bit is set if overflow had ever occurred.
Table 91. MX-B1h: EQ Control 2 en_hpf2 6 R /W 0’h EQ High Pass 2nd Butterworth Filter (HPF) Control. en_hpf1 5 R/W 0’h EQ High Pass Filter (HPF) Control. en_bpf4 4 R/W 0’h EQ Band-4 (BP4) shelving Filter Control. en_bpf3 3 R/W 0’h EQ Band-3 (BP3) shelving Filter Control. en_bpf2 2 R/W 0’h EQ Band-2 (BP2) shelving Filter Control. en_bpf1 1 R/W 0’h EQ Band-1 (BP1) shelving Filter Control. en_lpf 0 R/W 0’h EQ Low Pass Filter (LPF) Filter Control. Table 92. MX-B4h: DRC/AGC Control 1
13 R 1’h Update DR C/AGC Parameter
change the DRC/AGC rate, the parameter of DR C/AGC isn’t need be modified. parameter by I2S’s sample rate. Table 93. MX-B5h: DRC/AGC Control 2
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 105 Rev. 0.93 Name Bits Read/Write Reset State Description sel_drc_agc_post_bst 13:8 R /W 1f’h DR C/AGC Digital Post-Boost Gain (0.375dB/step) 00’h= -11.625dB 3F’h= 12dB Others: Reserved En_drc_agc_compres s
7 R/W 0’h DRC Compression Function Control
0’b: Disable 1’b: Enable Sel_ratio 6:5 R/W 0’h DRC Compression Ratio Selection 00’b: 1:1 01’b: 1:2 10’b: 1:4 11’b: 1:8 sel_drc_agc_pre_bst 4:0 R/W 0’h DR C/AGC Digital Pre-Boost GAin (1.5dB/step) 00’h= 0dB 01’h= 1.5dB 02’h= 3dB 03’h= 4.5dB 13’h= 28.5dBFS Others: Reserved Gain table: DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DE C HEX Boost Gain 0 0 -11.625 16 10 -5.625 32 20 0.375 48 30 6.375 64 40 1 1 -11.25 17 11 -5.25 33 21 0.75 49 31 6.75 65 41 2 2 -10.875 18 12 -4.875 34 22 1.125 50 32 7.125 66 42 3 3 -10.5 19 13 -4.5 35 23 1.5 51 33 7.5 67 43 4 4 -10.125 20 14 -4.125 36 24 1.875 52 34 7.875 68 44 5 5 -9.75 21 15 -3.75 37 25 2.25 53 35 8.25 69 45 6 6 -9.375 22 16 -3.375 38 26 2.625 54 36 8.625 70 46 7 7 -9 23 17 -3 39 27 3 55 37 9 71 47 8 8 -8.625 24 18 -2.625 40 28 3.375 56 38 9.375 72 48 9 9 -8.25 25 19 -2.25 41 29 3.75 57 39 9.75 73 49 10 A -7.875 26 1A -1.875 42 2A 4.125 58 3A 10.125 74 4A 11 B -7.5 27 1B -1.5 43 2B 4.5 59 3B 10.5 75 4B 12 C -7.125 28 1C -1.125 44 2C 4.875 60 3C 10.875 76 4C
15 F -6 31 1F 0 47 2F 6 63 3F 12
10 A 15 26 1A
12 C 18 28 1C
14 E 21 30 1E
Table 94. MX-B6h: DRC/AGC Control 3
6 R/W 0’h Enable Noise Gate function
5 R/W 0’h Enable Noise Gate Hold Data Function
Table 95. MX-BBh: Jack Detection Control 1
Table 96. MX-BCh: Jack Detection Control 2
Table 97. MX-BDh: IRQ Control 1 Table 98. MX-BEh: IRQ Control 2
15 R/W 0’h IRQ Output Source Configure of MICBIAS1 Over Current
11 R/W 0’h Sticky Control for MICBIAS1 Over Current
Table 99. MX-BFh: GPIO and Internal Status Table 100. MX-C0h: GPIO Control 1
Table 101. MX-C2h: GPIO Control 2 Table 102. MX-C4h: Voice DSP Control 1 Table 103. MX-C5h: Voice DSP Control 2
Table 104. MX-C6h: Voice DSP Control 3 Table 105. MX-C8h: Programmable Register Array Control 1
Table 106. MX-C9h: Programmable Register Array Control 2 Table 107. MX-CAh: Programmable Register Array Control 3
Table 108. MX-CBh: Programmable Register Array Control 4 Table 109. MX-CCh: Programmable Register Array Control 5 Table 110. MX-CFh: SounzReal BassBack Control
Table 111. MX-D0h: SounzReal TruTreble Control 1
Table 112. MX-D1h: SounzReal TruTreble Control 2 Table 113. MX-D2h: SounzReal OmniHeadphone Control
Table 114. MX-D3h: Wind Filter Control – Enable/Disable Table 115. MX-D6h: HP Amp Control
Table 116. MX-D9h: Soft Volume & ZCD Control
Table 117. MX-FAh: General Control 1
5 R/W 0’h Clock Select for Left Mono ADC
4 R/W 0’h Clock Select for Right Mono ADC
Table 118. MX-FBh: General Control 2
Table 119. MX-FCh: General Control 3 Table 120. PR-01h: ALC Parameter Control
Table 121. PR-02h: ALC Parameter Control Table 122. PR-24h: Charge Pump Parameter Control Table 123. PR-3Ah: Digital IO Driving Control
Table 124. PR-3Dh: ADC/DAC RESET Control Table 125. PR-3Fh: Digital Path Control
14 R/W 0’h Select DACR2 Source
rx_lr_mixer 11 R/W 0’h DSP RxDP L / R channel data control.
Table 126. PR-63h: SounzReal OmniSound Control Table 127. PR-6Ch: Wind Detector Control 1
Table 128. PR-6Dh: Wind Detector Control 2 Table 129. PR-6Eh: Wind Detector Control 3 Table 130. PR-6Fh: Wind Detector Control 4 Table 131. PR-70h: Wind Detector Control 5
Table 132. PR-73h: Wind Detector Control 6 Table 133. PR-75h: SounzReal Dipole Speaker Control Table 134. PR -90h: HP Amplitude Threshold Control
Table 135. PR -91h: HP Amplitude Threshold Control Table 136. PR-A0h: EQ Low Pass Filter Coefficient (LPF:a1) Table 137. PR-A1h: EQ Low Pass Filter Gain (LPF:H0) Table 138. PR-A2h: EQ Band 1 Coefficient (BPF1:a1)
Table 139. PR-A3h: EQ Band 1 Coefficient (BPF1:a2) Table 140. PR-A4h: EQ Band 1 Gain (BPF1:H0) Table 141. PR-A5h: EQ Band 2 Coefficient (BPF2:a1) Table 142. PR-A6h: EQ Band 2 Coefficient (BPF2:a2)
Table 143. PR-A7h: EQ Band 2 Gain (BPF2:H0) Table 144. PR-A8h: EQ Band 3 Coefficient (BPF3:a1) Table 145. PR-A9h: EQ Band 3 Coefficient (BPF3:a2) Table 146. PR-AAh: EQ Band 3 Gain (BPF3:H0)
Table 147. PR-ABh: EQ Band 4 Coefficient (BPF4:a1) Table 148. PR-ACh: EQ Band 4 Coefficient (BPF4:a2) Table 149. PR-ADh: EQ Band 4 Gain (BPF4:H0) Table 150. PR-AEh: EQ High Pass Filter 1 Coefficient (HPF1:a1)
Table 151. PR-AFh: EQ High Pass Filter 1 Gain (HPF1:H0) Table 152. PR-B0h: EQ High Pass Filter 2 Coefficient (HPF2:a1) Table 153. PR-B1h: EQ High Pass Filter 2 Coefficient (HPF2:a2) Table 154. PR-B2h: EQ High Pass Filter 2 Gain (HPF2:H0)
Table 155. MX-FEh: Vendor ID
- Electrical Characteristics
Table 156. Absolute Maximum Ratings Note 1: SPKVDD=5V with 3.5% duty cycle Power bouncing up to SPKVDD=7V is acceptable. Table 157. Recommended Operating Conditions Table 158. Static Characteristics Note: DBVDD =1.8V, DCVDD=1.2V , Tambient=40C.
Table 159. Analog Performance Characteristics
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 135 Rev. 0.93 Parameter M in Typ Max Units Line_In to Stereo ADC with 0dB (Single-end) MIC_In to Stereo ADC with 0dB (Differential or Single-end) MIC_In to Stereo ADC with 20dB and MICBIAS (Differential or Single-end) MIC_In to Stereo ADC with 40dB and MICBIAS (Differential or Single-end) MIC_In to Stereo ADC with 50dB and MICBIAS (Differential or Single-end) -83 -83 -81 -74 -65 dB dB dB dB dB PSRR (Vripple=100mV , <=1KHz) DAC to Headphone Amplifier DAC to BTL Speaker Amplifier MIC/LINE_IN to ADC dB dB dB BTL Speaker Amplifier Efficiency (fIN=1kHz, 4 Load, SPKVDD=5.0V , Output Power=2.8W, with LC filter, L=33uH and C=1uF) Class-D (Stereo Mode) Power Consumption (Slave I2S Mode, 24-bit, SR: 44.1KHz) P_power down (No Clock Input) P_playback (Stereo DAC to HP_OUT with 16 Ohm Load, With Clock, play silence) P_playback (Stereo DAC to HP_OUT with 16 Ohm Load, With Clock, Po=1mW/CH) P_playback (Stereo DAC to SPK_OUT with 8 Ohm Load, With Clock, play silence) P_record (LINE_IN to Stereo ADC, With Clock) <150 <= 5 <= 13 < 19 < 8 uW mW mW mW mW Power Down Current IDDA (Analog Block) IDDD (Digital Block) µA µA MICBIAS1 Output Voltage Setting 1 Setting 2 0.9*MICVDD 0.75*MICVDD V V MICBIAS1 Drive Current MICBIAS = 0.9*LDO2_O mA Note: Standard test conditions: T ambient=25C DB VDD =1.8V DCVDD=1.2V A VDD=1.8V MICVDD=3.3V CPVDD=1.8V SPKVDD=5.0V or 4.2V or 3.6V . 1kHz input sine wave; PCM Sampling frequency=48kHz; Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation dBA: with A-Weighting
Figure 28. I 2C Control Interface Table 160. I2C Timing
Figure 29. Timing of I 2S/PCM Master Mode Table 161. Timing of I 2S/PCM Master Mode
Figure 30. I 2S/PCM Slave Mode Timing Table 162. I 2S/PCM Slave Mode Timing
Figure 31. Digital Microphone Interface Timing Table 163. Digital Microphone Interface Timing
Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzRealTM Digital Sound Effect 140 Rev. 0.93 10. Application Circuits R13 0/5% C12 2.2uF/6.3VCPVEE MONON If Use LDO1, Then Remove This Resistor R14 0/5% R26 10k/5% GPIO1/IRQ C28 10uF/16V 1.71V ~ 1.9V LOUTL SPKGND DGND C21 0.1uF/6.3V C22 10uF/6.3V CPVDD SPO_LN C27 0.1uF/16V SPKVDD C29 0.1uF/6.3V DBVDD C31 0.1uF/6.3V ALC5642 SPO_LP 1 LOUTL 16LOUTR 17 MICBIAS14 DACREF 10 SPO_LN 48 SPO_RN 47 SCL 38 MONON/IN3N 14 AVDD 15 DACDAT133 ADCDAT134 GPIO2/DMIC_SCL 41 DCVDD 42 DBVDD 43 AGND9 MONOP/IN3P 13 IN1P/DMIC1_DAT5 DACDAT231 CPN1 21 CPVEE 27 HPO_L 28 BCLK136 LRCK135 CPVDD 23 CPP1 20 VREF212 HPO_R 26 SDA 39 MCLK37 SPO_RP 45 SPKVDDL 2 IN2N/JD28 IN2P7 IN1N/DMIC2_DAT/JD16 VREF111 SPKGND49 DGND49 GPIO1/IRQ 40 CPGND22 ADCDAT232 BCLK230 LRCK229 SPKVDDR 46 HPOFB 25 CPP2 19 CPN2 18 CPVPP 24 MICVDD 3 LDO1_EN 44 DBVDD CPVDD R106 0/5%/1206 Size SPO_LP MONOP SPO_RN IN2N BCLK SPO_RP I2C Interface By-Pass Capcity Near The Power Pins AVDD 3.0V ~ 3.6V R29 0/5% C19 0.1uF/6.3V C20 10uF/6.3V SDAT IN1P MCLK C43 0.1uF/6.3V C44 2.2uF/6.3V MICVDD R15 0/5% GPIO R17 0/5% C41 2.2uF/6.3V C52 22pF/6.3V/NC R8 0/5% VLRCK LRCK2 BCLK2VBCLK I2S2 Interface C39 22pF/6.3V/NC SPKVDD DCVDD C40 22pF/6.3V/NC DACDAT2 ADCDAT2 VDACDAT R18 0/5% C54 22pF/6.3V/NC C42 2.2uF/6.3V VADCDAT SPKVDD MICBIAS1 3.3V ~ 5.0V IN1N R107 0/5% AGND HPOL C18 4.7uF/6.3V IN2P DACDAT C30 2.2uF/6.3V C32 2.2uF/6.3V HPOR LDO1 Control 1: Enable 0: Disable R10 0/5% LRCK ADCDAT VADCDAT DBVDD VDACDAT C25 2.2uF/6.3V 1.71V ~ 3.3V C50 22pF/6.3V/NC If Use LDO2, Then Remove This Resistor DACREF VLRCK Close to HP Jack's GND R7 0/5% LRCK LRCK1 BCLK1BCLK I2S1 Interface VBCLK MCLK C33 22pF/6.3V/NC AVDD C34 22pF/6.3V/NC CPGND R27 10k/5% Power 1.0V ~ 1.2V ADCDAT1 R28 0/5% DACDAT SCLK DACREF C48 0.1uF/6.3V C49 10uF/6.3V DACDAT1 C10 2.2uF/6.3V LDO1_EN DBVDD DCVDD MICVDD R11 0/5% R9 0/5%MCLK C45 22pF/6.3V/NC 4.7uF/6.3V LOUTR C51 22pF/6.3V/NC 1.71V ~ 1.9V SCL_Host CPVPP DMIC_SCL Reserved for PSRR ADCDAT SDA_Host
Figure 32. Application Circuit
Figure 33. Package Dimension
Table 164. Thermal Information
- PCB Dimension (L x W): 114.3mm x 101.6mm
- Number of Cu Layer-PCB: 4-layers (2S2P)
Table 165. Ordering Information
- “R ” is special for certain assign project purpose, not for general purpose.