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I2S AUDIO CODEC + 1.3W CLASS AB/D MONO SPEAKER AMPLIFIER DATASHEET Rev. 1.0

08 April 2008

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier ii Track ID: JATR-1076-21 Rev. 1.0 COPYRIGHT ©2008 Realtek Semiconductor Corp. A ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular pu rpose. Realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC5622 Audio Codec IC. Though every effort has been made to ensure th at this document is cu rrent and accurate, more information may have become available subsequent to the production of th is guide. In th at event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2008/04/08 First release

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier iii Track ID: JATR-1076-21 Rev. 1.0 Table of Contents

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier iv Track ID: JATR-1076-21 Rev. 1.0

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier v Track ID: JATR-1076-21 Rev. 1.0

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 1 Track ID: JATR-1076-21 Rev. 1.0 1. General Description The ALC5622 is a highly-integrated I 2S/PCM interface audio codec with multiple input/output ports and is designed for mobile computing and communications. It provides a Stereo Hi-Fi DAC for playback and Stereo ADC for recording via the I2S/PCM interface. To reduce component count, the device can connect directly to:

  • MONO or stereo differential analog inputs
  • LINE_IN stereo Single-Ended analog inputs
  • AUX_IN Single-Ended analog inputs
  • Stereo LINE_Out Output
  • Single-end stereo configurable to AUXOUT or BTL MONO_OUT
  • MONO or Stereo Bridge-Tied Load (BTL) speaker Multiple analog input and output pins are provided for seamless integration with analog connected wireless communication devices. Differential input/output connec tions efficiently reduce noise interference, providing better sound quality. Class AB or Class D amplifiers are easily swapped via simple register configuration, and the 1.3 Watt M ono speaker removes the need for an additional amplifier, further cutting both cost and required board area. Additionally, a flexible hardware 5-band equalizer with configurable gain, bandwidth, and center frequency, enriches the sound experience. The ALC5622 AVDD operates at supply voltages from 2.3V to 3.6V. DVDD operates from 1.71V to 3.6V, and SPKVDD operates from 2.3V to 5V. To extend battery life, each sectio n of the device can be powered down individually under software control. L eakage current in maximum power saving state is less than 10µA. The ALC5622 is available in a 5x5mm ‘Green’ QFN- 32 package, making it ideal for use in handheld portable systems.

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 2 Track ID: JATR-1076-21 Rev. 1.0 2. Features „ Digital-to-Analog Converter with 92dB SNR and –85dB THD+N „ Analog-to-Digital Converter with 85dB SNR and –80dB THD+N „ Two analog stereo single-ended inputs, LINE-IN_L/R and AUXIN_L/R „ Stereo differential analog microphone inputs, with boost pre-amplifiers (+20/+30dB) „ BTL (Bridge-Tied Load) Speaker output with on-chip 1.3W speaker driver (SPKVDD=5V, 4.7Ω load with THD+N=40dB) „ Mono Speaker output supports Class AB or Class D optional „ Stereo Line_Out output „ Differential MONO_OUT configurable to Single Ended AUXOUT (AVDD=3.3V, 32Ω load) „ Audio jack insert detection and microphone switch detection „ Power management and enhanced power saving „ Supports digital 5-band equalizer (EQ) „ Supports digital spatial sound and pseudo stereo effect „ Supports pop noise suppression „ Internal PLL can receive wide range of clock input „ Digital power supplies from 1.71V to 3.6V; speaker amplifier power supplies from 2.3V to 5V „ Analog power supplied from 2.3V to 3.6V „ Supports softmute function „ 32-pin QFN package 3. System Applications „ Tablet PC system/Ultra-Mobile PC (UMPC) „ Personal Digital Assistants (PDA) or PDA Phone „ Multimedia Phone Applications „ Portable Navigation Device (PND) „ Bluetooth Headphone

1.3 W BTL

Figure 1. Block Diagram

Figure 2. Audio Mixer Path

Figure 3. Pin Assignments

Table 1. Digital I/O Pins

15 General Purpose Input And Output/

Table 2. Analog I/O Pins

Table 3. Filter/Reference Table 4. Power/Ground Note: DBVDD ≥ DCVDD, and SPKVDD ≥ AVDD ≥ DCVDD.

conditions are DBVDD ≥ DCVDD, and SPKVDD ≥ AVDD ≥ DCVDD. There are two types of reset operation: Power-On Reset (POR) and Register reset. Table 5. Reset Operation POR Monitor digital power supply voltage reach V POR Power-On Reset. Reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip. Table 6. Power-On Reset Voltage Note: VPOR_OFF must be below VPOR_ON.

Figure 4. Audio SYSCLK setting pll_sour_sel (Reg42[14]). Table 7. Clock Setting Table for 48K (Unit: MHz)

Table 8. Clock Setting Table for 44.1K (Unit: MHz) default values after a soft-reset (write Reg00). BCLK synchronized clock externally as the Stereo_SYSCLK.

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 14 Track ID: JATR-1076-21 Rev. 1.0 7.5. Audio Data Path 7.5.1. Vref Vref is the reference voltage for all analog blocks . An external 1µF Capacitor connected to AGND is required. The default status of Vref is enabled after power on. Driver can set I ndex-39[11]=0b in order to enable power control bit of Reg-3C[13]:pow_vref. 7.5.2. Stereo ADC The stereo ADC is used for recordi ng stereo sound. The sample rate of the stereo ADC is independent of the stereo DAC sample rate. In order to save power, the left and right ADC can be powered down separately by setting adc_l_vol and adc_r_vol The sample rate of the Stereo ADC is the same as the sample rate of Stereo DAC (described in the following section). 7.5.3. Stereo DAC The stereo DAC can be configured to different sample rates by dr iving 256Fs/384Fs into audio SYSCLK with setting divider properly (Reg36). adda_osr is used to control the over sample rate clock divider of the DA filter to 128Fs or 64Fs. Performance of 128Fs is be tter than 64Fs but with much higher pow er consumption. Refer to section 12 Appendix A: Stereo I2S Clock Table, page 64 for detailed settings. dac_l_vol & dac_r_vol can be used to control the DAC output volume.

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 15 Track ID: JATR-1076-21 Rev. 1.0 7.6. Mixers The ALC5622 supports four mixers for all audio function requirements:

  • Headphone mixer for 2 channels
  • MONO mixer
  • Speaker mixer
  • ADC record mixer 7.6.1. Headphone Mixer The headphone mixer is used to drive ster eo output, including LINE _OUT_L/R, SPK_OUT, and MONO_OUT (AUXOUT_L/R). The output of the headpho ne mixer can be input to the ADC record mixer. The following signals can be mixed into the headphone mixer:
  • LINE-IN_L/R (Controlled by Reg0A)
  • AUXIN_L/R (Controlled by Reg08)
  • MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
  • Stereo DAC output (Controlled by Reg0C)
  • ADC record mixer output (Controlled by Reg12 & Reg14). When the SPK_OUT source is from the HP_mixer, SPK _OUTP/N can be configured to L/R, L+R, and L/LN by setting spk_outn_source. The HP mixer can be powered down by setting pow_mix_hp_l and pow_mix_hp_r. 7.6.2. MONO Mixer The MONO mixer is used to drive MONO_OUT (AUXOUT_L/R) and SPK_OUT. The output of the MONO mixer can be input to the AD C record mixer. The output of the MONO mixer is two channels with the same signal. The following signals can be mixed into the MONO mixer:
  • LINE-IN_L/R (Controlled by Reg0A)
  • AUXIN_L/R (Controlled by Reg08)
  • MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
  • Stereo DAC output (Controlled by Reg0C)

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 16 Track ID: JATR-1076-21 Rev. 1.0

  • ADC record mixer output (Controlled by Reg12 & Reg14). Note: The MONO mixer can be powered down by setting pow_mix_mono. 7.6.3. Speaker Mixer The speaker mixer is the same as the MONO mixe r and is used to driv e MONO_OUT (AUXOUT_L/R) and SPK_OUT. The output of the speaker mixer can be input to the ADC record mixer. The output of the speaker mixer is two channels with the same signal. The following signals can be mixed into the speaker mixer:
  • LINE-IN_L/R (Controlled by Reg0A)
  • AUXIN_L/R (Controlled by Reg08)
  • MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
  • Stereo DAC output (Controlled by Reg0C) Note: The speaker mixer can be powered down by setting pow_mix_spk. 7.6.4. ADC Record Mixer The ADC record mixer is used to mix analog signals as input to the Stereo ADC for recording. Output of the ADC record mixer can be input to the headphone mixer, MONO mixer, and speaker mixer. The following signals can be mixed into the ADC record mixer:
  • LINE-IN_L/R (Controlled by Reg0A)
  • AUXIN_L/R (Controlled by Reg08)
  • MIC1P/N and MIC2P/N (Controlled by Reg22)
  • Headphone mixer output
  • MONO mixer output
  • Speaker mixer output Note: The ADC record mixer can be power ed down by setting pow_mix_adc_rec_l & pow_mix_adc_rec_r.

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 17 Track ID: JATR-1076-21 Rev. 1.0 7.7. Analog Audio Input Path The ALC5622 supports four Analog Audio Input paths:

  • Line_IN_L/R
  • AUXIN_L/R
  • MIC1
  • MIC2 7.7.1. Line Input LINE_IN_L and LINE_IN_R provide 2-channel stereo single-ended input that can be mixed into any analog output mixer and ADC record mixer. The LINE_IN_L/R volume and mute are controlled by Reg0A. pow_li_l_vol and pow_li_r_vol can be used to power down LINE_IN volume control. LINE_IN_L is pin shared to JD1 and can be configured by lineinl_pin_sharing. LINE_IN_R is pin shared to JD2 and can be configured by lineinr_pin_sharing. 7.7.2. AUXiliary Input AUXIN_L and AUXIN_R provide 2-cha nnel stereo single-ended input that can be mixed into the ADC record mixer and any analog output mixer. AUXIN_L/R volume and mute are controlled by Reg08. pow_auxin_l_vol and pow_auxin_r_vol can be used to power down AUXIN_L/R volume control. 7.7.3. Microphone Input MIC1P/N and MIC2P/N provide 2-cha nnel stereo differential or single- ended input, via mic1_diff_ctrl and mic2_diff_ctrl, that can be mixed into the ADC record mixer, or any an alog output mixer. MIC1P and MIC2P are main inputs when differential mode is disabled. The ALC5622 microphone input boost provides 20/30dB boost, set by mic1_boost_ctrl (for MIC1) and mic2_boost_ctrl (for MIC2). The MIC1/2 volume and mute are controlled by Reg0E. pow_mic1_vol & pow_mic2_vol can be used to power down the MIC1/2 volume control path. pow_mic1_admixer & pow_mic2_admixer can be used to power down the MIC1/2 admixer path.

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 18 Track ID: JATR-1076-21 Rev. 1.0 7.8. Analog Audio Output Data Path The ALC5622 supports three Analog Audio output paths:

  • SPK_OUT_L/R
  • LINE_OUT_L/R
  • MONO_OUT(AUX_OUT_L/R). 7.8.1. Speaker Output SPK_OUT_L/R provides mono differential output and can be configured to dual Single-Ended output The SPK_OUT source is selected in spk_vol_in_sel. Sources are shown below:
  • Vmid
  • Headphone left mixer
  • Speaker mixer
  • MONO mixer The Speaker-out of the ALC5622 supports Class AB and Class D type amp lifiers. The type can be set in spk_out_type_sel. If a Class D amplif ier is selected, the driver must set Index-46=CF00’h. As the power voltage of SPKVDD is usually hi gher than AVDD, the ALC5622 must set Class AB Vmid ratio at spk_ampAB_ctrl (Reg40[14:12]) and Class D Vmid ra tio at spk_ampD_ctrl (R eg40[11:10]) in order to extend the output level. The SPK_OUT volume and mute are controlled by Reg02. Also, Reg3E[12]: pow_spk can be used to power down SPK output. pow_clsab (Reg3C[15]) is us ed to power down the Class AB Amplifier and pow_clsd (Reg3C[14]) is used to power down the Class D Amplifier. SPK_OUT supports a softmute func tion and a zero cross detect func tion. The soft-mute function is enabled by sp_l_soft-mute_en/sp_r_soft-mute_en, and the zero cross detect function is enabled by sp_l_dezero/sp_r_dezero. If spk_vol_in_sel=10b or 11b, SPK_OUT is configured to differential, only sp_l_soft-mute_en and sp_l_dezero can be used to control the soft-mute and zero cross of SPK_OUT.

from Line_l_in_sel & Line_r_in_sel (Reg1C[9:8]).

  • Vmid
  • Headphone mixer The LINE_OUT_L/R volume and mute are controlled by Reg04. pow_Line_l_vol (Reg3E[10]) and pow_Line_r_vol (Reg 3E[9]) can be used to power down the LINE output volume. LINE_OUT supports soft-mute and zero cross-detect function, which can be individually enabled at Line_l_soft-mute_en/Line_r_soft-mute_en and Line_l_dezero/Line_r_dezero. 7.8.3. MONO Output MONO_OUT provides one-channel di fferential MONO_OUT or stereo single-ended AUXOUT_L/R via se_diff_auxout. The MONO/AUXOUT source can be selected from Reg1C[7:6], mono_in_sel. Sources are shown below.
  • Vmid
  • Headphone mixer (L+R)
  • Speaker mixer
  • MONO mixer The MONO/AUXOUT output signal depends on the setting of se_diff_auxout & mono_in_sel.

Table 9. MONO/AUXOUT Output Signal Table

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 20 Track ID: JATR-1076-21 Rev. 1.0 MONO/AUXOUT volume and mute are controlled by Reg08. pow_aux_outl_vol (Reg3E[14]) and pow _aux_outr_vol (Reg3E[13])can be used to power down the volume of MONO/AUXOUT. If MONO/AUXOUT is configured to stereo Single-Ended AUXOUT, the soft-mute and zero cross detect function of MONO/AUXOUT can be enabled at AUXO_l_soft-mute_en/AUXO_r_soft-mute_en and AUXO_l_dezero/AUXO_r_dezero. If MONO/AUX is configured to mono differe ntial MONO_OUT, only AUXO_l_soft-mute_en and AUXO_l_dezero can be used to control soft-mute and zero cross of MONO/AUXOUT. 7.9. A VC Control The Automatic Volume Control (AVC) function dynami cally adjusts the input signal quantized by the ADC to an expected sound level by setting THma x, THmin, and THnonact (see Figure 14 AVC Behavior, page 21. When the average level of input signal is higher th an THmax, the AVC will decrease the selected analog gain to attenuate the quantized Pulse Code Modulation (PCM) signal to a lower amplitude than THmax. When the average level of input signal is lower th an THmin and higher than Thnonact., the AVC will increase the selected analog gain to amplify the input signal. Th e quantized Pulse Code Modulation (PCM) signal is then set to a higher amplitude than THmin. The quantized PCM has an average level between THmin and THmax. In order not to output a strong amplified signal when the gain detector input level is transiting from a very small signal to a normal signal, the AVC block will li mit the selected analog gain to unit gain (=0dB) when the input level of the gain detector is lower than THnonact. The AVC reference source channel and target channel can be individually set by Reg68: AVC Control.

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 22 Track ID: JATR-1076-21 Rev. 1.0 7.10. Hardware Sound Effects The Sound Effect block is composed of Pseudo Ster eo, Spatial 3D, and Equalizer blocks. The Pseudo Stereo block is used to convert a MONO source into virtualized stereo output. The Spatial 3D block is a surround sound generator with adjustab le amplitude (Gain) and surroun d depth (Ratio). The Equalizer block can be used to compensate fo r speaker response, or to make e nvironment sound effects, e.g., ‘Pub’, ‘Live’, ‘Rock’,… etc.. 7.10.1. Equalizer Block The Equalizer block cascades 5 bands of equalizer to compensate for speaker response and to emulate environment sound. One high-pass filter cascaded in the front end is used to drop low frequency tone, which has a larger amplitude and may damage a mini speaker. The high-pass filter can also be used to adjust Treble strength with ga in control. A low-pass filter with gain control can adjust the Bass strength. Three bands of bi-quad ban dpass filters are used to emulate environment sounds. To avoid PCM sample saturation, a digital volume control has 0 ~18dB attenuation in the front of equalizer is required. A –3 ~ +18dB digital gain control after equalizer is used to compensate PCM output to suitable level. The Equalizer source of the ALC5622 can be selected from DAC or ADC. If Equalizer parameters will be dynamically changed, the driver should set EQ Mode Ch ange enable and disable after the EQ parameters have been set to new values. 7.10.2. Pseudo Stereo and Spatial 3D Sound There are two spatial effects in post-processing; the Ps eudo-Stereo Effect + Spatial Effect, and the Stereo Expansion Effect. The Pseudo-Stereo Effect + Spatial Effect convert s a MONO signal to a stereo signal by changing the phase and amplitude of the original signal followed by enhancing the spatial effect. The Stereo Expansion Effect enhances the spatial effect when the input signal is Stereo.

support MCLK during register access. Table 10. Addressing Setting Figure 15. Data Transfer Over I 2C Control Interface

Table 11. Write WORD Protocol Table 12. Read WORD Protocol The ALC5622 will return ‘0000h’ when odd-addressed and unimplemented registers are read. both Reg26 and Reg3A/3C/3E are set to ‘Enable’.

gpio_pin_sharing =00’b. When the GPIO is configured as Input, the status will be indicated in Reg54[1]. status can be read in Reg54[1]. (Line_Out, Speaker Out, and AUXOUT_L/R). configured in the Reg-5Ah Jack Detect Control Register. to ‘1’ to clear each IRQ status flag. Figure 16. GPIO Implementation

  • Sticky by setting Reg50
  • Changed polarity by setting Reg4E
  • Wake-up by setting Reg52 The driver can write each bit of Reg54 to ‘1’ to clear each IRQ status flag. QS R Wake (52h. n) Config (4Ch. n) Sticky (50h . n) Write 0 ? to GPIO Status (54h . n) GPIO Status (54h . n) Polarity (4Eh. n) Other 15 bits Sticky (50h . n) Config (4Ch. n) IRQout_ Inv (5Eh. 0) gpio 2_pin_ sharing (56h. [1:0]) 01: Close Others : Open IRQ JD1/JD2 QS R Wake (52h. n) Config (4Ch. n) Write 0 ? to GPIO Status (54h . n) Sticky (50h . n) GPIO Status (54h . n) Polarity (4Eh. n) 0 : Active Low 1: A c t i v e H i g h ALC 206 Internal Signal Sticky (50h . n) Config (4Ch. n) JD Controller Others JD_ sel (5Ah. 15:14) 0 : Active Low 1: A c t i v e H i g h

Figure 17. Jack Detect and IRQ Logic

Accessing odd numbered registers, or reading unimplemented registers, will return a 0. Table 13. Reg-00h: Reset Table 14. Reg-02h: Speaker Output Volume

Table 15. Reg-04h: Line_Out Output Volume

Table 16. Reg-06h: MONO_OUT/AUXOUT Volume

13 RW 0’h AUXOUT Left Channel Softmute Enable

5 RW 0’h AUXOUT Right Channel Softmute Enable

Table 17. Reg-08h: AUXIN Volume

Table 18. Reg-0Ah: LINE_IN Volume Table 19. Reg-0Ch: STEREO DAC Volume

Table 20. Reg-0Eh: MIC Volume Table 21. Reg-10h: MIC Routing Control

Table 22. Reg-12h: ADC Record Gain

13 RW 1’h Mute Left Gain Output to MONO Mixer Control

12 RW 1’h Mute Right Gain Output to MONO Mixer Control

Table 23. Reg-14h: ADC Record Mixer Control

Table 24. Reg-16h: Avol Soft Volume Control Time Table 25. Reg-1Ch: Output Mixer Control

00 RN -(L+R)

01 RP L+R

10 LN -(L+R)

11 Vmid

Table 26. Reg-22h: Microphone Control Table 27. Reg-34h: Audio Interface

Table 28. Reg-36h: Stereo AD/DA Clock Control

Table 29. Reg-38h: Companding Control Table 30. Reg-3Ah: Power Management Addition 1 detailed de-pop sequence information.

Table 31. Auxiliary Output Amplifier Configuration Table 32. Reg-3Ch: Power Management Addition 2 Note: This bit works only if Index-39[11]=0b. Reserved 11 RW 0’h Reserved.

Table 33. Reg-3Eh: Power Management Addition 3

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 39 Track ID: JATR-1076-21 Rev. 1.0 Figure 18. Power Control to MIC Input Table 34. Reg-40h: Additional Control Register

Description

se_diff_auxout 15 RW 0’b AUXOUT Selection of Single-End or Differential Mode 0: Differential Mode 1: Single-End Mode spk_ampAB_ctrl 14:12 RW 5’h Speaker Class AB Amplifier V MID Ratio Control (Output Gain Control) 000: 2.25 Vdd 001: 2.00 Vdd 010: 1.75 Vdd 011: 1.5 Vdd 100: 1.25 Vdd 101: 1 Vdd Others: Not allowed spk_ampD_ctrl 11:10 RW 0’h Speaker Class D Amplifier V MID Ratio Control (Output Gain Control) 00: 1.75 Vdd 01: 1.5 Vdd 10: 1.25 Vdd 11: 1.0 Vdd dac_hpf_en 9 R/W 1’h STEREO DAC High Pass Filter 0: Disable 1: Enable adc_hpf_en 8 R/W 1’h STEREO ADC High Pass Filter 0: Disable 1: Enable Reserved 7:6 R 0’h Reserved digital_vol_boost 5:4 RW 0’b Digital V olume Boost 00: 0dB 01: 6dB 10: 12dB 11: 18dB se_btl_clsab 3 RW 0’b Speaker Class AB selection of Single-End or Bridge-Tied Load (BTL). 0: Differential Mode 1: Single-End Mode Reserved 2:0 RW 0’h Reserved

Table 35. Reg-42h: Global Clock Control Register Table 36. Reg-44h: PLL Control Register

Table 37. PLL Clock Setting Table for 48K: (Unit: MHz) Table 38. PLL Clock Setting Table for 44.1K: (Unit: MHz) Table 39. Reg-4Ch: GPIO_Output Pin Control

Table 40. Reg-4Ch: GPIO Pin Configuration Table 41. Reg-4Eh: GPIO Pin Polarity

Table 42. Reg-50h: GPIO Pin Sticky Table 43. Reg-52h: GPIO Pin Wake-Up

Table 44. Reg-54h: GPIO Pin Status Table 45. Reg-56h: Pin Sharing Table 46. Reg-58h: Over-Current Status

Table 47. Reg-5Ah: Jack Detect Control Register Table 48. Reg-5Eh: MISC Control disabled before playback/record. Reserved 14:4 RW 0’b Reserved.

Table 49. Reg-60h: Stereo and Spatial Effect Block Control Spatial coefficients cannot be modified when Spatial is enabled.

Table 50. Reg-62h: EQ Control 0: Disabled and reset 1: Enabled. 0: Disabled and reset 1: Enabled. 0: Disabled and reset 1: Enabled. 0: Disabled and reset 1: Enabled. Table 51. Reg-66h: EQ Mode Change Enable register to 'Enable'. After the EQ parameter has been changed, the driver should set this register to 'Disable'.

Table 52. Reg-68h: AVC Control Table 53. Reg-6Ah: Index Address Table 54. Reg-6Ch: Index Data

Table 55. Index-00h: EQ Band-0 Coefficient (LP0: a1) Note: For low pass filter for Bass control – LP0 has filter coefficient a1 and gain Ho must be set (see Table 56). Table 56. Index-01h: EQ Band-0 Gain (LP0: Ho) Table 57. Index-02h: EQ Band-1 Coefficient (BP1: a1) Table 58. Index-03h: EQ Band-1 Coefficient (BP1: a2) Table 59. Index-04h: EQ Band-1 Gain (BP1: Ho)

Table 60. Index-05h: EQ Band-2 Coefficient (BP2: a1) Table 61. Index-06h: EQ Band-2 Coefficient (BP2: a2) Table 62. Index-07h: EQ Band-2 Gain (BP2: Ho) Table 63. Index-08h: EQ Band-3 Coefficient (BP3: a1) Table 64. Index-09h: EQ Band-3 Coefficient (BP3: a2)

Table 65. Index-0Ah: EQ Band-3 Gain (BP3: Ho) Table 66. Index-0Bh: EQ Band-4 Coefficient (HPF: a1) Table 67. Index-0Ch: EQ Band-4 Gain (HPF: Ho) Table 68. Index-11h: EQ Input Volume Control

Table 69. Index-12h: EQ Output Volume Control Table 70. Index-21h: Auto Volume Control Register 1 Table 71. Index-22h: Auto Volume Control Register 2 Table 72. Index-23h: Auto Volume Control Register 3

Table 73. Index-24h: Auto Volume Control Register 4 Table 74. Index-25h: Auto Volume Control Register 5 Table 75. Index-39h: Digital Internal Register

15 RW Pad Drive Capability

12 RW Power Gating Enable

11 RW Vref Power Control Enable

Table 76. Index-46h: Cla ss D Internal Register

15 RW Class D Speaker (pos) 0: Power down 1: Power on

14 RW Class D Speaker (neg) 0: Power down 1: Power on

11 RW Class D VREF Generator 0: Power down 1: Power on

10 RW Class D Ramp Generator 0: Power down 1: Power on

9 RW Class D Clock Gen 0: Power down 1: Power on

8 RW Class D BIAS Generator 0: Power down 1: Power on

Table 77. Reg-7Ch: VENDOR ID 1 Table 78. Reg-7Eh: VENDOR ID 2

  1. Electrical Characteristics

Table 79. Absolute Maximum Ratings Table 80. Recommended Operating Conditions Table 81. Static Characteristics Note: DVDD=3.3V , Tambient=25°C, with 50pF external load.

Table 82. Analog Performance Characteristics

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 57 Track ID: JATR-1076-21 Rev. 1.0 Parameter Min Typ Max Units BTL Class D Speaker Amplifier Output Power (8Ω Load) @4.2V with THD+N=40dB @5V with THD+N=40dB 1000 1300 mW mW BTL Class AB Speaker Amplifier Output Power (8Ω Load) @4.2V with THD+N=40dB @5V with THD+N=40dB 1060 1300 mW mW BTL Speaker Amplifier Efficiency (fIN=1KHz, 8Ω Load, Output Power=900mW) Class AB Class D BTL Speaker Amplifier THD+N Class AB_Strong (8Ω Load) Output Power=350mW Output Power=700mW Class D Output Power=350mW Output Power=700mW dB dB dB dB BTL Speaker Amplifier THD+N Class AB_Weak (10KΩ/50pF Load) -85 dB BTL Speaker Amplifier SNR Class AB_Weak (10KΩ/50pF Load) -90 dB BTL Speaker Amplifier PSRR (217Hz) - 50 - dB Power Supply Current IDDA (Analog Block) IDDD (Digital Block) mA mA Power Down Current IDDA (Analog Block) IDDD (Digital Block) µA µA MICBIAS Output V oltage 0.75*Avdd Setting 0.9*Avdd Setting 2.475 2.97 V V MICBIAS Drive Current 2 - 3 mA Note: Standard test conditions Tambient=25°C, DBVDD=DCVDD=AVDD=3.3V , SPKVDD=5V 1kHz input sine wave; PCM Sampling frequency=48kHz; 0dB=1Vrms, Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation; EQ and 3D disabled.

Figure 19. I 2C Control Interface Table 83. I 2C Timing Note: Condition: MCLK > 8MHz.

Figure 20. Timing of I 2S Master Mode Table 84. Timing of I 2S Master Mode

Figure 21. I 2S Slave Mode Timing Table 85. I 2S Slave Mode Timing

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 61 Track ID: JATR-1076-21 Rev. 1.0 10. Application Circuit

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 62 Track ID: JATR-1076-21 Rev. 1.0 11. Mechanical Dimensions

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 63 Track ID: JATR-1076-21 Rev. 1.0

I2S Audio Codec + 1.3W Class AB/D Mono Speaker Amplifier 64 Track ID: JATR-1076-21 Rev. 1.0 12. Appendix A: Stereo I2S Clock Table MCLK PLL Output Sel_sysclk DA/AD Clock DAC/ADC Sample Rate (Hz) (Hz) Reg42[15] Reg36 LRCK(Hz) BCLK=64fs BCLK=32fs

24576000 X 0’b

X 24576000 1’b 0x386F 0x3C6B

16384000 X 0’b

X 16384000 1’b 0x366D 0x3A69 8000 X 24576000 1’b 0x366D 0x3A69

18432000 X 0’b

X 18432000 1’b 0x286F 0x2C6B 12000 X 24576000 1’b 0x286F 0x2C6B X 16384000 1’b 0x266D 0x2A69 16000 X 24576000 1’b 0x266D 0x2A69 X 18432000 1’b 0x186F 0x1C6B 24000 X 24576000 1’b 0x186F 0x1C6B X 16384000 1’b 0x166D 0x1A69 32000 X 24576000 1’b 0x166D 0x1A69 X 18432000 1’b 0x086F 0x0C6B 48000

22579200 X 0’b

X 22579200 1’b 0x366D 0x3A69

16934400 X 0’b

X 16934400 1’b 0x286F 0x2C6B 11025 X 22579200 1’b 0x266D 0x2A69 X 16934400 1’b 0x186F 0x1C6B 22050 X 22579200 1’b 0x166D 0x1A69 X 16934400 1’b 0x086F 0x0C6B 44100

Table 86. Ordering Information Note 1: See page 5 for Green package and version identification. Note 2: Above parts are tested under AVDD=3.3V .