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Ultra-Low Power Audio CODEC for Mobile Devices Datasheet Rev. 0.1 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com
I2S Audio CODEC for Mobile Devices ii Rev. 0.1 COPYRIGHT © 2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC5616 Audio Codec IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.
I2S Audio CODEC for Mobile Devices iii Rev. 0.1
REVISION HISTORY
Revision Release Date Summary 0.1 2012/7/29 Preliminary version
I2S Audio CODEC for Mobile Devices iv Rev. 0.1 Table of Contents
I2S Audio CODEC for Mobile Devices v Rev. 0.1
I2S Audio CODEC for Mobile Devices vi Rev. 0.1
Two-Channel Audio Hub/CODEC and SounzRealTM Digital Sound Effect for Mobile Devices 1 Rev. 0.1 1. General Description The ALC5616 is a high performance, low power, stereo channel I2S interface audio CODEC. The transmitted data can from analog input or digital microphone input. Also the received data can to headphone output, line output. The ALC5616 features an ultra low power cap-free headphone amplifier. It consumes only less than 6.5mW power during playback, providing mobile system longer battery life under headphone listening mode. The integrated DRC(Dynamic Range Controller) and 7-band parametric Equalizer provide further digital sound processing capability of audio playback paths. The DRC in ALC5616 continuously monitors the DAC output level. When the power level is low, it increases the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. It ensures the maximum/consistent signal amplitude without producing audio clipping and speaker damage. The 7-band parametric Equalizer contains 7 independent filters with programmable gain, center frequency and bandwidth to tailor the frequency characteristics of embedded speaker system according to user preferences. For microphone recording, the DRC in ALC5616 can be used as AGC(Auto Gain Controller) to maintain a constant recording volume. Besides, a dynamic wind reduction filter is built in on recording path. The filter can detect the level of wind noise and on/off dynamically to keep the recording quality. ALC5616 only requires two voltage supplies and consume ultra low power, making it ideal for mobile devices.
I2S Audio CODEC for Mobile Devices 2 Rev. 0.1 2. Features Analog Features: Digital-to-Analog Converter with 98dBA SNR Analog-to-Digital Converter with 94dBA SNR Differential analog microphone inputs with boost pre-amplifiers and low noise microphone bias +20/+24/+30/+35/+40/+44/+50/+52 dB microphone boost gain MIC input to ADC with 50dB boost gain, SNR > 66dBA and THD+N < -65dB Adjustable MICBIAS (0.9*MICVDD or 0.75*MICVDD) Stereo line inputs Line input to ADC with 0dB gain, SNR >= 94dBA, THD+N <= -83dB Stereo line outputs DAC to line output with 0dB gain, SNR >= 98dBA, THD+N <= -86dB Stereo Cap-Free headphone amplifier with ultra low power consumption for playback 20mW/CH (AVDD=CPVDD=1.8V, THD+N <= -80dB, 16Ohm Load) Playback power consumption <= 6.5mW (AVDD=VBVDD=CPVDD=1.8V, 16Ohm, With I2S Clock, Playback Silence) Playback power consumption <= 14mW (AVDD=VBVDD=CPVDD=1.8V, 16Ohm, With I2S Clock, Playback 1mW/CH) Audio jack detection Inside PLL can receiver wide range clock input Digital Features: One 24bit/8kHz ~ 192kHz I2S/PCM interface for stereo DAC and stereo ADC I2C control interface 7-bands flexible equalizer (EQ) for DAC path or ADC path Enhanced DRC(Dynamic Range Control)/AGC(Auto Gain Control) function for DAC path or ADC path One wind noise reduction filter Zero detection and soft volume for pop noise suppression 3. System Application Smart Phones Tablet
- Function Block and Mixer Path
Figure 1. Block Diagram
Figure 2. Audio Mixer Path
Figure 3. Digital Mixer Path
Figure 4. Pin Assignments
Table 1. Digital I/O Pins Table 2. Analog I/O Pins
Table 3. Filter/Reference
Table 4. Power/Ground
performance, our design setting is show on below. Table 5. Power Supply for Best Performance *1.2V DCVDD was generated by internal LDO. To prevent all power down leakage, needs keep all power supply on. Table 6. Power Supply Condition for Power Down Leakage
I2S Audio CODEC for Mobile Devices 11 Rev. 0.1 7.2. Power Supply On/Off Sequence To prevent pop noise and make sure function work normally, following power on and off sequence are recommended. Power On Sequence: (Sequentially turn on power pins) 1. DBVDD/AVDD/DACREF/CPVDD power supply on. 2. MICVDD power supply on. 3. Software starts to initialize ALC5616. Power Off Sequence: (Sequentially turn off power pins) 1. Power down all Codec function (Write 0x0000’h to register MX-00’h). 2. MICVDD power supply off. 3. DBVDD/AVDD/DACREF/CPVDD power supply off
There are 2 types of reset operation: power on reset (POR) and register reset. Table 7. Reset Operation control registers and logic. power on reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip. Table 8. Power-On Reset Voltage
- When DCVDD is supplied 1.2V
When MX-00h is wrote, all registers become to default value.
clock of each block and setup each divider. device. The ratio of BCLK and LRCK can set by register – MX73. Figure 5. Audio Clock Tree
source of the PLL can be set to MCLK, BCLK1 by setting register. The S/W driver can set up the PLL to output a frequency to match the requirement of system clock. Table 9. Clock Setting Table for 48K (Unit: MHz) Table 10. Clock Setting Table for 44.1K (Unit: MHz)
Table 11. The relative of SYSCLK/BCLK/LRCK distribution. Refer to Figure5. Audio Clock Tree, for details.
The ALC5616 provides 2-channel analog DACs for playback and 2-channel analog ADCs for recording. pass to analog ADCs or stereo line inputs to analog ADCs. ad_gain_l (MX-1C[14:8]) and ad_gain_r (MX-1C[6:0]). Figure 13. 2-Channel Recording Path
signal to headphone output or line output. Figure 14. 4-Channel Playback Path
I2S Audio CODEC for Mobile Devices 21 Rev. 0.1 7.6.3. Mixers The ALC5616 has analog mixers build-in. Output mixer - OUTMIXL/R The stereo analog mixer can do mixing for DAC output and analog input. The mixer output is mainly for headphone output and line output. Each input path has individual mute control to the mixer block in MX-4D ~ MX-52. pow_outmixl and pow_outmixr can be used to power on/off OUTMIXL/R Record mixer – RECMIXL/R The stereo analog mixer can do mixing for analog input and OUTMIX output. The mixer output is for ADC input. Each input path has individual mute control to the mixer block in MX-3B ~ MX-3E. pow_recmixl and pow_recmixr can be used to power on/off RECMIXL/R.
I2S Audio CODEC for Mobile Devices 22 Rev. 0.1 7.7. Analog Audio Input Port The ALC5616 has two types analog input ports: microphone input and line input. IN1P The IN1P is a microphone type input port. The input port is single-ended type input. The microphone input port has its microphone bias and microphone boost. The low noise microphone bias can improve recording performance and enhance recording quality. Build-in short current detection scheme can be used for switch detection. Multi-steps microphone boost gain set by sel_bst1 (MX-0D[15:12]) is easy to use for microphone application. Pow_bst1 can be used to power down the MIC1 boost and pow_micbias1 can be used to power down the microphone bias 1. IN2P/N The IN2P/N is a dual type input port: microphone input and line input. Microphone input can be configured to differential input or single-ended input by MX-0D[6]. Multi-steps microphone boost gain set by sel_bst2 (MX-0D[11:8]) is easy to use for microphone application. Pow_bst2 can be used to power down the MIC2 boost. As line input, it has volume control for tuning by MX-0F[12:8] and MX-0F[4:0].
I2S Audio CODEC for Mobile Devices 23 Rev. 0.1 7.8. Analog Audio Output Port The ALC5616 supports two type output ports: HPO_L/R The headphone output of ALC5616 is a stereo output with cap-free type headphone amplifier. It does not need to connect external capacitor and can connect to earphone device directly. The headphone output source can mix from output mixer (OUTMIX) or DAC by setting MX-45. The front stage of headphone output has volume control and gain control. The volume range is from +12dB to -46.5dB with 1.5dB/step by MX-02. En_l_hp and en_r_hp (MX-63[7/6]) can be used to power on/off Headphone Amplifier, and pow_hpo_voll and pow_hpo_volr (MX-66[11/10]) can be used to power on/off headphone volume control. In addition, pow_pump_hp (MX-8E[3]) can be used to power on/off charge pump circuit for Headphone Amplifier. Line_OUT_L/R/P/N The output type is line type output. The output is a stereo single ended output or mono differential output. The input can be selected from OUTVOL or DAC output by setting MX-53[15:12]. The front stage of LOUT output has gain control for attenuation. The gain control is 0dB or -6dB by MX-53[11].
I2S Audio CODEC for Mobile Devices 24 Rev. 0.1 7.9. Multi-Function Pins There are two multi-function pins in ALC5616. For different function on pin is controlled by register. You need to set the right register settings for multi-function pin by your application. GPIO1/IRQ – Pin 38 The pin default is GPIO function. If want to change to IRQ output, write MX-C0[15] to 1’b that will switch to IRQ function. IN2N/JD2 – Pin 4 In IN2N microphone input function, need to disable JD2 jack detection function – MX-64[1] = 0’b. In JD2 jack detection function, need to set these register settings: 1. Power on JD2 – MX-64[1] = 1’b 2. Mute IN2 to each analog mixer - (RECMIXL/RECMIXR/OUTMIXR). 3. Set MX-64[4] = 1’b 4. Enable JD2 as jack detection source – MX-BC[11:9] = 011’b
return to the target level, need to set the pre-gain to achieve. Figure 17. DRC/AGC for Playback/Recording Mode
the input signal will be boosted to target level. Figure 18. DRC/AGC for Noise Gate Mode
I2S Audio CODEC for Mobile Devices 28 Rev. 0.1 7.11. Equalizer Block The equalizer block cascades 7 bands of equalizer to tailor the frequency characteristics of embedded speaker system according to user preferences and to emulate environment sound. The 7 bands equalizer includes two high pass filter, four band pass filter and one low pass filter. One high pass filter cascaded in the front end is used to drop low frequency tone, The tone has a large amplitude and may damage a mini speaker. The high pass filter can be used to adjust Treble strength with gain control. One low pass filter with gain control can adjust the Bass strength. Four bands of bi-quad band pass filters are used to emulate environment sounds, e.g., ‘Pub’, ‘Live’, ‘Rock’,… etc.. The gain, center frequency and bandwidth of each filter are all programmable. 7.12. Wind Filter with Dynamic Wind Noise Detector 7.12.1. Wind Filter The wind filter is implemented by a high pass filter. The wind filter is mainly for ADC recording used. The cut-off frequency of wind filter is programmable and is varied according to different sample rate. The filter is used to remove DC offset at normal condition, and to remove wind noise at application mode. Wind filter setting procedure: Step1: Disable wind filter – MX-D3[15] Step2: Select target sample rate – MX-D3[14:12] and MX-D3[10:8] Step3: Fine tune wind filter Fc – MX-D4[13:8] and MX-D4[5:0] Step4: Enable wind filter – MX-D3[15] The following table is shown the Fc with sample rate selection. For the formula of Fc calculation is also shown as: Fc = (Fs * tan-1(a/(2-a))) / π Where: Sample rate = 8K/12K/16K (MX-D3[14:12] & [10:8]), a = 2-6 + n * 2-6 (n is MX-D4[13:8] & [5:0]) Sample rate = 24K/32K (MX-D3[14:12] & [10:8]), a = 2-7 + n * 2-7 (n is MX-D4[13:8] & [5:0])
Table 12. Sample Rate with filter coefficient for Wind Filter
I2S Audio CODEC for Mobile Devices 30 Rev. 0.1 MX-D4 n L & R Channel Sample Rate Setting 8K 16K 32K 44.1K 48K
Table 13. Address Setting (0x36h) Figure 19. Data Transfer Over I2C Control Interface
Table 14. Write WORD Protocol Table 15. Read WORD Protocol
Figure 22. JD Source Selection
I2S Audio CODEC for Mobile Devices 35 Rev. 0.1 The jack detect function can be used to turn-on or turn-off the related output ports. When jack detect pin is trigged, the selected output port s will turn -on or turn -off. For example on HP and LOUT auto switch when JD is trigger. Setting procedure: 1. Select JD source: use sta_jd1_1 as JD status. MX-BC[11:9] = 001’b 2. Set target behavior by JD active – HP & LOUT auto switch when JD is triggered. MX-BB[11:10] = 11’b & MX-BB[3:2] = 10’b 3. When JD status is low, HP_OUT is mute and LOUT is un-mute. When JD status is low go high, HP is un-mute and LOUT is mute. Note: For HP and SPK jack switch function, driver need to turn-on DAC to HP path and DAC to LOUT path first. The register control of MX-BB is only do mute/un-mute function for HP and SPK.
66h. Each particular block will only be active when each bit of each register is set to enable. Figure 23. Power Management
ALC5616 register map as shown as following and accessing unimplemented registers will return a 0. Table 16. Register Map
1 I2S & DAC & ADC & Power Control MX-61h 0x0000’h
2 Digital Filter Power Control MX-62h 0x0000’h
4 MICBST & MICBIAS & JD Power Control MX-64h 0x0000’h
5 OUTMIX & RECMIX Power Control MX-65h 0x0000’h
6 OUTVOL & HPOVOL & INVOL Power Control MX-66h 0x0000’h
I2S Audio CODEC for Mobile Devices 38 Rev. 0.1 Type Name Description Register Address Reset State ADC/DAC Clock-2 ADC/DAC Clock Control-2 MX-74h 0x0C00’h Global Clock Global Clock Global Clock Control MX-80h 0x0000’h PLL-1 PLL Control-1 MX-81h 0x0000’h PLL-2 PLL Control-2 MX-82h 0x0000’h HP Amp HP HP Amp Control 1 MX-8Eh 0x0004’h HP Amp Control 2 MX-8Fh 0x1100’h MICBIAS MICBIAS MICBIAS Control MX-93h 0x2000’h JD JD Jack Detection Control MX-94h 0x0200’h EQ EQ-1 EQ Control-1 MX-B0h 0x2080’h EQ-2 EQ Control-2 MX-B1h 0x0000’h EQ-Parameter EQ Low Pass Filter – a1 PR-A0h 0x1C10’h EQ-Parameter EQ Low Pass Filter – H0 PR-A1h 0x01F4’h EQ-Parameter EQ Band Pass Filter 1 – a1 PR-A2h 0xC5E9’h EQ-Parameter EQ Band Pass Filter 1 – a2 PR-A3h 0x1A98’h EQ-Parameter EQ Band Pass Filter 1 – H0 PR-A4h 0x1D2C’h EQ-Parameter EQ Band Pass Filter 2 – a1 PR-A5h 0xC882’h EQ-Parameter EQ Band Pass Filter 2 – a2 PR-A6h 0x1C10’h EQ-Parameter EQ Band Pass Filter 2 – H0 PR-A7h 0x01F4’h EQ-Parameter EQ Band Pass Filter 3 – a1 PR-A8h 0xE904’h EQ-Parameter EQ Band Pass Filter 3 – a2 PR-A9h 0x1C10’h EQ-Parameter EQ Band Pass Filter 3 – H0 PR-AAh 0x01F4’h EQ-Parameter EQ Band Pass Filter 4 – a1 PR-ABh 0xE904’h EQ-Parameter EQ Band Pass Filter 4 – a2 PR-ACh 0x1C10’h EQ-Parameter EQ Band Pass Filter 4 – H0 PR-ADh 0x01F4’h EQ-Parameter EQ High Pass Filter 1 – a1 PR-AEh 0x1C10’h EQ-Parameter EQ High Pass Filter 1 – H0 PR-AFh 0x01F4’h EQ-Parameter EQ High Pass Filter 2 – a1 PR-B0h 0x2000’h EQ-Parameter EQ High Pass Filter 2 – a2 PR-B1h 0x0000’h EQ-Parameter EQ High Pass Filter 2 – H0 PR-B2h 0x2000’h DRC/AGC DRC/AGC-1 DRC/AGC Control-1 MX-B4h 0x2206’h DRC/AGC-2 DRC/AGC Control-2 MX-B5h 0x1F00’h DRC/AGC-3 DRC/AGC Control-3 MX-B6h 0x0000’h Jack Detection JD-1 Jack Detection Control-1 MX-BBh 0x0000’h JD-2 Jack Detection Control-2 MX-BCh 0x0000’h IRQ IRQ-1 IRQ Control-1 MX-BDh 0x0000’h IRQ-2 IRQ Control-2 MX-BEh 0x0000’h Flag Status Status GPIO & Internal Status MX-BFh 0x0000’h GPIO GPIO-1 GPIO Control-1 MX-C0h 0x0100’h GPIO-2 GPIO Control-2 MX-C1h 0x0000’h Wind Filter Control-1 Wind Filter Control 1 MX-D3h 0xB320’h Control-2 Wind Filter Control 2 MX-D4h 0x0000’h SVOL & ZCD SVOL & ZCD Soft Volume and ZCD Control MX-D9h 0x0809’h General Control General Control 1 MX-FAh 0x0010’h ADC/DAC RESET Control PR-3Dh 0x2800’h Vendor ID ID Vendor ID MX-FEh 0x10EC’h
Table 17. MX-00h: S/W Reset & Device ID Note: Writes to this register will reset all registers to their default values. Table 18. MX-02h: Headphone Output Control
I2S Audio CODEC for Mobile Devices 40 Rev. 0.1 Name Bits Read/Write Reset State Description Vol_hpor 5:0 R/W 8’h Right Headphone Channel Volume Control (HPOVOLR) 00’h: +12dB 08’h: 0dB 27’h: -46.5dB, with 1.5dB/step Volume Table DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 0 0 12 16 10 -12 32 20 -36 1 1 10.5 17 11 -13.5 33 21 -37.5 2 2 9 18 12 -15 34 22 -39 3 3 7.5 19 13 -16.5 35 23 -40.5 4 4 6 20 14 -18 36 24 -42 5 5 4.5 21 15 -19.5 37 25 -43.5 6 6 3 22 16 -21 38 26 -45 7 7 1.5 23 17 -22.5 39 27 -46.5 8 8 0 24 18 -24 9 9 -1.5 25 19 -25.5
10 A -3 26 1A -27
11 B -4.5 27 1B -28.5
12 C -6 28 1C -30
13 D -7.5 29 1D -31.5
14 E -9 30 1E -33
15 F -10.5 31 1F -34.5
Table 19. MX-03h: LINE Output Control 1
Table 20. MX-05h: LINE Output Control 2 Table 21. MX-0Dh: IN1/2 Input Control
Table 22. MX-0Fh: INL & INR Volume Control
Table 23. MX-19h: DACL1/R1 Digital Volume
I2S Audio CODEC for Mobile Devices 45 Rev. 0.1 3 3 -64.5 56 38 -44.625 109 6D -24.75 162 A2 -4.875 215 D7 4 4 -64.125 57 39 -44.25 110 6E -24.375 163 A3 -4.5 216 D8 5 5 -63.75 58 3A -43.875 111 6F -24 164 A4 -4.125 217 D9 6 6 -63.375 59 3B -43.5 112 70 -23.625 165 A5 -3.75 218 DA 7 7 -63 60 3C -43.125 113 71 -23.25 166 A6 -3.375 219 DB 8 8 -62.625 61 3D -42.75 114 72 -22.875 167 A7 -3 220 DC 9 9 -62.25 62 3E -42.375 115 73 -22.5 168 A8 -2.625 221 DD 10 A -61.875 63 3F -42 116 74 -22.125 169 A9 -2.25 222 DE 11 B -61.5 64 40 -41.625 117 75 -21.75 170 AA -1.875 223 DF 12 C -61.125 65 41 -41.25 118 76 -21.375 171 AB -1.5 224 E0 13 D -60.75 66 42 -40.875 119 77 -21 172 AC -1.125 225 E1 14 E -60.375 67 43 -40.5 120 78 -20.625 173 AD -0.75 226 E2 15 F -60 68 44 -40.125 121 79 -20.25 174 AE -0.375 227 E3 16 10 -59.625 69 45 -39.75 122 7A -19.875 175 AF 0 228 E4 17 11 -59.25 70 46 -39.375 123 7B -19.5 176 B0 229 E5 18 12 -58.875 71 47 -39 124 7C -19.125 177 B1 230 E6 19 13 -58.5 72 48 -38.625 125 7D -18.75 178 B2 231 E7 20 14 -58.125 73 49 -38.25 126 7E -18.375 179 B3 232 E8 21 15 -57.75 74 4A -37.875 127 7F -18 180 B4 233 E9 22 16 -57.375 75 4B -37.5 128 80 -17.625 181 B5 234 EA 23 17 -57 76 4C -37.125 129 81 -17.25 182 B6 235 EB 24 18 -56.625 77 4D -36.75 130 82 -16.875 183 B7 236 EC 25 19 -56.25 78 4E -36.375 131 83 -16.5 184 B8 237 ED 26 1A -55.875 79 4F -36 132 84 -16.125 185 B9 238 EE 27 1B -55.5 80 50 -35.625 133 85 -15.75 186 BA 239 EF 28 1C -55.125 81 51 -35.25 134 86 -15.375 187 BB 240 F0 29 1D -54.75 82 52 -34.875 135 87 -15 188 BC 241 F1 30 1E -54.375 83 53 -34.5 136 88 -14.625 189 BD 242 F2 31 1F -54 84 54 -34.125 137 89 -14.25 190 BE 243 F3 32 20 -53.625 85 55 -33.75 138 8A -13.875 191 BF 244 F4 33 21 -53.25 86 56 -33.375 139 8B -13.5 192 C0 245 F5 34 22 -52.875 87 57 -33 140 8C -13.125 193 C1 246 F6 35 23 -52.5 88 58 -32.625 141 8D -12.75 194 C2 247 F7 36 24 -52.125 89 59 -32.25 142 8E -12.375 195 C3 248 F8 37 25 -51.75 90 5A -31.875 143 8F -12 196 C4 249 F9 38 26 -51.375 91 5B -31.5 144 90 -11.625 197 C5 250 FA
Table 24. MX-1Ch: Stereo1 ADC Digital Volume Control
I2S Audio CODEC for Mobile Devices 47 Rev. 0.1 Vol_adc1_r 6:0 R/W 2F’h Stereo1 ADC Right Channel Volume Control 00’h: -17.625dB 2F’h: 0dB 7F’h: +30dB, with 0.375dB/Step Volume Table: DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 1 1 -17.25 27 1B -7.5 53 35 2.25 79 4F 12 105 69 21.75 3 3 -16.5 29 1D -6.75 55 37 3 81 51 12.75 107 6B 22.5 5 5 -15.75 31 1F -6 57 39 3.75 83 53 13.5 109 6D 23.25 7 7 -15 33 21 -5.25 59 3B 4.5 85 55 14.25 111 6F 24 9 9 -14.25 35 23 -4.5 61 3D 5.25 87 57 15 113 71 24.75 11 B -13.5 37 25 -3.75 63 3F 6 89 59 15.75 115 73 25.5 13 D -12.75 39 27 -3 65 41 6.75 91 5B 16.5 117 75 26.25 15 F -12 41 29 -2.25 67 43 7.5 93 5D 17.25 119 77 27 17 11 -11.25 43 2B -1.5 69 45 8.25 95 5F 18 121 79 27.75 19 13 -10.5 45 2D -0.75 71 47 9 97 61 18.75 123 7B 28.5 21 15 -9.75 47 2F 0 73 49 9.75 99 63 19.5 125 7D 29.25 23 17 -9 49 31 0.75 75 4B 10.5 101 65 20.25 127 7F 30 24 18 -8.625 50 32 1.125 76 4C 10.875 102 66 20.625 25 19 -8.25 51 33 1.5 77 4D 11.25 103 67 21
Table 25. MX-1Eh: ADC Digital Boost Gain Control Table 26. MX-27h: Stereo1 ADC Digital Mixer Control
Table 27. MX-29h: Stereo ADC to DAC Digital Mixer Control
15 R/W 1’h Mute Control for Stereo1 ADC Left Channel to DAC
7 R/W 1’h Mute Control for Stereo1 ADC Right Channel to DAC
Table 28. MX-2Ah: Stereo DAC Digital Mixer Control
14 R/W 1’h Mute Control for DACL1 to Stereo DAC Left Mixer
13 R/W 0’h Gain Control for DACL1 to Stereo DAC Left Mixer
9 R/W 1’h Mute Control for DACR1 to Stereo DAC Left Mixer
8 R/W 0’h Gain Control for DACR1 to Stereo DAC Left Mixer
6 R/W 1’h Mute Control for DACR1 to Stereo DAC Right Mixer
5 R/W 0’h Gain Control for DACR1 to Stereo DAC Right Mixer
1 R/W 1’h Mute Control for DACL1 to Stereo DAC Right Mixer
0 R/W 0’h Gain Control for DACL1 to Stereo DAC Right Mixer
Table 29. MX-3Bh: RECMIXL Control 1
Table 30. MX-3Ch: RECMIXL Control 2 Table 31. MX-3Dh: RECMIXR Control 1
Table 32. MX-3Eh: RECMIXR Control 2
Table 33. MX-45h: HPOMIX Control Table 34. MX-4Dh: OUTMIXL Control 1
Table 35. MX-4Eh: OUTMIXL Control 2 Table 36. MX-4Fh: OUTMIXL Control 3
Table 37. MX-50h: OUTMIXR Control 1
Table 39. MX-52h: OUTMIXR Control 3
I2S Audio CODEC for Mobile Devices 57 Rev. 0.1 Name Bits Read/Write Reset State Description Mu_bst2_outmixr 6 R/W 1’h Mute Control for BST2 to OUTMIXR 0’b: Un-Mute 1’b: Mute Mu_bst1_outmixr 5 R/W 1’h Mute Control for BST1 to OUTMIXR 0’b: Un-Mute 1’b: Mute Mu_inr_outmixr 4 R/W 1’h Mute Control for INR to OUTMIXR 0’b: Un-Mute 1’b: Mute Mu_recmixr_outmixr 3 R/W 1’h Mute Control for RECMIXR to OUTMIXR 0’b: Un-Mute 1’b: Mute Reserved 2:1 R 0’h Reserved Mu_dacr1_outmixr 0 R/W 1’h Mute Control for DACR1 to OUTMIXR 0’b: Un-Mute 1’b: Mute 8.25. MX-53h: LOUTMIX Control Default: F000’h Table 40 MX-53h: LOUTMIX Control Name Bits Read/Write Reset State Description Mu_dacl1_lout 15 R/W 1’h Mute Control for DACL1 to LOUTMIX 0’b: Un-Mute 1’b: Mute Mu_dacr1_lout 14 R/W 1’h Mute Control for DACR1 to LOUTMIX 0’b: Un-Mute 1’b: Mute Mu_outvoll_lout 13 R/W 1’h Mute Control for OUTVOLL to LOUTMIX 0’b: Un-Mute 1’b: Mute Mu_outvolr_lout 12 R/W 1’h Mute Control for OUTVOLR to LOUTMIX 0’b: Un-Mute 1’b: Mute Gain_lout 11 R/W 0’h Gain Control for LOUTMIX 0’b: 0dB 1’b: -6dB reserved 10:0 R/W 0’h Reserved
Table 41. MX-61h: Power Management Control 1 Table 42. MX-62h: Power Management Control 2
15 R/W 0’h Stereo1 ADC Digital Filter Power Control
11 R/W 0’h Stereo1 DAC Digital Filter Power Control
Table 43. MX-63h: Power Management Control 3
Table 44. MX-64h: Power Management Control 4 Table 45. MX-65h: Power Management Control 5
Table 46. MX-66h: Power Management Control 6
Table 47. MX-6Ah: Private Register Index Table 48. MX-6Ch: Private Register Data Table 49. MX-70h: I2S1 Digital Interface Control
Table 50. MX-73h: ADC/DAC Clock Control 1 Table 51. MX-74h: ADC/DAC Clock Control 2
Table 52. MX-80h: Global Clock Control Table 53. MX-81h: PLL Control 1
Table 54. MX-82h: PLL Control 2 Table 55. MX-8Eh: HP Amp Control 1
Table 56. MX-8Fh: HP Amp Control 2 Table 57. MX-93h: MICBIAS Control
Table 58. MX-94h: Jack Detection Control Table 59. MX-B0h: EQ Control 1 sta_hpf2 6 R 0’h EQ High Pass Filter (HPF2) Status. This bit is set if overflow had ever occurred. sta_hpf1 5 R 0’h EQ High Pass Filter (HPF1) Status. This bit is set if overflow had ever occurred.
sta_bpf4 4 R 0’h EQ Band-4 (BP4) Status. This bit is set if overflow had ever occurred. sta_bpf3 3 R 0’h EQ Band-3 (BP3) Status. This bit is set if overflow had ever occurred. sta_bpf2 2 R 0’h EQ Band-2 (BP2) Status. This bit is set if overflow had ever occurred. sta_bpf1 1 R 0’h EQ Band-1 (BP1) Status. This bit is set if overflow had ever occurred. sta_lpf 0 R 0’h EQ Low Pass Filter (LPF) Status. This bit is set if overflow had ever occurred. Table 60. MX-B1h: EQ Control 2 en_hpf2 6 R/W 0’h EQ High Pass 2nd Butterworth Filter (HPF) Control. en_hpf1 5 R/W 0’h EQ High Pass Filter (HPF) Control. en_bpf4 4 R/W 0’h EQ Band-4 (BP4) shelving Filter Control.
en_bpf3 3 R/W 0’h EQ Band-3 (BP3) shelving Filter Control. en_bpf2 2 R/W 0’h EQ Band-2 (BP2) shelving Filter Control. en_bpf1 1 R/W 0’h EQ Band-1 (BP1) shelving Filter Control. en_lpf 0 R/W 0’h EQ Low Pass Filter (LPF) Filter Control. Table 61. MX-B4h: DRC/AGC Control 1
13 R 1’h Update DRC/AGC Parameter
change the DRC/AGC rate, the parameter of DRC/AGC isn’t need be modified. parameter by I2S’s sample rate. Table 62. MX-B5h: DRC/AGC Control 2
7 R/W 0’h DRC/AGC Compression Function Control
I2S Audio CODEC for Mobile Devices 71 Rev. 0.1 Name Bits Read/Write Reset State Description Sel_ratio 6:5 R/W 0’h DRC/AGC Compression Ratio Selection 00’b: 1:1 01’b: 1:2 10’b: 1:4 11’b: 1:8 sel_drc/agc_pre_bst 4:0 R/W 0’h DRC/AGC Digital Pre-Boost Gain (1.5dB/step) 00’h= 0dB 01’h= 1.5dB 02’h= 3dB 03’h= 4.5dB 13’h= 28.5dBFS Others: Reserved Gain table: DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 0 0 -11.625 16 10 -5.625 32 20 0.375 48 30 6.375 64 40 1 1 -11.25 17 11 -5.25 33 21 0.75 49 31 6.75 65 41 2 2 -10.875 18 12 -4.875 34 22 1.125 50 32 7.125 66 42 3 3 -10.5 19 13 -4.5 35 23 1.5 51 33 7.5 67 43 4 4 -10.125 20 14 -4.125 36 24 1.875 52 34 7.875 68 44 5 5 -9.75 21 15 -3.75 37 25 2.25 53 35 8.25 69 45 6 6 -9.375 22 16 -3.375 38 26 2.625 54 36 8.625 70 46 7 7 -9 23 17 -3 39 27 3 55 37 9 71 47 8 8 -8.625 24 18 -2.625 40 28 3.375 56 38 9.375 72 48 9 9 -8.25 25 19 -2.25 41 29 3.75 57 39 9.75 73 49 10 A -7.875 26 1A -1.875 42 2A 4.125 58 3A 10.125 74 4A 11 B -7.5 27 1B -1.5 43 2B 4.5 59 3B 10.5 75 4B 12 C -7.125 28 1C -1.125 44 2C 4.875 60 3C 10.875 76 4C 13 D -6.75 29 1D -0.75 45 2D 5.25 61 3D 11.25 14 E -6.375 30 1E -0.375 46 2E 5.625 62 3E 11.625
15 F -6 31 1F 0 47 2F 6 63 3F 12
DEC HEX Boost Gain DEC HEX Boost Gain 0 0 0 16 10 24 1 1 1.5 17 11 25.5 2 2 3 18 12 27
10 A 15 26 1A
12 C 18 28 1C
14 E 21 30 1E
Table 63. MX-B6h: DRC/AGC Control 3
6 R/W 0’h Enable Noise Gate function
5 R/W 0’h Enable Noise Gate Hold Data Function
Table 64. MX-BBh: Jack Detection Control 1 Table 65. MX-BCh: Jack Detection Control 2
Table 66. MX-BDh: IRQ Control 1
Table 67. MX-BEh: IRQ Control 2
15 R/W 0’h IRQ Output Source Configure of MICBIAS1 Over Current
11 R/W 0’h Sticky Control for MICBIAS1 Over Current
Table 68. MX-BFh: GPIO and Internal Status
Table 69. MX-C0h: GPIO Control 1 Table 70. MX-C1h: GPIO Control 2
Table 71. MX-D3h: Wind Filter Control 1 Table 72. MX-D3h: Wind Filter Control 2
Table 73. MX-D9h: Soft Volume & ZCD Control
Table 74. MX-FAh: General Control 1 Table 75. PR-3Dh: ADC/DAC RESET Control
Table 76. PR-A0h: EQ Low Pass Filter Coefficient (LPF:a1) Table 77. PR-A1h: EQ Low Pass Filter Gain (LPF:H0) Table 78. PR-A2h: EQ Band 1 Coefficient (BPF1:a1) Table 79. PR-A3h: EQ Band 1 Coefficient (BPF1:a2)
Table 80. PR-A4h: EQ Band 1 Gain (BPF1:H0) Table 82. PR-A6h: EQ Band 2 Coefficient (BPF2:a2) Table 83. PR-A7h: EQ Band 2 Gain (BPF2:H0)
Table 84. PR-A8h: EQ Band 3 Coefficient (BPF3:a1) Table 85. PR-A9h: EQ Band 3 Coefficient (BPF3:a2) Table 86. PR-AAh: EQ Band 3 Gain (BPF3:H0) Table 87. PR-ABh: EQ Band 4 Coefficient (BPF4:a1)
Table 88. PR-ACh: EQ Band 4 Coefficient (BPF4:a2) Table 89. PR-ADh: EQ Band 4 Gain (BPF4:H0) Table 90. PR-AEh: EQ High Pass Filter 1 Coefficient (HPF1:a1) Table 91. PR-AFh: EQ High Pass Filter 1 Gain (HPF1:H0)
Table 92. PR-B0h: EQ High Pass Filter 2 Coefficient (HPF2:a1) Table 93. PR-B1h: EQ High Pass Filter 2 Coefficient (HPF2:a2) Table 94. PR-B2h: EQ High Pass Filter 2 Gain (HPF2:H0) Table 95. PR-B3h: EQ Pre Volume Control
Table 96. PR-B4h: EQ Post Volume Control Table 97. MX-FEh: Vendor ID
- Electrical Characteristics
Table 98. Absolute Maximum Ratings Table 99. Recommended Operating Conditions Table 110. Static Characteristics Note: DBVDD=1.8V, DCVDD=1.2V , Tambient=40C.
Table 111. Analog Performance Characteristics
I2S Audio CODEC for Mobile Devices 88 Rev. 0.1 Parameter Min Typ Max Units IDD_1.8V IDDD_3.3V µA µA MICBIAS1 Output Voltage Setting 1 Setting 2 0.9*MICVDD 0.75*MICVDD V V MICBIAS1 Drive Current MICBIAS = 0.9*MICVDD mA Note: Standard test conditions: Tambient=25C DBVDD=1.8V DCVDD=1.2V A VDD=1.8V MICVDD=3.3V CPVDD=1.8V 1kHz input sine wave; PCM Sampling frequency=48kHz; Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation
Figure 24. I2C Control Interface Table 112. I2C Timing
Figure 25. Timing of I2S/PCM Master Mode
Figure 26. I2S/PCM Slave Mode Timing Table 114. I2S/PCM Slave Mode Timing
I2S Audio CODEC for Mobile Devices 92 Rev. 0.1 10. Application Circuits LRCK C12 2.2uF/6.3V R26 10k/5% GPIO1/IRQ LOUTL I2C Interface DBVDD C41 2.2uF/6.3V C32 2.2uF R19 0/5% INL C42 2.2uF/6.3V INR HPOL C18 4.7uF/6.3V DACDAT MCLK_IC MIC_IN HPOR R29 10k/5% MICBIAS1 DBVDD DCVDD CPVDD AVDD MICVDD ADCDAT MIC_VDD DACREF SDA R27 10k/5% JD1_1 ALC5651 MICVDD 31 CPP1 14 CPN1 13 JD11 AGND7 CPN2 11CPP2 12 BCLK124 MCLK25 AVDD 6 LOUTR/N 10 IN2P3 DACDAT122 HPO_R 17 SDA 27SCL 26 CPVEE 19 CPVREF 18 LOUTL/P 9 DCVDD 30 GPIO1/IRQ128 MICBIAS132 DACREF 5 IN2N/JD24 VREF2 8 CPGND33 DGND33 DBVDD 29 HPO_L 20 LRCK123 ADCDAT121 CPVPP 16 CPVDD 15 IN1P2 HPGND33 JD1_2 R5 0/5%/0805 SCL C10 2.2uF/6.3V 4.7uF/6.3V BCLK LOUTR SCL_Host CPGND DGND CPGND AGND SDA_Host
Figure 27. Application Circuit
Figure 28. Package Dimension
Table 115. Ordering Information