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AC’97 AUDIO CODEC + TOUCH PANEL CONTROLLER DATASHEET Rev. 1.0
15 August 2007
Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw
AC’97 Audio Codec + Touch Panel Controller ii Track ID: JATR-1076-21 Rev. 1.0 COPYRIGHT ©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC5611 Audio Codec IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary 1.0 2007/08/15 First release
AC’97 Audio Codec + Touch Panel Controller iii Track ID: JATR-1076-21 Rev. 1.0 Table of Contents
AC’97 Audio Codec + Touch Panel Controller iv Track ID: JATR-1076-21 Rev. 1.0
AC’97 Audio Codec + Touch Panel Controller v Track ID: JATR-1076-21 Rev. 1.0
AC’97 Audio Codec + Touch Panel Controller 1 Track ID: JATR-1076-21 Rev. 1.0 1. General Description The ALC5611 is a highly-integrated AC'97 interface audio codec with multiple input/output ports and a 4-wire touch panel controller. The ALC5611 is designed for mobile computing and communications. Stereo audio is supported via the AC’97 interface. To reduce component count, the device can connect directly to:
- A 4-wire touch panel
- MONO or stereo differential analog inputs
- Stereo headphone
- Single-end or BTL MONO output
- MONO or Stereo Bridge-Tied Load (BTL) speaker Multiple analog input and output pins are provided for seamless integration with analog connected wireless communication devices. Differential input/output connections efficiently reduce noise interference, providing better sound quality. Class-AB or Class-D amplifiers are easily swapped via simple register configuration, and the 1 Watt speaker removes the need for an additional amplifier, further cutting both cost and required board area. Additionally, a flexible hardware 5-band equalizer with configurable gain, bandwidth, and center frequency, and enriches the sound experience. The ALC5611 operates at supply voltages from 1.8 to 5 Volts. To extend battery life, each section of the device can be powered down individually under software control. Leakage current in maximum power saving state is less than 10uA. The ALC5611 is available in a 7x7mm ‘Green’ QFN package, making it ideal for use in handheld portable systems.
AC’97 Audio Codec + Touch Panel Controller 2 Track ID: JATR-1076-21 Rev. 1.0 2. Features Single-chip AC’97 Rev 2.2 compatible codec 16-bit DAC SNR 90dB, THD+N -85dB 16-bit ADC SNR 85dB, THD+N -80dB Supports all WinCE variable rates (8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz) One analog stereo input (LINE-IN) One analog MONO single-ended or differential input (PHONE and PHONEN input) Stereo, single-ended MONO, or differential analog microphone inputs, with boost pre-amplifiers (+20/+30/+40dB) BTL (Bridge-Tied Load) Max. output with on-chip 1W speaker driver (SPKVDD=5V, 8Ω load) Stereo headphone output with on-chip 45mW headphone driver (HPVDD=3.3V, 16Ω load) 25mW SE or 75mW BTL MONO output support (AVDD=3.3V, 32Ω load) Microphone switch detection Power management and enhanced power saving Supports digital 5 band equalizer (EQ) Supports digital spatial sound and pseudo stereo effect Supports pop noise suppression Internal PLL can receive wide range of clock input (Digital IO power > 2.3V) Digital power supplies from 1.8V to 3.6V, speaker amplifier power supplies from 2.3V to 5V Analog power, headphone power, and touch panel power supplies from 2.3V to 3.6V Resistive touch panel interface Supports 4-wire panel X, Y axis and pressure measurement 12-bit resolution AUX_ADC for battery measurement, DNL<±1 LSB, INL<±2 LSBs Supports pen-down detection in power down mode 48-pin QFN package
Figure 1. Block Diagram
Figure 2. Audio Mixer Path
Figure 3. Pin Assignments
Table 1. AC’97 Digital I/O Pins Table 2. Analog I/O Pins
Table 3. Filter/Reference Table 4. Power/Ground
Table 5. Power Setting for Best Performance There are 4 types of reset operation: Power-On Reset (POR), Cold, Warm, and Register reset. Table 6. Reset Operation Resets all hardware logic and all registers to default values. except some PLL related control registers and logic. related control registers and logic. Reactivates AC-LINK. No change to register values. Power On Reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip. Table 7. Power On Reset Voltage Note: VPOR_OFF must be below VPOR_ON.
externally, and the driver should arrange the clock of each block and setup each divider. depend on the accuracy of PLL output. Table 8. AC-Link Clock Setting Table (Unit: MHz) For the AC-LINK controller, the BIT_CLK driven by PLL will only be enabled after a warm reset. Reg2C (stereo DAC) and Reg32 (stereo ADC).
SDATA_IN on the rising edge of BIT_CLK. an unimplemented slot or bit with 0 in SDATA-IN. Note that AC-LINK is MSB-justified. See the ‘Audio CODEC ’97 Component Specification Revision 2.2’ for detailed information. Figure 4. AC-Link Wake Up Timing
AC’97 Audio Codec + Touch Panel Controller 12 Track ID: JATR-1076-21 Rev. 1.0 7.5. Audio Data Path 7.5.1. Stereo ADC The Stereo ADC is used for recording stereo sound. The sample rate of the stereo ADC is independent of the Stereo DAC sample rate. In order to save power, the left and right ADC can be powered down separately by setting Reg3C [6], [7]). PR0=1 will disable both channels of the ADC. The volume control of the stereo ADC is set via Reg12[11:7][4:0]. 7.5.2. Stereo DAC The sample rate of the stereo DAC is controlled by Reg2C. Reg0C[12:8][4:0] can be used to control the volume of DAC output. 7.5.3. Mixers The ALC5611 supports four mixers for all audio function requirements:
- Headphone mixer for 2 channels
- MONO mixer
- Speaker mixer
- ADC record mixer
7.5.3.1 Headphone Mixer
The headphone mixer is used to drive stereo output, including HP_OUT_L/R, SPK_OUT_L/R (SPK_OUT_LN/RN) and MONO_OUT (MONO_OUTN). The output of the Headphone mixer can be input to the ADC record mixer. The following signals can be mixed into the headphone mixer:
- LINE-IN_L/R (Controlled by Reg0A)
- PHONEP/N (Controlled by Reg08)
- MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
- Stereo DAC output (Controlled by Reg0C)
- ADC record mixer output (Controlled by Reg12 & Reg14). Note: The headphone mixer can be powered down by setting Reg3C[5][4].
AC’97 Audio Codec + Touch Panel Controller 13 Track ID: JATR-1076-21 Rev. 1.0
7.5.3.2 MONO Mixer
The MONO mixer is used to drive MONO_OUT (MONO_OUTN) and SPK_OUT_L/R (SPK_OUT_LN/RN). The output of the MONO mixer can be input to the ADC record mixer. The output of the MONO mixer is two channels with the same signal. The following signals can be mixed into the MONO mixer:
- LINE-IN_L/R (Controlled by Reg0A)
- MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
- Stereo DAC output (Controlled by Reg0C)
- ADC record mixer output (Controlled by Reg12 & Reg14). Note: The MONO mixer can be powered down by setting Reg3C[2].
7.5.3.3 Speaker Mixer
The speaker mixer is the same as the MONO mixer and is used to drive MONO_OUT (MONO_OUTN) and SPK_OUT_L/R (SPK_OUT_LN/RN). The output of the speaker mixer can be input to the ADC record mixer. The output of the speaker mixer is two channels with the same signal. The following signals can be mixed into the speaker mixer:
- LINE-IN_L/R (Controlled by Reg0A)
- PHONEP/N (Controlled by Reg08)
- MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
- Stereo DAC output (Controlled by Reg0C) Note: The speaker mixer can be powered down by setting Reg3C[3].
7.5.3.4 ADC Record Mixer
The ADC record mixer is used to mix analog signals as input to the Stereo ADC for recording. Output of the ADC record mixer can be input to the headphone mixer, MONO mixer, and speaker mixer. The following signals can be mixed into the ADC record mixer:
- LINE-IN_L/R (Controlled by Reg0A)
- PHONEP/N (Controlled by Reg08)
- MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10)
- Headphone mixer output
- MONO mixer output
- Speaker mixer output Note: The ADC record mixer can be powered down by setting Reg3C[1][0].
AC’97 Audio Codec + Touch Panel Controller 14 Track ID: JATR-1076-21 Rev. 1.0 7.5.4. Analog Audio Input Path The ALC5611 supports four Analog Audio Input paths:
- Line_IN_L/R
- PHONEP/N
- MIC1
- MIC2
7.5.4.1 Line Input
Line_In_L and Line_In_R provide 2-channel stereo single-ended input that can be mixed into the MONO mixer, Headphone mixer, Speaker mixer, or the ADC record mixer. The Line_In_L/R volume and mute are controlled by Reg0A. Reg3E[7:6] can be used to power down Line_In volume control.
7.5.4.2 Phone Input
PHONEP/N provides one-channel MONO differential or single-ended input configured by Reg08[13] that can be mixed into the ADC record mixer, or any analog output mixer except for the MONO mixer. PHONEP is main input when differential mode is disabled. The PHONEP/N volume and mute are controlled by Reg08. Reg3E[5:4] can be used to power down the PHONEP/N volume control and mixer.
7.5.4.3 Microphone Input
MIC1P/N and MIC2P/N provide two-channel stereo differential or single-ended input via Reg10[12], [4], that can be mixed into the ADC record mixer, or any analog output mixer. MIC1P and MIC2P are main inputs when differential mode is disabled. MIC1N is pin-shared to AUX3 input. The ALC5611 Microphone input boost provides 20/30/40dB boost, set by Reg22[11:10] (for MIC1), and by Reg22[9:8] (for MIC2). The MIC1/2 volume and mute are controlled by Reg0E. For detailed power management of MIC1/2, Reg3E[3][2] can be used to power down the MIC1/2 volume control. Reg3E[1][0] can be used to power down MIC1/2 and mixer.
7.5.4.4 MIC1N/AUX3 and MICBIAS2/AUX4 Pin Sharing
AUX_ADC. The driver must set the related register as shown in Table 9. Table 9. Pin Sharing Configuration Table
- SPK_OUT_L/R
- HP_OUT_L/R
- MONO_OUT
7.5.5.1 Speaker Output
SPK_OUT_L/R provides two-channel differential output.
- Vmid
- Headphone left mixer
- Speaker mixer
- MONO mixer The SPK_OUT_R source is set in Reg1C[12:11]. Sources are shown below:
- Vmid
- Headphone right mixer
- Speaker mixer
- MONO mixer
AC’97 Audio Codec + Touch Panel Controller 16 Track ID: JATR-1076-21 Rev. 1.0 The ALC5611 speaker supports Class AB and Class D type amplifiers (set in Reg1C[13]:spk_out_sel). As the voltage of SPKVDD is usually higher than AVDD, the driver should set the Class AB Vmid ratio in Reg40[5:3], and the Class D Vmid ratio in Reg40[7:6] in order to extend the output level. In class AB mode, for single stereo speaker solutions, SPK_OUT_R can select a different signal source (SPKR Volume output or SPKL Volume output by Reg1C[14]) but SPK_OUT_RN only outputs SPKR Volume Negative Output. The SPK_OUT_L/R volume and mute are controlled by Reg02. Reg3E[13]: pow_spk_r and Reg3E[12]:pow_spk_rn can be used to power down SPK output. Reg3C[14]: pow_clsab is used to power down Class AB output, and Index 46[15:12] is used to power down each output channel of Class D. SPK_OUT_L/R supports the zero-cross detect function (enabled at Reg02[6][14]: sp_l_dezero/ sp_r_dezero).
7.5.5.2 Headphone Output
HP_OUT_L/R provides two-channel single-ended output. The HP_OUT_L/R source is set in Reg1C[9][8]. Sources are shown below:
- Vmid
- Headphone mixer The HP_OUT_L/R volume and mute are controlled by Reg04. Reg3E[11]: pow_hp_l_vol and Reg3E[10]: pow_hp_r_vol can be used to power down the volume of HP output. HP_OUT supports the zero-cross detect function (enabled at Reg04[14][6]:hp_l_dezero/ hp_r_dezero).
7.5.5.3 MONO Output
MONO_OUT provide one-channel differential or single-ended output configured by Reg08[15]. The MONO_OUT source is set in Reg1C[7:6]. Sources are shown below:
- Vmid
- Headphone mixer (L+R)
- Speaker mixer
- MONO mixer The MONO_OUT volume and mute are controlled by Reg08. Reg3E[14]: pow_MONO_out_vol can be used to power down the volume of MONO_OUT. MONO_OUT supports the zero-cross detect function (enabled at Reg08[6]:MONO_dezero).
touch pressure, and AUX measurement are supported by using AUX_ADC. Figure 7. 4-Wire Resistive Touch Panel Circuit Reg76[15] =1. The ALC5611 will clear the Reg76[15] after measurement is complete.
ADC to an expected sound level by setting THmax and THmin. gain to attenuate the quantized Pulse Code Modulation (PCM) signal to a lower amplitude than THmax. than THmin. The quantized PCM has an average level between THmin and THmax. Figure 8. Auto Volume Control Block Diagram
AC’97 Audio Codec + Touch Panel Controller 19 Track ID: JATR-1076-21 Rev. 1.0 7.8. Hardware Sound Effects The Sound Effect block is composed of Pseudo Stereo, Spatial 3D and Equalizer blocks. The Pseudo Stereo block is used to convert a MONO source into virtualized stereo output. The Spatial 3D block is a surround sound generator with adjustable amplitude (Gain) and surround depth (Ratio). The Equalizer block can be used to compensate for speaker response, or to make environment sound effects, e.g., ‘Pub’, ‘Live’ , ‘Rock’,… etc.. 7.8.1. Equalizer Block The Equalizer block cascades 5 bands of equalizer to compensate for speaker response and to emulate environment sound. One high-pass filter cascaded in the front end is used to drop low frequency tone, which has a larger amplitude and may damage a mini speaker. The high-pass filter can also be used to adjust Treble strength with gain control. A low-pass filter with gain control can adjust the Bass strength. Three bands of bi-quad bandpass filters are used to emulate environment sounds. To avoid internal PCM data sample saturation, the digital volume control has up to 18dB of attenuation before the equalizer. A 0~+18dB digital gain after the equalizer is used to correct internal PCM data output to a suitable level. 7.8.2. Pseudo Stereo and Spatial 3D Sound There are two spatial effects in post-processing; the Pseudo-Stereo Effect + Spatial Effect, and the Stereo Expansion Effect. The Pseudo-Stereo Effect + Spatial Effect converts a MONO signal to a stereo signal by changing the phase and amplitude of the original signal followed by enhancing the spatial effect. The Stereo Expansion Effect enhances the spatial effect when the input signal is Stereo. 7.9. Odd-Addressed Register Access The ALC5611 will return ‘0000h’ when odd-addressed and unimplemented registers are read.
active when both Reg26 and Reg3C/3E are set to ‘Enable’. can set other control bits to save power according to system requirements.
- Pen-down Detection
- GPIO and Interrupts
- Analog to analog path when control registers Reg 3C & 3E are enabled There are two methods to wake the ALC5611 from Sleep mode
- Warm Reset and Cold Reset from AC Link
- Wake-up from GPIO (configured as Input) and Internal event signal (pen-down, over-temperature) when the wake-up bit is set at Reg52.
Figure 9. Example of ALC5611 Power-Down/Power-Up Flow
The ALC5611 supports up to five GPIOs. Each GPIO can be configured as Input/Output by Reg4C.
- Sticky by setting Reg50
- Changed polarity by setting Reg4E
- Wake-up by setting Reg52 The wake-up function will drive SDATA_In ‘high’ when the AC-Link is in sleep mode, and set GPIO_INT (Slot12 bit0) when the AC-Link is awake. The wake up function can only be enabled when Wake-up control (Reg5E[1])=1. The driver can write each bit of Reg54=1 to clear each IRQ status flag. GPIO pin2 can be configured and pin-shared with IRQ_Output by setting Reg56.
Figure 10. GPIO Implementation
Accessing odd numbered registers, or reading unimplemented registers, will return a 0. Table 10. Reg-00h: Reset Table 11. Reg-02h: Speaker Output Volume
Table 12. Reg-04h: Headphone Output Volume Table 13. Reg-08h: Phone Input/MONO Output Volume
Table 14. Reg-0Ah: LINE_IN Volume Table 15. Reg-0Ch: STEREO DAC Volume
Table 16. Reg-0Eh: MIC Volume Table 17. Reg-10h: MIC Routing Control
AC’97 Audio Codec + Touch Panel Controller 26 Track ID: JATR-1076-21 Rev. 1.0 8.9. Reg-12h: ADC Record Gain Default: F58Bh Table 18. Reg-12h: ADC Record Gain
Description
adc2hp_l_mute 15 R/W 1’h Mute Left Gain Output to Headphone Mixer Control 0: On 1: Mute (-∞dB) adc2hp_r_mute 14 R/W 1’h Mute Right Gain Output to Headphone Mixer Control 0: On 1: Mute (-∞dB) adc2MONO_l_mute 13 R/W 1’h Mute Left Gain Output to MONO Mixer Control 0: On 1: Mute (-∞dB) adc2MONO_r_mute 12 R/W 1’h Mute Right Gain Output to MONO Mixer Control 0: On 1: Mute (-∞dB) adc_l_vol 11:7 R/W 0B’h ADC Record Gain Left Channel (LRG[4..0]) in 1.5dB Steps 00h: -16.5dB attenuation 0Bh: 0dB gain 1Fh: 30dB gain adc_l_dezero 6 R/W 0’h ADC_L Zero-Cross Detector Control 0: Disable 1: Enable adc_r_dezero 5 R/W 0’h ADC_R Zero-Cross Detector Control 0: Disable 1: Enable adc_r_vol 4:0 R/W 0B’h ADC Record Gain Right Channel (RRG[4..0]) in 1.5dB Steps 00h: -16.5dB attenuation 0Bh: 0dB gain 1Fh: 30dB gain
Table 19. Reg-14h: ADC Record Mixer Control
Table 20. Reg-1Ch: Output Mixer Control
Table 21. Reg-22h: Microphone Control Table 22. Reg-26h: Power Down Control/Status
Table 23. Truth Table for Power Down Mode: (PD = Power Down)
Table 24. Reg-2Ah: Tone Control Table 25. Reg-2Ch: AC’97 Stereo DAC Rate/DPE Rate The ALC5611 supports the following PC99/PC2001 design guide sampling rates. Table 26. PC99/PC2001 Design Guide Sampling Rates
44100 AC44h
48000 BB80h
When ac_src_en=0 (VRA is disabled), any non-zero value in this register will be forced to BB80h.
Table 27. Reg-32h: AC’97 Stereo ADC Rate adc_sample_rate 15:0 R/W BB80’h IISR[15:0] Output Sampling Rate. The ALC5611 supports the following PC99/PC2001 design guide sampling rates. Table 28. PC99/PC2001 Design Guide Sampling Rates
Table 29. Reg-3Ah: Power Management Addition 1
Table 30. Reg-3Ch: Power Management Addition 2
Table 31. Reg-3Eh: Power Management Addition 3
Figure 11. Power Control to MIC Input Table 32. Reg-40h: General Purpose Control Register 1
Table 33. Reg-42h: General Purpose Control Register 2 Table 34. Reg-44h: PLL Control
AC’97 Audio Codec + Touch Panel Controller 38 Track ID: JATR-1076-21 Rev. 1.0 8.22.1. AC-LINK PLL Clock Setting Table (Unit: MHz) Table 35. AC-LINK PLL Clock Setting Table (Unit: MHz) Table 36. Reg-4Ch: GPIO Pin Configuration Reserved 15:14 R 00’b Reserved pendown_conf 13 R/W 1’h Pen-down Detect Status Source Configuration 0: Bypass 1: Normal Reserved 12 R 0’b Reserved over_temp_conf 11 R/W 1’h Over-temperature Status Source Configuration 0: Bypass 1: Normal mic1_short_det_conf 10 R/W 1’h MICBIAS1 Short Current Status Source Configuration 0: Bypass 1: Normal mic2_short_det_conf 9 R/W 1’h MICBIAS2 Short Current Status Source Configuration 0: Bypass 1: Normal Reserved 8:6 R 0’h Reserved gpio5_conf 5 R/W 1’h GPIO5 Pin Configuration 0: Output 1: Input gpio4_conf 4 R/W 1’h GPIO4 Pin Configuration 0: Output 1: Input gpio3_conf 3 R/W 1’h GPIO3 Pin Configuration 0: Output 1: Input gpio2_conf 2 R/W 1’h GPIO2 Pin Configuration 0: Output 1: Input gpio1_conf 1 R/W 1’h GPIO1 Pin Configuration 0: Output 1: Input Reserved 0 R 0’h Reserved. Read as 0
Table 37. Reg-4Eh: GPIO Pin Polarity
Table 38. Reg-50h: GPIO Pin Sticky
Table 39. Reg-52h: GPIO Pin Wake-Up
10 R/W 0’h MICBIAS1 Short Current Detect Wake-up Enable
9 R/W 0’h MICBIAS2 Short Current Detect Wake-up Enable
Table 40. Reg-54h: GPIO Pin Status
Table 41. Reg-56h: Pin Sharing Figure 12. GPIO and IRQ Logic
Table 42. GPIO and IRQ Logic Table 43. Reg-58h: Over-Temp/Current Status
Table 44. Reg-5Ch: GPIO_Output Pin Control
Table 45. Reg-5Eh: MISC Control disabled before playback/record.
- Set the GPIO of the controller as output and set the
- After Reset, Set the GPIO of the controller as Input
- Enable the GPIO of the controller to receive INT
- After the controller Received INT, the controller
- Pen-up will be reported by Reg78[15]
The Jack-insert-detect pull up resister is implemented via an external circuit (see Figure 13, below). Figure 13. Jack-Insert-Detect Pull Up Resist er Implemented via an External Circuit
Table 46. Reg-68h: Pseudo Stereo and Spatial Effect Block Control 0: Disable (Bypass) and reset. Spatial coefficients cannot be modified when Spatial is enabled.
Table 47. Reg-6Ah: Index Address Table 48. Reg-6Ch: Index Data Table 49. Reg-6Eh: EQ Status This bit is set if overflow has occurred. Write 1 to clear. This bit is set if overflow has occurred. Write 1 to clear. This bit is set if overflow has occurred. Write 1 to clear. This bit is set if overflow has occurred. Write 1 to clear. This bit is set if overflow has occurred. Write 1 to clear.
Table 50. Index-00h: EQ Band-0 Coefficient (LP0: a1) Note: For low pass filter for Bass control – LP0 has filter coefficient a1 and gain Ho must be set (see Table 51). Table 51. Index-01h: EQ Band-0 Gain (LP0: Ho) Table 52. Index-02h: EQ Band-1 Coefficient (BP1: a1) Table 53. Index-03h: EQ Band-1 Coefficient (BP1: a2) Table 54. Index-04h: EQ Band-1 Gain (BP1: Ho)
Table 55. Index-05h: EQ Band-2 Coefficient (BP2: a1) Table 56. Index-06h: EQ Band-2 Coefficient (BP2: a2) Table 57. Index-07h: EQ Band-2 Gain (BP2: Ho) Table 58. Index-08h: EQ Band-3 Coefficient (BP3: a1) Table 59. Index-09h: EQ Band-3 Coefficient (BP3: a2)
Table 60. Index-0Ah: EQ Band-3 Gain (BP3: Ho) Table 61. Index-0Bh: EQ Band-4 Coefficient (HPF: a1) Table 62. Index-0Ch: EQ Band-4 Gain (HPF: Ho)
Table 63. Index-10h: EQ Control and Status Register
15 R/W EQ block Control
4 R/W EQ High-Pass Filter (HPF) Control
3 R/W EQ Band-3 (BP3) Control
2 R/W EQ Band-2 (BP2) Control
1 R/W EQ Band-1 (BP1) Control
0 R/W EQ Low-Pass Filter (LPF) Control
Note: Individual EQ coefficients cannot be modified when EQ is enabled. Table 64. Index-11h: EQ Input Volume Control Table 65. Index-12h: EQ Output Volume Control
Table 66. Index-20h: Auto Volume Control Register 0
15 R/W Select the Controlled Gain Block for A VC (Default:00b)
0 R/W A VC Reference Channel Selection (Default:0b)
Table 67. Index-21h: Auto Volume Control Register 1 Table 68. Index-22h: Auto Volume Control Register 2
Table 69. Index-23h: Auto Volume Control Register 3 Table 70. Index-24h: Auto Volume Control Register 4 Table 71. Index-25h: Auto Volume Control Register 5 Table 72. Index-39h: Digital Internal Register
15 R/W Pad Drive Capability
Table 73. Index-44h: Cla ss AB Internal Register
15 R/W POW_CLSAB LP: Class_AB Left Positive Channel
14 R/W POW_CLSAB LN: Class_AB Left Negative Channel
13 R/W POW_CLSAB RP: Class_AB Right Positive Channel
12 R/W POW_CLSAB RN: Class_AB Right Negative Channel
Table 74. Index-4Ah: Class D Temperature Sensor
15 R/W Reserved
11 R/W Reserved
7 R/W Reserved
3 R/W Reserved
Table 75. Index-54h: AD_DA_Mixer_Internal Register Note: To reduce DAC power consumption, we suggest that Index54=E184’h be initialized. Table 76. Reg-74h: Touch Panel Control Byte 1 will be turned ON once pen-down is detected. will not be turned ON even if pen-down is detected.
Table 77. Reg-76h: Touch Panel Control Byte 2
Table 78. Reg-78h: Touch Panel Indication Table 79. Reg-7Ch: VENDOR ID 1 Table 80. Reg-7Eh: VENDOR ID 2
- Electrical Characteristics
Table 81. Absolute Maximum Ratings Note: SPKVDD =5V with 3.5% duty cycle Power bouncing up to SPKVDD=8V is acceptable. Table 82. Recommended Operating Conditions Note 1: Minimum DVDD1=2.3V when PLL is working.
Table 83. Static Characteristics Note: DVDD= 3.3V , Tambient=25°C, with 50pF external load.
Table 84. Analog Performance Characteristics
AC’97 Audio Codec + Touch Panel Controller 63 Track ID: JATR-1076-21 Rev. 1.0 Parameter Min Typ Max Units MONO_OUT Amplifier Efficiency (fIN=1kHz, 32Ω Load) Single End Mode (Output Power=25mW) BTL Mode (Output Power=75mW) MONO_OUT/AUXOUT_L/R Amplifier THD+N Single End Mode (10KΩ Load) Output Power=0.1mW BTL Mode (10KΩ Load) Output Power=0.1mW 0.01 0.01 MONO_OUT Amplifier PSRR - 50 - dB Headphone Amplifier Output Power (32Ω Load) - - 31.25 mW Headphone Amplifier Quiescent Current (32Ω Load) - 700 - uA Headphone Amplifier Efficiency (fIN=1kHz, 32Ω Load, Output Power=25mW) 50 - - % Headphone Amplifier THD+N (32Ω Load) Output Power=20mW Output Power=25mW dB dB Headphone Amplifier PSRR - 50 - dB BTL Speaker Amplifier Output Power (SPKVDD=5V with 8Ω Load) - 1 - W BTL Speaker Amplifier Quiescent Current Class AB_Strong (8Ω Load) Class D mA mA BTL Speaker Amplifier Efficiency (fIN=1kHz, 8Ω Load, Output Power=700mW) Class AB Class D BTL Speaker Amplifier THD+N (8Ω Load) Class AB_Strong (8Ω Load) Output Power=350mW Output Power=600mW Class D Output Power=350mW Output Power=600mW dB dB dB dB BTL Speaker Amplifier THD+N Class AB_Weak (10KΩ/50pF Load) -85 dB BTL Speaker Amplifier SNR Class AB_Weak (10KΩ/50pF Load) -90 dB BTL Speaker Amplifier PSRR - 50 - dB Power Supply Current IDDA (Analog Block) IDDD (Digital Block) mA mA Power Down Current IDDA (Analog Block) IDDD (Digital Block) µA µA
AC’97 Audio Codec + Touch Panel Controller 64 Track ID: JATR-1076-21 Rev. 1.0 Parameter Min Typ Max Units MICBIAS1 Output V oltage 0.75*Avdd Setting 0.9*Avdd Setting 2.475 2.97 V V MICBIAS1 and MICBIAS2 Drive Current - 16 - mA MICBIAS2 Output V oltage 0.75*Avdd Setting 0.9*Avdd Setting 2.475 2.97 V V Verf Pull Up Resistor - 50 - KΩ Note: Standard test conditions Tambient=25°C, DVDD=AVDD=HPVDD=3.3V , SPKVDD = 4.2V 1kHz input sine wave;internal PCM data Sampling frequency=48kHz; 0dB=1Vrms, Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation; EQ and 3D disabled
Table 87. AC-Link Clock Parameters Note: Worse case duty cycle restricted to 45/55. Figure 16. Data Output and Input Timing Table 88. AC-Link Data Timing Parameters Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes.
Figure 17. Signal Rise and Fall Timing Table 89. AC-Link Signal Rise and Fall Timing Parameters
Figure 18. AC-Link Low Power Mode Timing Table 90. AC-Link Low Power Mode Timing Parameters Table 91. AC-Link IO Pin Capacitance Parameters
AC’97 Audio Codec + Touch Panel Controller 69 Track ID: JATR-1076-21 Rev. 1.0 10. Application Circuits
AC’97 Audio Codec + Touch Panel Controller 70 Track ID: JATR-1076-21 Rev. 1.0 11. Mechanical Dimensions
Table 92. Ordering Information Note 1: See page 5 for Green package and version identification. Note 2: Above parts are tested under AVDD =3.3V .