ALC3261 REALTEK | Alldatasheet
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(P/N: ALC3261-CG) FOUR CHANNEL I2S/PCM AUDIO CODEC WITH VOICE DSP DATASHEET (China Customer Only) Rev. 0.91 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com
Four Channel I2S Audio Codec with Voice DSP ii Rev. 0.91 COPYRIGHT ©2012 Realtek Semiconductor Corp. A ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC3261 Audio Codec IC. Though every effort has been made to ensure th at this document is cu rrent and accurate, more information may have become available subsequent to the production of this guide.
Four Channel I2S Audio Codec with Voice DSP iii Rev. 0.91
REVISION HISTORY
Revision Release Date Summary 0.9 2012/5/14 First release for China customer 0.91 2012/5/28
Four Channel I2S Audio Codec with Voice DSP iv Rev. 0.91 Table of Contents
Four Channel I2S Audio Codec with Voice DSP v Rev. 0.91
Four Channel I2S Audio Codec with Voice DSP vi Rev. 0.91
Four Channel I2S Audio Codec with Voice DSP vii Rev. 0.91
Four Channel I2S Audio Codec with Voice DSP designed for Dell only 1 Rev. 0.1 1. General Description The ALC3261 is a low power, dual I2S interface, 4 channels DAC and 2 channel ADC Audio Codec with a optimized Voice DSP integrated. The primary I2S interface connects to system host chip and its secondary I2S interface can perform as input or output device connected to external processor, blue tooth device or wireless transceiver. ALC3261 is a highly integration of audio subsystem chip, including two stereo DACs with 100dB SNR, one stereo ADC with 94dB SNR, stereo Class-D speaker amplifiers provides 1.5W per channel into 8Ω or 2.5W per channel into 4Ω with a 5V supply with excellent PSRR and low EMI, a mono differential earpiece amplifier is also provided, providing output from any DAC or Analog-in. The ALC3261 features an extra low power cap-free headphone amplifier. It consumes only less than 10mW power during playback, providing tablet system longer battery life under headphone listening mode. The integrated DRC (Dynamic Range Controller) and parametric Equalizer provides further digital sound processing capability of audio playback paths. The DRC in ALC3261 continuously monitors the DAC output level. When the power level is low, it increases the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. It ensures the maximum/consistent signal amplitude without producing audio clipping and speaker damage. The parametric Equalizer contains 7 independent filters with programmable gain, center frequency and bandwidth to tailor the frequency characteristics of embedded speaker system according to user preferences. ALC3261 embedded a low power wideband voice DSP. This optimized voice DSP provides excellent noise suppression, echo cancellation and beam forming performance. It combines 8 kHz and 16 kHz sampling rate and 75MIPS digital signal processing capability to achieve high fidelity and non-stationary wideband performance.
Four Channel I2S Audio Codec with Voice DSP 2 Rev. 0.91 2. Features Two Stereo Digital-to-Analog Converters with 100dBA SNR One Stereo Analog-to-Digital Converter with 94dBA SNR Differential analog microphone inputs with boost pre-amplifiers and low noise microphone bias +20/+24/+30/+35/+40/+44/+50/+52 dB microphone boost gain MIC input to ADC with 50dB boost gain, SNR > 66dBA and THD+N < -65dB Adjustable microphone reference voltage (0.9*MICVDD or 0.75*MICVDD) Stereo line level input Line level input to ADC with 0dB gain, SNR >= 94dBA, THD+N <= -83dB Stereo line level output ADC to line level output with 0dB gain, SNR >= 100dBA, THD+N <= -86dB Stereo/Mono BTL (Bridge-Tied-Load) Class-D amplifier 650mW/CH (SPKVDD=3.6V, THD+N < = 1%, 8 Load) 500mW/CH (SPKVDD=3.6V, THD+N < = 0.1%, 8 Load) 1.2W/CH (SPKVDD=5.0V, THD+N < = 1%, 8 Load) 2.5W/CH (SPKVDD=5.0V, THD+N < = 10%, 4 Load) 2.1W/CH (SPKVDD=5.0V, THD+N < = 1%, 4 Load) Auto speaker ratio gain for SPKVDD = 3.3V ~ 5.0V Stereo Cap-Free headphone amplifier with extra low power consumption for playback 20mW/CH (AVDD=CPVDD=1.8V, THD+N <= -80dB, 16 Load) Playback power consumption <= 10mW (AVDD=VBVDD=CPVDD=1.8V, 16, With I2S Clock, Playback Silence) Playback power consumption <= 13mW (AVDD=VBVDD=CPVDD=1.8V, 16, With I2S Clock, Playback 1mW/channel to 32 headphone) Mono differential receiver amplifier 50mW/CH (AVDD=CPVDD=1.8V, THD+N <= -70dB, 16 Load, BTL mode) Audio jack insert detection Inside PLL can receiver wide range clock input Two 24bit/8kHz ~ 192kHz I2S/PCM interface for each mono DAC and stereo DAC Two 24bit/8kHz ~ 192kHz I2S/PCM interface for stereo ADC I2C control interface Two digital microphone interfaces supported Asynchronous sample rate converter (ASRC) for each interface Programmable register table with two sequencers 7-bands parametric equalizer (EQ) for DAC path or ADC path Enhanced DRC(Dynamic Range Control)/AGC(Auto Gain Control) with compression function for DAC path or ADC path Zero detection and soft volume for pop noise suppression Speaker amplifier DC term self-test function for speaker protection Voice Processing Noise Reduction Beam Forming with Stereo Microphone Far Field Pick-Up Technology
Four Channel I2S Audio Codec with Voice DSP 3 Rev. 0.91 3. System Application Smart Phones Tablet
- Function Block and Mixer Path
Figure 1. Block Diagram
Figure 2. Audio Mixer Path
Figure 3. Digital Mixer Path
Figure 4. Pin Assignments
Table 1. Digital I/O Pins
Table 2. Analog I/O Pins
Table 3. Filter/Reference Table 4. Power/Ground
Four Channel I2S Audio Codec with Voice DSP 11 Rev. 0.91 7. Function Description 7.1. Power There are different power types in ALC3261. DBVDD is for digital I/O power, DCVDD is for digital core power, AVDD/DACREF is for analog power, CPVDD is for charge pump power, MICVDD is for MICBIAS power and SPKVDD is for speaker amplifier power. The power supplier limit condition are DBVDD DCVDD and SPKVDD ≧≧ MICVDD > AVDD = DACREF = CPVDD, AVDD DCVDD, and for the best performance, our design setting is show≧ n as below. Table 5. Power Supply for Best Performance Power DBVDD DCVDD AVDD DACREF CPVDD MICVDD SPKVDD To prevent all power down leakag e, there are two settings for pow er supply. At these conditions, the leakage will be smaller. First setting is to power on all power pin. Second setting is to only power on SPKVDD and others are removed. The detail setting is shown as following table. Table 6. Power Supply Condition for Power Down Leakage Power DBVDD DCVDD AVDD DACREF CPVDD MICVDD SPKVDD Setting-1 Supplied Supplied Supplied Supplied Supplied Supplied Supplied Setting-2 N/A N/A N/A N/A N/A N/A Supplied
Four Channel I2S Audio Codec with Voice DSP 12 Rev. 0.91 7.2. Power Supply On/Off Sequence To prevent pop noise or other side effect and make sure function work normally. We recommend power supply on/off sequence as below: Power On Sequence: (Sequentially turn-on power pins) 1. Pull LDO1_EN pin (Pin#44) to DGND (digital ground) 2. SPKVDD power supply on 3. DCVDD power supply on (This step is required if DCVDD is suppl ied by external 1.2V power. This step and Step 5 are exclusive.) 4. DBVDD/AVDD/DACREF/CPVDD power supply on 5. Pull LDO1_EN pin (Pin#44) to DBVDD (This step is required if DCVDD is generated by internal LDO. This step and Step 3 are exclusive. If DCVDD is supplied by external 1.2V, LDO1_EN must be pulled low.) 6. MICVDD power supply on (This step is required if MICVDD is supplied by external power) 7. Software starts to initialize ALC3261 Power Off Sequence: (Sequentially turn off power pins) 1. Power down all Codec function (Write 0x0000’h to register MX-00’h) 2. Pull LDO1_EN pin (Pin#44) to DGND (If internal LDO is used to generate DCVDD) 3. MICVDD power supply off (If MICVDD is supplied by external power) 4. DBVDD/AVDD/DACREF/CPVDD power supply off 5. DCVDD power supply off (If DCVDD is supplied by external power) 6. SPKVDD power supply off
There are 2 types of reset operation: power on reset (POR) and register reset. Table 7. Reset Operation control registers and logic. power on reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip. Table 8. Power-On Reset Voltage
- When DCVDD is supplied 1.2V
When MX-00h is wrote, all registers become to default value.
clock of each block and setup each divider. accuracy and keep audio performance under clock source asynchronous. device. The ratio of BCLK and LRCK can set by register – MX-73. Figure 5. Audio Clock Tree
source of the PLL can be set to MCLK, BCLK1 or BCLK2 by setting register. The S/W driver can set up the PLL to output a frequency to match the requirement of system clock. Table 10. Clock Setting Table for 48K (Unit: MHz) Table 11. Clock Setting Table for 44.1K (Unit: MHz)
Four Channel I2S Audio Codec with Voice DSP 16 Rev. 0.91 7.4.2. I2C and Two I2S/PCM Interface The ALC3261 supports I 2C for the digital control interface, and has two I 2S/PCM for digital data interface. These two I 2S/PCM audio digital interfaces are used to send data to 4 DACs or to receive data from a stereo ADC. These two I 2S/PCM audio digital interfaces can be configured to Master mode or Slave mode. Master Mode Under master mode, BCLK and LRCK are configured as output. If I2S SYSCLK is selected from MCLK source, sel_sysclk1 (MX-80[15:14]) s hould set as 00’b. If selected fr om PLL output, sel_sysclk1 should set as 01’b. PLL’s source is sugge sted to provide frequency from 2.048MHz to 40MHz. The driver should set each divider (MX-73 and MX-89) to arra nge the clock distribution. Refer to Figure5. Audio Clock Tree, for details. Slave Mode Under slave mode BCLK and LRCK are configured as input. The SYSCLK can be input from MCLK, and BCLK can be synchronous or asynchronous to MCLK . If the SYSCLK is se lected from BCLK, the internal PLL should generate 256*FS by BCLK. And the driver should set each divider to arrange the clock distribution. Refer to Figure5. Audio Clock Tree, for details.
The ALC3261 provides 4-channel analog DACs for playback and 2-channel analog ADCs for recording. interface, maybe two channels for one I2S interface or mono channel for one I2S interface. ADC can be powered down separately by setting pow _adc_l (MX-61[2]) and pow_adc_r (MX-61[1]). Figure 13. 4-Channel Recording Path
output, mono output or line output. vol_mono_dacl (MX-1A[15:8] and vol_mono_dacr (MX-1A[7:0]). Figure 14. 4-Channel Playback Path
Four Channel I2S Audio Codec with Voice DSP 22 Rev. 0.91 7.6.3. Mixers The ALC3261 has digital and analog mixers build-in. Output mixer - OUTMIXL/R The stereo analog mixer can do mixing for DAC output and analog input. The mixer output is mainly for headphone output and line output. Each input path has it’s mute control to the mixer block in MX-4D ~ MX-52. pow_outmixl and pow_outmixr can be used to power on/off OUTMIXL/R Speaker mixer – SPKMIXL/R The stereo analog mixer can do mixing for OUTMIX output, DAC output and analog input. The mixer output is for speaker output. Each input path has it’s mute control to the mixer block in MX-46 and MX-47. pow_spkmixl and pow_spkmixr can be used to power on/off SPKMIXL/R. Speaker_Out mixer – SPOMIXL/R The stereo analog mixer can do mixing for from speaker volume, DAC and analog input. The mixer output is direct to speaker output. Each input path has it’s mute control to the mixer block in MX-48 and MX-49. LINE_Out mixer – LOUTMIX The stereo analog mixer can do mixing for analog input and DAC output. The mixer output is for line-out output for drive external amplifier. Each input has individual mute control to the mixer block in MX-53. pow_lout can be used to power on/off LOUTMIX. Record mixer – RECMIXL/R The stereo analog mixer can do mixing for analog input and OUTMIX output. The mixer output is for ADC input. Each input path has it’s mute control to the mixer block in MX-3B ~ MX-3E. pow_recmixl and pow_recmixr can be used to power on/off RECMIXL/R. HP mixer – HPOMIXL/R The stereo analog mixer can do mixing for headphone volume and DAC output. The mixer output directly output to external headphone device. Each input path has it’s mute control to the mixer block in MX-45. Digital mixer There are ten digital mixers in ALC3261. Four digital mixers are assigned for ADC recording. These four mixers can mix analog line input, analog microphone input and digital microphone input then output to I2S interface to other device. Another four digital mixers are assigned DAC playback. These mixers can mix digital data from I2S interface or ADC data from external analog signal. The mixed data is output to analog DAC and output port to drive external device. The other two mixers are use for DA-AD processing. The incoming data from two I2S interfaces (DACDAT) uses these two mixers to do mixing and output to I2S interface (ADCDAT).
Four Channel I2S Audio Codec with Voice DSP 23 Rev. 0.91 7.7. Analog Audio Input Port The ALC3261 has two types analog input ports: microphone input and line input. IN1P/N The IN1P/N is a microphone type input port. The input port can be configured to differential input or single-ended input by MX-0D[7]. The microphone input port has its microphone bias and microphone boost. The low noise microphone bias can improve recording performance and enhance recording quality. Build-in short current detection scheme can be used for switch detection. Multi-steps microphone boost gain set by sel_bst1 (MX-0D[15:12]) is easy to use for microphone application. Pow_bst1 can be used to power down the MIC1 boost and pow_micbias1 can be used to power down the microphone bias 1. IN2P/N The IN2P/N is a dual type input port: microphone input and line input. Microphone input can be configured to differential input or single-ended input by MX-0E[6]. Multi-steps microphone boost gain set by sel_bst2 (MX-0E[11:8]) is easy to use for microphone application. Pow_bst2 can be used to power down the MIC2 boost. As line input, it has volume control for tuning by MX-0F[12:8] and MX-0F[4:0]. IN3P/N The IN3P/N is a microphone input. The microphone input can be configured to differential input or single-ended input by MX-0D[6]. Multi-steps microphone boost gain set by sel_bst3 (MX-0D[11:8]) is easy to use for microphone application. Pow_bst3 can be used to power down the MIC3 boost.
The speaker output of ALC3261 is a stereo BTL output with Class-D type amplifier. ratio setting can be controlled by fbgain_clsd (MX-8D[15:12]). -46.5dB with 1.5dB/step controlled by MX-01. SPKVOLL and SPKVOLR. The pow_clsd (MX-61[0]) can be used to power on/off SPO_L/R_P/N. Figure 15. Speaker Output Mode – Stereo Mode
Four Channel I2S Audio Codec with Voice DSP 25 Rev. 0.91 HPO_L/R The headphone output of ALC3261 is a stereo output with cap-free type headphone amplifier. It does not need to connect external capacitor and can connect to earphone device directly. The headphone output source can mix from output mixer (OUTMIX) or DAC by setting MX-45. The front stage of headphone output has volume control and gain control. The volume range is from +12dB to -46.5dB with 1.5dB/step by MX-02. En_l_hp and en_r_hp (MX-63[7/6]) can be used to power on/off Headphone Amplifier, and pow_hpo_voll and pow_hpo_volr (MX-66[11/10]) can be used to power on/off headphone volume control. In addition, pow_pump_hp (MX-8E[3]) can be used to power on/off charge pump circuit for Headphone Amplifier. MONO_P/N The mono output is a differential output with Class-AB type amplifier. The mono output source can be mixed from analog input, OUTVOL and DAC output by setting MX-4C[15:11]. The front stage of mono output has gain control for attenuation, the gain control is 0dB or -6dB by MX-4C[10]. Line_OUT_L/R The output type is line type output. The output is a stereo single ended output. The input can be selected from OUTVOL or DAC output by setting MX-53[15:12]. The front stage of LOUT output has gain control for attenuation. The gain control is 0dB or -6dB by MX-53[11].
return to the target level, need to set the pre-gain to achieve. Figure 18. DRC/AGC for Playback/Recording Mode
the input signal will be boosted to target level. Figure 19. DRC/AGC for Noise Gate Mode
prevent the signal is too small. Table 12. Ration Gain Table for SPKVDD and AVDD Figure 20. Ratio Gain Behavior for SPKVDD and AVDD
Four Channel I2S Audio Codec with Voice DSP 30 Rev. 0.91 7.11. Equalizer Block The equalizer block cascades 7 bands of equalizer to tailor the frequency characteristics of embedded speaker system according to user preferences and to emulate environment sound. The 7 bands equalizer includes two high pass filter, four band pass filter and one low pass filter. One high pass filter cascaded in the front end is used to drop low frequency tone, The tone has a large amplitude and may damage a mini speaker. The high pass filter can be used to adjust Treble strength with gain control. One low pass filter with gain control can adjust the Bass strength. Four bands of bi-quad band pass filters are used to emulate environment sounds, e.g., ‘Pub’, ‘Live’, ‘Rock’,… etc.. The gain, center frequency and bandwidth of each filter are all programmable.
drain structure. The input has built-in spike filter and can remove less than 50ns spike at SCL and SDA. Table 14. Address Setting (0x38h) Figure 21. Data Transfer Over I 2C Control Interface
Table 15. Write WORD Protocol Table 16. Read WORD Protocol
pins – JD1 and JD2. The JD1 and JD2 share pins with IN1N and IN2N. Figure 22. GPIO Function Block
ALC3261 detailed Power Management control registers are supported in MX-61h, 62h, 63h, 64h and 65h. Each particular block will only be active when each bit MX-61h, 62h, 63h, 64h, and 65h is set to enable. Figure 25. Power Management
The Programmable Register Array is used for continuing executing register set by one register command. The Table 17 shown as programmable register table with two sequencers. Table 17. Programmable Register Table
- Set Programmable Register Table
- Enable Programmable Register Function (MX-CA[7])
- Check Sequencer-1/2 finished or not?
ALC3261 register map as shown as following and accessing unimplemented registers, will return a 0. Table 18. Register Map
Four Channel I2S Audio Codec with Voice DSP 38 Rev. 0.91 Type Name Description Register Address Reset State Management-
1 I2S & DAC & ADC & Class-D Power Control MX-61h 0x0000’h
2 Digital Filter Power Control MX-62h 0x0000’h
VREF & MBias & LOUTMIX & Mono & HP & LDO2 Power Control MX-63h 0x00C0’h Management-
4 MICBST & MICBIAS Power Control MX-64h 0x0000’h
5 OUTMIX & SPKMIX & RECMIX Power Control MX-65h 0x0000’h
SPOVOL & OUTVOL & HPOVOL & INVOL Power Control MX-66h 0x0000’h PR Index PR Register Index MX-6Ah 0x0000’h PR Register PR Data PR Register Data Mx-6Ch 0x0000’h I2S1 Port Ctrl I2S-1 Interface Control MX-70h 0x8000’h I2S2 Port Ctrl I2S-2 Interface Control MX-71h 0x8000’h ADC/DAC Clock-1 ADC/DAC Clock Control-1 MX-73h 0x1110’h Digital Interface ADC/DAC Clock-2 ADC/DAC Clock Control-2 MX-74h 0x0C00’h Digital MIC DMIC Digital Microphone Control MX-75h 0x1D00’h Global Clock Global Clock Control MX-80h 0x0000’h PLL-1 PLL Control-1 MX-81h 0x0000’h PLL-2 PLL Control-2 MX-82h 0x0000’h ASRC-1 ASRC Control-1 MX-83h 0x0000’h ASRC-2 ASRC Control-2 MX-84h 0x0000’h ASRC-3 ASRC Control-3 MX-85h 0x0008’h ASRC-6 ASRC Control-4 MX-89h 0x0000’h Global Clock ASRC-7 ASRC Control-5 MX-8Ah 0x0000’h Class-D Class-D OC C ontrol MX-8Ch 0x0228’h SPK Amp Class-D Class-D Ratio Gain & Mode Control MX-8Dh 0xA800’h HP Amp HP HP Output De-Pop Control MX-8Eh 0x0004’h SPK Amp PV Detection SPKVDD Detection Control MX-92h 0x0000’h MICBIAS MICBIAS MICBIAS Control MX-93h 0x3000’h EQ-1 EQ Control-1 MX-B0h 0x2000’h EQ-2 EQ Control-2 MX-B1h 0x0000’h EQ-Parameter EQ Low Pass Filter – a1 PR-A0h 0x1C10’h EQ-Parameter EQ Low Pass Filter – H0 PR-A1h 0x01F4’h EQ-Parameter EQ Band Pass Filter 1 – a1 PR-A2h 0xC5E9’h EQ-Parameter EQ Band Pass Filter 1 – a2 PR-A3h 0x1A98’h EQ-Parameter EQ Band Pass Filter 1 – H0 PR-A4h 0x1D2C’h EQ-Parameter EQ Band Pass Filter 2 – a1 PR-A5h 0xC882’h EQ-Parameter EQ Band Pass Filter 2 – a2 PR-A6h 0x1C10’h EQ-Parameter EQ Band Pass F ilter 2 – H0 PR-A7h 0x01F4’h EQ-Parameter EQ Band Pass F ilter 3 – a1 PR-A8h 0xE904’h EQ-Parameter EQ Band Pass Filter 3 – a2 PR-A9h 0x1C10’h EQ-Parameter EQ Band Pass F ilter 3 – H0 PR-AAh 0x01F4’h EQ-Parameter EQ Band Pass F ilter 4 – a1 PR-ABh 0xE904’h EQ-Parameter EQ Band Pass Filter 4 – a2 PR-ACh 0x1C10’h EQ-Parameter EQ Band Pass F ilter 4 – H0 PR-ADh 0x01F4’h EQ EQ-Parameter EQ High Pass Filter 1 – a1 PR-AEh 0x1C10’h
Table 19. MX-00h: S/W Reset Note: Writes to this register will reset all registers to their default values.
Table 20. MX-01h: Speaker Output Control
10 A -3 26 1A -27
12 C -6 28 1C -30
14 E -9 30 1E -33
Table 21. MX-02h: Headphone Output Control
Four Channel I2S Audio Codec with Voice DSP 42 Rev. 0.91 Name Bits Read/Write Reset State Description Mu_hpovolr_in 6 R/W 1’h Mute Control for Right Headphone Volume Channel (HPOVOLR) 0’b: Un-Mute 1’b: Mute Vol_hpor 5:0 R/W 8’h Right Headphone Channel Volume Control (HPOVOLR) 00’h: +12dB 08’h: 0dB 27’h: -46.5dB, with 1.5dB/step Volume Table DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 0 0 12 16 10 -12 32 20 -36 1 1 10.5 17 11 -13.5 33 21 -37.5 2 2 9 18 12 -15 34 22 -39 3 3 7.5 19 13 -16.5 35 23 -40.5 4 4 6 20 14 -18 36 24 -42 5 5 4.5 21 15 -19.5 37 25 -43.5 6 6 3 22 16 -21 38 26 -45 7 7 1.5 23 17 -22.5 39 27 -46.5 8 8 0 24 18 -24 9 9 -1.5 25 19 -25.5 11 B -4.5 27 1B -28.5 13 D -7.5 29 1D -31.5 15 F -10.5 31 1F -34.5
Table 22. MX-03h: LINE Output Control
Table 23. MX-04h: MONO Output Control Table 24. MX-0Dh: IN1 Input Control
Table 25. MX-0Eh: IN2 Input Control
Table 26. MX-0Fh: INL & INR Volume Control
Table 27. MX-19h: DACL1/R1 Digital Volume Table 28. MX-1Ah: DACL2/R2 Digital Volume
Four Channel I2S Audio Codec with Voice DSP 48 Rev. 0.91 6 6 -63.375 59 3B -43.5 112 70 -23.625 165 A5 -3.75 218 DA 7 7 -63 60 3C -43.125 113 71 -23.25 166 A6 -3.375 219 DB 8 8 -62.625 61 3D -42.75 114 72 -22.875 167 A7 -3 220 DC 9 9 -62.25 62 3E -42.375 115 73 -22.5 168 A8 -2.625 221 DD 10 A -61.875 63 3F -42 116 74 -22.125 169 A9 -2.25 222 DE 11 B -61.5 64 40 -41.625 117 75 -21.75 170 AA -1.875 223 DF 12 C -61.125 65 41 -41.25 118 76 -21.375 171 AB -1.5 224 E0 13 D -60.75 66 42 -40.875 119 77 -21 172 AC -1.125 225 E1 14 E -60.375 67 43 -40.5 120 78 -20.625 173 AD -0.75 226 E2 15 F -60 68 44 -40.125 121 79 -20.25 174 AE -0.375 227 E3 16 10 -59.625 69 45 -39.75 122 7A -19.875 175 AF 0 228 E4 17 11 -59.25 70 46 -39.375 123 7B -19.5 176 B0 229 E5 18 12 -58.875 71 47 -39 124 7C -19.125 177 B1 230 E6 19 13 -58.5 72 48 -38.625 125 7D -18.75 178 B2 231 E7 20 14 -58.125 73 49 -38.25 126 7E -18.375 179 B3 232 E8 21 15 -57.75 74 4A -37.875 127 7F -18 180 B4 233 E9 22 16 -57.375 75 4B -37.5 128 80 -17.625 181 B5 234 EA 23 17 -57 76 4C -37.125 129 81 -17.25 182 B6 235 EB 24 18 -56.625 77 4D -36.75 130 82 -16.875 183 B7 236 EC 25 19 -56.25 78 4E -36.375 131 83 -16.5 184 B8 237 ED 26 1A -55.875 79 4F -36 132 84 -16.125 185 B9 238 EE 27 1B -55.5 80 50 -35.625 133 85 -15.75 186 BA 239 EF 28 1C -55.125 81 51 -35.25 134 86 -15.375 187 BB 240 F0 29 1D -54.75 82 52 -34.875 135 87 -15 188 BC 241 F1 30 1E -54.375 83 53 -34.5 136 88 -14.625 189 BD 242 F2 31 1F -54 84 54 -34.125 137 89 -14.25 190 BE 243 F3 32 20 -53.625 85 55 -33.75 138 8A -13.875 191 BF 244 F4 33 21 -53.25 86 56 -33.375 139 8B -13.5 192 C0 245 F5 34 22 -52.875 87 57 -33 140 8C -13.125 193 C1 246 F6 35 23 -52.5 88 58 -32.625 141 8D -12.75 194 C2 247 F7 36 24 -52.125 89 59 -32.25 142 8E -12.375 195 C3 248 F8 37 25 -51.75 90 5A -31.875 143 8F -12 196 C4 249 F9 38 26 -51.375 91 5B -31.5 144 90 -11.625 197 C5 250 FA 39 27 -51 92 5C -31.125 145 91 -11.25 198 C6 251 FB 40 28 -50.625 93 5D -30.75 146 92 -10.875 199 C7 252 FC 41 29 -50.25 94 5E -30.375 147 93 -10.5 200 C8 253 FD
Table 29. MX-1Bh: DACL2/R2 Mute/Un-Mute Control
Table 30. MX-1Ch: Stereo ADC Digital Volume Control Table 31. MX-1Dh: Mono ADC Digital Volume Control
Four Channel I2S Audio Codec with Voice DSP 51 Rev. 0.91 Mono_ad_gain_r 6:0 R/W 2F’h Mono ADC Right Channel Volume Control 00’h: -17.625dB 2F’h: 0dB 7F’h: +30dB, with 0.375dB/Step Volume Table: DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain 1 1 -17.25 27 1B -7.5 53 35 2.25 79 4F 12 105 69 21.75 3 3 -16.5 29 1D -6.75 55 37 3 81 51 12.75 107 6B 22.5 5 5 -15.75 31 1F -6 57 39 3.75 83 53 13.5 109 6D 23.25 7 7 -15 33 21 -5.25 59 3B 4.5 85 55 14.25 111 6F 24 9 9 -14.25 35 23 -4.5 61 3D 5.25 87 57 15 113 71 24.75 11 B -13.5 37 25 -3.75 63 3F 6 89 59 15.75 115 73 25.5 13 D -12.75 39 27 -3 65 41 6.75 91 5B 16.5 117 75 26.25 15 F -12 41 29 -2.25 67 43 7.5 93 5D 17.25 119 77 27 17 11 -11.25 43 2B -1.5 69 45 8.25 95 5F 18 121 79 27.75 19 13 -10.5 45 2D -0.75 71 47 9 97 61 18.75 123 7B 28.5 21 15 -9.75 47 2F 0 73 49 9.75 99 63 19.5 125 7D 29.25 23 17 -9 49 31 0.75 75 4B 10.5 101 65 20.25 127 7F 30 24 18 -8.625 50 32 1.125 76 4C 10.875 102 66 20.625 25 19 -8.25 51 33 1.5 77 4D 11.25 103 67 21
Table 32. MX-1Eh: ADC Digital Boost Gain Control Table 33. MX-27h: Stereo ADC Digital Mixer Control
Table 34. MX-28h: Mono ADC Digital Mixer Control
Table 35. MX-29h: Stereo ADC to DAC Digital Mixer Control
15 R/W 1’h Mute Control for Stereo ADC Left Channel to DAC
7 R/W 1’h
Table 36. MX-2Ah: Stereo DAC Digital Mixer Control
13 R/W 0’h
11 R/W 0’h
5 R/W 0’h
3 R/W 0’h
Table 37. MX-2Bh: Mono DAC Digital Mixer Control
Table 38. MX-2Ch: DAC Digital Mixer Control
Table 39. MX-2Dh: Voice DSP Path Control 1 Table 40. MX-2Eh: Voice DSP Path Control 2
Table 41. MX-2Fh: Interface DAC/ADC Data Control Table 42. MX-3Bh: RECMIXL Control 1
Table 43. MX-3Ch: RECMIXL Control 2
Table 44. MX-3Dh: RECMIXR Control 1
Table 45. MX-3Eh: RECMIXR Control 2
Table 46. MX-45h: HPOMIX Control Table 47. MX-46h: SPKMIXL Control
Table 48. MX-47h: SPKMIXR Control
Table 49. MX-48h: SPOLMIX Control
Table 50. MX-49h: SPORMIX Control Table 51. MX-4Ah: SPOL/RMIX Gain Control
Table 52. MX-4Ch: MONOMIX Control
13 R/W 1’h Mute Control for OUTVOLR to MONOMIX
12 R/W 1’h Mute Control for OUTVOLL to MONOMIX
Table 53. MX-4Dh: OUTMIXL Control 1
Table 54. MX-4Eh: OUTMIXL Control 2
Table 55. MX-4Fh: OUTMIXL Control 3
Table 56. MX-50h: OUTMIXR Control 1
Table 57. MX-51h: OUTMIXR Control 2
Table 58. MX-52h: OUTMIXR Control 3 Table 59. MX-53h: LOUTMIX Control
Table 60. MX-61h: Power Management Control 1
Table 61. MX-62h: Power Management Control 2
15 R/W 0’h Stereo ADC Digital Filter Power Control
14 R/W 0’h Mono ADC_L Digital Filter Power Control
13 R/W 0’h Mono ADC_R Digital Filter Power Control
Table 62. MX-63h: Power Management Control 3
Table 63. MX-64h: Power Management Control 4
Table 64. MX-65h: Power Management Control 5 Table 65. MX-66h: Power Management Control 6
Table 66. MX-6Ah: Private Register Index Table 67. MX-6Ch: Private Register Data Table 68. MX-70h: I2S1 Digital Interface Control
Table 69. MX-71h: I2S2 Digital Interface Control
Table 70. MX-73h: ADC/DAC Clock Control 1
Table 71. MX-74h: ADC/DAC Clock Control 2
Table 72. MX-75h: Digital Microphone Control
Table 73. MX-80h: Global Clock Control Table 74. MX-81h: PLL Control 1
Table 75. MX-82h: PLL Control 2 Table 76. MX-83h: ASRC Control 1
Table 77. MX-84h: ASRC Control 2
4 R/W 0’h Automatically Detect I2S1 Input Sample Rate
3 R/W 0’h Automatically Detect I2S2 Input Sample Rate
Table 78. MX-85h: ASRC Control 3
Table 79. MX-89h: ASRC Control 4 Table 80. MX-8Ah: ASRC Control 5
Table 81. MX-8Ch: Class-D Amp OC Control Table 82. MX-8Dh: Class-D Amp Output Control Table 83. MX-8Eh: HP Amp Control
Table 84. MX-8Fh: HP Amp Control 2
Table 85. MX-92h: SPKVDD Detection Control Table 86. MX-93h: MICBIAS Control
Table 87. MX-B0h: EQ Control 1 sta_hpf2 6 R 0’h EQ High Pass Filter (HPF2) Status. This bit is set if overflow had ever occurred. sta_hpf1 5 R 0’h EQ High Pass Filter (HPF1) Status. This bit is set if overflow had ever occurred. sta_bpf4 4 R 0’h EQ Band-4 (BP4) Status. This bit is set if overflow had ever occurred. sta_bpf3 3 R 0’h EQ Band-3 (BP3) Status. This bit is set if overflow had ever occurred. sta_bpf2 2 R 0’h EQ Band-2 (BP2) Status. This bit is set if overflow had ever occurred.
sta_bpf1 1 R 0’h EQ Band-1 (BP1) Status. This bit is set if overflow had ever occurred. sta_lpf 0 R 0’h EQ Low Pass Filter (LPF) Status. This bit is set if overflow had ever occurred. Table 88. MX-B1h: EQ Control 2 en_hpf2 6 R/W 0’h EQ High Pass 2nd Butterworth Filter (HPF) Control. en_hpf1 5 R/W 0’h EQ High Pass Filter (HPF) Control. en_bpf4 4 R/W 0’h EQ Band-4 (BP4) shelving Filter Control. en_bpf3 3 R/W 0’h EQ Band-3 (BP3) shelving Filter Control. en_bpf2 2 R/W 0’h EQ Band-2 (BP2) shelving Filter Control. en_bpf1 1 R/W 0’h EQ Band-1 (BP1) shelving Filter Control. en_lpf 0 R/W 0’h EQ Low Pass Filter (LPF) Filter Control.
Table 89. MX-B4h: DRC/AGC Control 1
13 R 1’h Update DRC/AGC Parameter
change the DRC/AGC rate, the parameter of DRC/AGC isn’t need be modified. parameter by I2S’s sample rate.
Table 90. MX-B5h: DRC/AGC Control 2
7 R/W 0’h DRC Compression Function Control
Four Channel I2S Audio Codec with Voice DSP 92 Rev. 0.91 6 6 -9.375 22 16 -3.375 38 26 2.625 54 36 8.625 70 46 7 7 -9 23 17 -3 39 27 3 55 37 9 71 47 8 8 -8.625 24 18 -2.625 40 28 3.375 56 38 9.375 72 48 9 9 -8.25 25 19 -2.25 41 29 3.75 57 39 9.75 73 49 10 A -7.875 26 1A -1.875 42 2A 4.125 58 3A 10.125 74 4A 11 B -7.5 27 1B -1.5 43 2B 4.5 59 3B 10.5 75 4B 12 C -7.125 28 1C -1.125 44 2C 4.875 60 3C 10.875 76 4C 13 D -6.75 29 1D -0.75 45 2D 5.25 61 3D 11.25 14 E -6.375 30 1E -0.375 46 2E 5.625 62 3E 11.625
15 F -6 31 1F 0 47 2F 6 63 3F 12
DEC HEX Boost Gain DEC HEX Boost Gain 0 0 0 16 10 24 1 1 1.5 17 11 25.5 2 2 3 18 12 27 3 3 4.5 19 13 28.5 4 4 6 20 14 5 5 7.5 21 15 6 6 9 22 16 7 7 10.5 23 17 8 8 12 24 18 9 9 13.5 25 19
10 A 15 26 1A
11 B 16.5 27 1B
12 C 18 28 1C
13 D 19.5 29 1D
14 E 21 30 1E
15 F 22.5 31 1F
Table 91. MX-B6h: DRC/AGC Control 3
6 R/W 0’h Enable Noise Gate function
5 R/W 0’h Enable Noise Gate Hold Data Function
Table 92. MX-BBh: Jack Detection Control 1
Table 93. MX-BCh: Jack Detection Control 2 Table 94. MX-BDh: IRQ Control 1
Table 95. MX-BEh: IRQ Control 2
15 R/W 0’h IRQ Output Source Configure of MICBIAS1 Over Current
11 R/W 0’h Sticky Control for MICBIAS1 Over Current
Table 96. MX-BFh: GPIO and Internal Status
Table 97. MX-C0h: GPIO Control 1 Table 98. MX-C2h: GPIO Control 2
Table 99. MX-C4h: Voice DSP Control 1 Table 100. MX-C5h: Voice DSP Control 2 Table 101. MX-C6h: Voice DSP Control 3
Table 102. MX-C8h: Programmable Register Array Control 1 Table 103. MX-C9h: Programmable Register Array Control 2
Table 104. MX-CAh: Programmable Register Array Control 3 Table 105. MX-CBh: Programmable Register Array Control 4 Table 106. MX-CCh: Programmable Register Array Control 5
Table 107. MX-CFh: SounzReal BassBack Control Table 108. MX-D9h: Soft Volume & ZCD Control
Table 109. MX-FAh: General Control 1
5 R/W 0’h Clock Select for Left Mono ADC
4 R/W 0’h Clock Select for Right Mono ADC
Table 110. MX-FBh: General Control 2
Table 111. PR-3Dh: ADC/DAC RESET Control Table 112. PR-A0h: EQ Low Pass Filter Coefficient (LPF:a1)
Table 113. PR-A1h: EQ Low Pass Filter Gain (LPF:H0) Table 114. PR-A2h: EQ Band 1 Coefficient (BPF1:a1) Table 115. PR-A3h: EQ Band 1 Coefficient (BPF1:a2) Table 116. PR-A4h: EQ Band 1 Gain (BPF1:H0)
Table 117. PR-A5h: EQ Band 2 Coefficient (BPF2:a1) Table 118. PR-A6h: EQ Band 2 Coefficient (BPF2:a2) Table 119. PR-A7h: EQ Band 2 Gain (BPF2:H0) Table 120. PR-A8h: EQ Band 3 Coefficient (BPF3:a1)
Table 121. PR-A9h: EQ Band 3 Coefficient (BPF3:a2) Table 122. PR-AAh: EQ Band 3 Gain (BPF3:H0) Table 123. PR-ABh: EQ Band 4 Coefficient (BPF4:a1) Table 124. PR-ACh: EQ Band 4 Coefficient (BPF4:a2)
Table 125. PR-ADh: EQ Band 4 Gain (BPF4:H0) Table 126. PR-AEh: EQ High Pass Filter 1 Coefficient (HPF1:a1) Table 127. PR-AFh: EQ High Pass Filter 1 Gain (HPF1:H0) Table 128. PR-B0h: EQ High Pass Filter 2 Coefficient (HPF2:a1)
Table 129. PR-B1h: EQ High Pass Filter 2 Coefficient (HPF2:a2) Table 130. PR-B2h: EQ High Pass Filter 2 Gain (HPF2:H0) Table 131. MX-FEh: Vendor ID
- Electrical Characteristics
Table 132. Absolute Maximum Ratings Note 1: SPKVDD=5V with 3.5% duty cycle Power bouncing up to SPKVDD=7V is acceptable. Table 133. Recommended Operating Conditions Table 134. Static Characteristics Note: DBVDD=1.8V , DCVDD=1.2V , Tambient=40C.
Table 135. Analog Performance Characteristics
Four Channel I2S Audio Codec with Voice DSP 112 Rev. 0.91 Parameter Min Typ Max Units Single-end) MIC_In to Stereo ADC with 40dB and MICBIAS (Differential or Single-end) MIC_In to Stereo ADC with 50dB and MICBIAS (Differential or Single-end) -74 -65 dB dB PSRR (Vripple=100mV , <=1KHz) DAC to Headphone Amplifier DAC to BTL Speaker Amplifier MIC/LINE_IN to ADC dB dB dB BTL Speaker Amplifier Efficiency (fIN=1kHz, 4 Load, SPKVDD=5.0V , Output Power=2.8W, with LC filter, L=33uH and C=1uF) Class-D (Stereo Mode) Power Consumption (Slave I2S Mode, 24-bit, SR: 44.1KHz) P_power down (No Clock Input) P_playback (Stereo DAC to HP_OUT with 16 Ohm Load, With Clock, play silence) P_playback (Stereo DAC to HP_OUT with 16 Ohm Load, With Clock, Po=1mW/CH) P_playback (Stereo DAC to SPK_OUT with 8 Ohm Load, With Clock, play silence) P_record (LINE_IN to Stereo ADC, With Clock) <150 <= 5 <= 13 < 19 < 8 uW mW mW mW mW Power Down Current IDDA (Analog Block) IDDD (Digital Block) µA µA MICBIAS1 Output Voltage Setting 1 Setting 2 0.9*MICVDD 0.75*MICVDD V V MICBIAS1 Drive Current MICBIAS = 0.9*LDO2_O mA Note: Standard test conditions: Tambient=25C DBVDD=1.8V DCVDD=1.2V A VDD=1.8V MICVDD=3.3V CPVDD=1.8V SPKVDD=5.0V or 4.2V or 3.6V . 1kHz input sine wave; PCM Sampling frequency=48kHz; Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation dBA: with A-Weighting
Figure 28. I 2C Control Interface Table 136. I 2C Timing
Figure 29. Timing of I 2S/PCM Master Mode Table 137. Timing of I 2S/PCM Master Mode
Figure 30. I 2S/PCM Slave Mode Timing Table 138. I 2S/PCM Slave Mode Timing
Four Channel I2S Audio Codec with Voice DSP 116 Rev. 0.91 10. Application Circuits R13 0/5% C12 2.2uF/6.3VCPVEE MONON If Use LDO1, Then Remove This Resistor R14 0/5% R26 10k/5% GPIO1/IRQ C28 10uF/16V 1.71V ~ 1.9V LOUTL SPKGND DGND C21 0.1uF/6.3V C22 10uF/6.3V CPVDD SPO_LN C27 0.1uF/16V SPKVDD C29 0.1uF/6.3V DBVDD C31 0.1uF/6.3V ALC3261 SPO_LP 1 LOUTL 16LOUTR 17 MICBIAS14 DACREF 10 SPO_LN 48 SPO_RN 47 SCL 38 MONON 14 AVDD 15 DACDAT133 ADCDAT134 GPIO2/DMIC_SCL 41 DCVDD 42 DBVDD 43 AGND9 MONOP 13 IN1P/DMIC1_DAT5 DACDAT231 CPN1 21 CPVEE 27 HPO_L 28 BCLK136 LRCK135 CPVDD 23 CPP1 20 VREF212 HPO_R 26 SDA 39 MCLK37 SPO_RP 45 SPKVDDL 2 IN2N/JD28 IN2P7 IN1N/DMIC2_DAT/JD16 VREF111 SPKGND49 DGND49 GPIO1/IRQ 40 CPGND22 ADCDAT232 BCLK230 LRCK229 SPKVDDR 46 HPOFB 25 CPP2 19 CPN2 18 CPVPP 24 MICVDD 3 LDO1_EN 44 DBVDD CPVDD R106 0/5%/1206 Size SPO_LP MONOP SPO_RN IN2N BCLK SPO_RP I2C Interface By-Pass Capcity Near The Power Pins AVDD 3.0V ~ 3.6V R29 0/5% C19 0.1uF/6.3V C20 10uF/6.3V SDAT IN1P MCLK C43 0.1uF/6.3V C44 2.2uF/6.3V MICVDD R15 0/5% GPIO R17 0/5% C41 2.2uF/6.3V C52 22pF/6.3V/NC R8 0/5% VLRCK LRCK2 BCLK2VBCLK I2S2 Interface C39 22pF/6.3V/NC SPKVDD DCVDD C40 22pF/6.3V/NC DACDAT2 ADCDAT2 VDACDAT R18 0/5% C54 22pF/6.3V/NC C42 2.2uF/6.3V VADCDAT SPKVDD MICBIAS1 3.3V ~ 5.0V IN1N R107 47/5% AGND HPOL C18 4.7uF/6.3V IN2P DACDAT C30 2.2uF/6.3V C32 2.2uF/6.3V HPOR LDO1 Control 1: Enable 0: Disable R10 0/5% LRCK ADCDAT VADCDAT DBVDD VDACDAT C25 2.2uF/6.3V 1.71V ~ 3.3V C50 22pF/6.3V/NC If Use LDO2, Then Remove This Resistor DACREF VLRCK Close to HP Jack's GND R7 0/5% LRCK LRCK1 BCLK1BCLK I2S1 Interface VBCLK MCLK C33 22pF/6.3V/NC AVDD C34 22pF/6.3V/NC CPGND R27 10k/5% Power 1.0V ~ 1.2V ADCDAT1 R28 0/5% DACDAT SCLK DACREF C48 0.1uF/6.3V C49 10uF/6.3V DACDAT1 C10 2.2uF/6.3V LDO1_EN DBVDD DCVDD MICVDD R11 0/5% R9 0/5%MCLK C45 22pF/6.3V/NC 4.7uF/6.3V LOUTR C51 22pF/6.3V/NC 1.71V ~ 1.9V SCL_Host CPVPP DMIC_SCL ADCDAT SDA_Host
Four Channel I2S Audio Codec with Voice DSP 117 Rev. 0.91 N P N P Analog Audio Input_R N P Analog Audio Input_L N P MICBIAS1 R108 0/5%/1206 Size DBVDD=1.8V R109 0/5%/1206 Size Ear Speaker MONOP MONON Receiver Amp Out R110 0/5%/1206 Size C11 1uF/6.3V IN2P C13 1uF/6.3V C15 1uF/6.3V MIC2 In IN2P IN2N R12 2.2k/5% IN1P C23 1uF/6.3V Line Input R16 2.2k/5% MIC1 In MIC3 MIC4 R111 0/5%/1206 Size DMIC_SCL R30 0/5% Loud SPKL R31 0/5% Loud SPKR MICBIAS1 SPO_LN SPO_LP SPO_RN SPO_RP C35 680pF/16V C36 680pF/16V C37 680pF/16V C38 680pF/16V Note: FB5~FB8 C35~C38 are reserved for EMI depression C67 100pF/6.3V C5 1uF/6.3V C6 1uF/6.3V IN2P IN2N 2.2k/5% MIC2 In 2.2k/5% C4 1uF/6.3V IN1P C8 1uF/6.3V IN1N 2.2k/5% MICBIAS1 2.2k/5% MIC1 In MIC2 MIC1 C68 100pF/6.3V MICBIAS1 DBVDD=1.8V DMIC_SCL IN1N MIC8 CON2 C D P G DMIC2 Input IN1P DMIC1 Input Analog Microphone Input - Option 2 (Single-End Mode) Analog Microphone Input - Option 1 (Differential Mode) MIC7 CON2 C D P G C24 1uF/6.3VLOUTR C26 1uF/6.3V J38 CON2 Line Out Heaphone Out R20 33/5% R21 33/5% C158 0.1uF/6.3V R98 22/5% R99 22/5% C165 0.1uF/6.3V PH2 HP Out HPOR HPOL R100 22/5% R101 22/5% Speaker - Stereo Mode LOUTL
Figure 32. Package Dimension
Table 139. Ordering Information