ALC269_09 REALTEK | Alldatasheet
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(ALC269Q-GR, ALC269QSRS-GR) HIGH DEFINITION AUDIO CODEC WITH EMBEDDED CLASS-D SPEAKER AMPLIFIER DATASHEET Rev. 1.3
21 January 2009
Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com
High Definition Audio Codec with Embedded Class-D Speaker Amplifier ii Track ID: JATR-1076-21 Rev. 1.3 COPYRIGHT ©2009 Realtek Semiconductor Corp. A ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular pu rpose. Realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC269 codec IC. Though every effort has been made to ensure th at this document is cu rrent and accurate, more information may have become available subsequent to the production of th is guide. In th at event, please contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary 1.0 2008/04/15 First Release 1.1 2008/04/25 Revised Figure 1 Block Diagram, page 5. Revised Table 84 Analog Performance, page 64 (DAC/ADC Full-Scale Input V oltage). 1.2 2008/12/24 Updated analog performance in section 9.3, page 64. 1.3 2009/01/21 Revised Table 77, page 59, Note 2.
High Definition Audio Codec with Embedded Class-D Speaker Amplifier iii Track ID: JATR-1076-21 Rev. 1.3 Table of Contents
High Definition Audio Codec with Embedded Class-D Speaker Amplifier iv Track ID: JATR-1076-21 Rev. 1.3 8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) .48
High Definition Audio Codec with Embedded Class-D Speaker Amplifier v Track ID: JATR-1076-21 Rev. 1.3
TABLE 58. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 48
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 1 Track ID: JATR-1076-21 Rev. 1.3 1. General Description The ALC269 is a High Definition Audio Codec that integrates a 2+2-channel DAC, a 4-channel ADC, and a Class-D Speaker Amplifier. The 2+2-channel DAC supports two independent st ereo sound outputs simultaneously. The 4-channel ADC integrates two stereo and independent analog sound inputs (multiple streaming). The ALC269 incorporates Realtek converter te chnology to achieve a 98dB dynamic range playback quality and a 98dB dynamic range recording quality. It meets the current WLP3.10 (Windows Logo Program) and future WLP requirements. The ALC269 also supports stereo digital microphone channels (mic rophone array) with Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously, significantly improving voice quality for PC VoIP applications. As well as basic audio f unctions, the ALC269 has two independent S/ PDIF outputs; one could be used to connect a PC to high-quality consumer electronic pr oducts such as digital decoders and speakers, the other could provide a dedicated digital output to a HDMI transmitter (common in high end PCs). There are three integrated power amplifiers. The fi rst is a linear headphone am plifier at port C. The second headphone amplifier at port A removes the need for external DC blocking capacitors, eliminating pop noise caused by these capac itors. The third is an integrated stereo Class-D amplifier to directly drive a mini-speaker. The Class-D amplifier is designed to drive speakers with as low as 4 Ω impedance. Its maximum output power is 2.3W per channel at 5V power supply. The advantage of an integrated Class-D amplifier in the ALC269 is high efficiency with low power consumption. The ALC269 integrates five hardware equalizer bands composed of one low-pass filter, one high-pass filter, and three band-pass filters to compensate for mini-speaker fre quency response. All the equalizer filters are programmable via the BIOS, allowing the e qualizer to function without the need to customize the audio driver. The ALC269 conforms to Intel’s Audio Codec low power state white paper and is ECR compliant. Note: ALC269 version differences are listed in section 12 Ordering Information, page 71.
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 2 Track ID: JATR-1076-21 Rev. 1.3 2. Features 2.1. Hardware Features 98dB Signal-to-Noise Ratio (A-weighting) for DAC output 98dB Signal-to-Noise Ratio (A-weighting) for ADC input Meets WLP (Windows Logo Program) 3.10 and future WLP requirements 2+2-channel DAC supports 16/20/24-bit PCM format for independent two stereo channel audio playback 4-channel ADC supports 16/20/24-bit PCM format for independent two stereo channel audio inputs All DACs supports 44.1/48/96/192kHz sample rate All ADCs support 44.1/48/96kHz sample rate S/PDIF-OUT support 16/20/24-bit format and 32/44.1/48/88.2/96/192kHz rate Supports MONO line level output Supports external PCBEEP input and built-in digital BEEP generator Software selectable 2.5V/3.2V/4.2V VREFOUT as bias voltage for analog microphone input Two jack detection pins each designed to detect up to 4 jacks 1dB resolution of input and output volume control Programmable +10/+20/+30dB boost gain for analog microphone input Built-in headphone amplifiers for port-A and port-C. 2 GPIOs are supported for customized applications (pin shared with digital microphone interface) EAPD (External Amplifier Power Down) is supported (pin shared with secondary S/PDIF-OUT) Supports Anti-pop mode when analog power AVDD is on and digital power is off analog power; 3.3V~5.0V power stage voltage Enhanced power management features Secondary S/PDIF-OUT supports 16/20/24-bit format and 32k/44.1k/48k/88.2k/96k/192kHz rate
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 3 Track ID: JATR-1076-21 Rev. 1.3 Supports stereo digital microphone input Programmable boost gain and volume control for digital microphone input Headphone amplifier for port-A does not require DC blocking capacitors Stereo Bridge-Tied Load Class-D amplifier at port-D has 2Watt (rms)/4Ω per channel output Short circuit and thermal overload protection for Class-D amplifier Supports digital PWM output at port-D which system integrator can easily connect the output to external power amplifier receives digital audio stream Five band hardware equalizer designed for BTL output (port-D) to compensate for frequency response while driving the mini-speaker Intel low power ECR compliant: supports power status control, jack detection, and wake-up event in D3 mode 48-pin QFN ‘Green’ package 2.2. Software Features Compatible with Windows Logo Program 3.10 and future requirements WaveRT-based audio function driver for Windows Vista EAX™ 1.0 & 2.0 compatible Direct Sound 3D™ compatible A3D™ compatible I3DL2 compatible HRTF 3D Positional Audio (Windows XP only) Emulation of 26 sound environments to enhance gaming experience Multi-band software equalizer and tools Voice Cancellation and Key Shifting in Karaoke mode Dynamic range control (expander, compressor, and limiter) with adjustable parameters Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 4 Track ID: JATR-1076-21 Rev. 1.3 Provides 10-foot GUI for Windows Media Center Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application Smart multiple streaming operation HDMI audio driver for AMD platform Dolby® PCEE program™ (optional software feature) SRS® TrueSurround HD (optional software feature) Fortemedia® SAM™ technology for voice processi ng (Beam Forming and Acoustic Echo Cancellation) (optional software feature) 3. System Applications Windows Vista premium desktop and laptop PCs Information appliances (IA) with High Definition Audio Controller
Figure 1. Block Diagram
Figure 2. Analog Input/Output Unit
Figure 3. Pin Assignments - ALC269 (QFN-48) in the location marked ‘VV’.
Table 1. Digital I/O Pins Output has 12 mA@75Ω driving capability. SPDIFO O 48 S/PDIF Output Output has 12mA@75Ω driving capability. Table 2. Analog I/O Pins MONO-OUT O 20 MONO Output Analog mono output is summation of (L+R)/2.
Table 3. Filter/Reference Table 4. Power/Ground
- High Definition Audio Link Protocol
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol. Figure 4. HDA Link Protocol
Table 5. Link Signal Definitions BCLK 24.0MHz bit clock sourced from the HDA controller and connected to all codecs. controller and connects to all codecs. least one SDO. To extend outbound bandwidth, multiple SDOs may be supported. each rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID. HDA controller and connects to all codecs. Table 6. HDA Signal Definitions BCLK Controller Output Global 24.0MHz Bit Clock. SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal. SDO Controller Output Serial Data Output from Controller. RST# Controller Output Global Active Low Reset Signal. Figure 5. Bit Timing
at the end of the stream tag. The stream tag includes a 4-Bit preamble and 4-Bit stream ID (Figure 8). Figure 7. SDO Outbound Frame
Figure 12. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz. blocks are transmitted every 160 frames.
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence AND interleave n empty frames. AND interleave an empty frame between non-empty frames (Table 9, page 18). Table 7. Defined Sample Rate and Transmission Rate Table 8. 48kHz Variable Rate of Delivery Timing N: No sample block in a frame. Y: One sample block in a frame. Yx: X sample blocks in a frame.
Table 9. 44.1kHz Variable Rate of Delivery Timing
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 19 Track ID: JATR-1076-21 Rev. 1.3 7.3. Reset and Initialization There are two types of reset within an HDA link:
- Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
- Codec Reset. Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events: 1. Link Reset 2. Codec Reset 3. Codec changes its power state (For example, hot docking a codec to an HDA system) 7.3.1. Link Reset A link reset may be caused by 3 events: 1. The HDA controller asserts RST# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ b it in the Global Control Register (GCR) of the HDA controller 3. Software initiates power management sequences . Figure 13, page 20, shows the ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v) Enter ‘Link Reset’: n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset o As the controller completes the current frame, it does not signal the normal 8-Bit frame SYNC at the end of the frame p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
4 BCLK 4 BCLK
Figure 13. Link Reset Timing
Figure 14. Codec Initialization Sequence
controls parameters in the codec. Table 10. 40-Bit Commands in 4-Bit Verb Format Table 11. 40-Bit Commands in 12-Bit Verb Format software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 12. Solicited Response Format Table 13. Unsolicited Response Format
various power states depending on system configuration. and input converters (ADCs) have no individual power control to supply fine-grained power control. Table 14. System Power State Definitions D0 All power on. Individual DACs and ADCs can be powered up or down as required. reference off (D1 + analog reference off). D3 (Hot) Power still supplied. The codec stops the internal clock. State is maintained. D3 (Cold) All power removed. State lost. Table 15. Power Controls in NID=01h Table 16. Powered Down Conditions sequences are supported. All states are maintained if DVDD is supplied. DAC powered down Analog block and digital filter are powered down. ADC powered down Analog block and digital filter ar e powered down. The data on SDATA-IN is quiet. Headphone Driver powered down All headphone drivers are powered down. at individual pin complexes are still alive.
- Supported Verbs and Parameters
not supported by the addressed widget, it will respond with 32 bits of ‘0’. detailed information about supported parameters. Table 17. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) 31:16 Vendor ID=10ECh (Realtek’s PCI vendor ID). Note: The Root Node (NID=00h) supports this parameter. Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 31:24 Reserved. Read as 0’s. 23:20 MajRev. The major version number (in decimal) of the HDA Spec to which the ALC269 is fully compliant. 19:16 MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC269 is fully compliant. 15:8 Revision ID. The vendor’s revision number. 00h is for the first silicon version A, 01h is for the second version B, etc. 7:0 Stepping ID. The vendor’s stepping number within the given Revision ID. Note: The Root Node (NID=00h in the ALC269) supports this parameter. For example, Revision ID=00h and Stepping ID=01h indicates the silicon is the A1 version.
associated with this function node. Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) 31:24 Reserved. Read as 0’s. 23:16 Starting Node Number. The starting node number in the sequential widgets. 7:0 Total Number of Nodes. For a root node, the total number of function groups in the root node. For a function group, the total number of widget nodes in the function group. Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) 03h~7Fh: Reserved 80h~FFh: Vendor Defined Function. Note: The Audio Function Group (NID=01h) supports this parameter. Table 22. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h) 31:17 Reserved. Read as 0’s. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0’s. Note: The Audio Function Group (NID=01h) supports this parameter.
Table 23. Parameter – Audi o Widget Capabilities (Verb ID=F00h, Parameter ID=09h) 31:24 Reserved. Read as 0’s. 19:16 Delay. Samples delayed between the HDA link and widgets. 15:11 Reserved. Read as 0’s. 8 ConnList. Connection List. 7 UnsolCap. Unsolicited Capable. 6 ProcWidget. Processing Widget. 3 AmpParOvr. AMP Param Override. 2 OutAmpPre. Out AMP Present.
own parameters to provide supported formats if their ‘Format Override’ bit is set. Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) 31:21 Reserved. Read as 0’s. 20 B32. Indicates whether 32-Bit audio format is supported. 19 B24. Indicates whether 24-Bit audio format is supported. 18 B20. Indicates whether 20-Bit audio format is supported. 17 B16. Indicates whether 16-Bit audio format is supported. 16 B8. Indicates whether 8-Bit audio format is supported. 15:12 Reserved. Read as 0’s. 11 R12. Indicates whether 384kHz (=8*48kHz) rate is supported. 10 R11. Indicates whether 192kHz (=4*48kHz) rate is supported. 9 R10. Indicates whether 176.4kHz (=4*44.1kHz) rate is supported. 8 R9. Indicates whether 96kHz (=2*48kHz) rate is supported. 7 R8. Indicates whether 88.2kHz (=2*44.1kHz) rate is supported. 6 R7. Indicates whether 48kHz rate is supported. 5 R6. Indicates whether 44.1kHz rate is supported. 4 R5. Indicates whether 32kHz (=2/3*48kHz) rate is supported. 3 R4. Indicates whether 22.05kHz (=1/2*44.1kHz) rate is supported. 2 R3. Indicates whether 16kHz (=1/3*48kHz) rate is supported. 1 R2. Indicates whether 11.025kHz (=1/4*44.1kHz) rate is supported. 0 R1. Indicates whether 8kHz (=1/ 6*48kHz) rate is supported.
have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Note: Input converters and output converters support this parameter. The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 26. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch) 31:16 Reserved. Read as 0’s. 15:8 VREF Control Capability. 7 L-R Swap. Indicates the capability of swapping the left and rights. 6 Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins. 5 Input Capable. ‘1’ indicates this pin complex supports input. 4 Output Capable. ‘1’ indicates this pin complex supports output. 3 Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone. 2 Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in. 1 Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement. device to determine its type. Note: Only Pin Complex widgets support this parameter.
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 27. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. 14:8 Number of Steps. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 6:0 Offset. Indicates which step is 0dB. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 28. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. 14:8 Number of Steps. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 6:0 Offset. Indicates which step is 0dB.
Parameters in this node provide audio function widget connection information. Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) input, and there is no Connection Select Control (Not a MUX widget). Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) 1: Power state D3 is supported. 1: Power state D2 is supported. 1: Power state D1 is supported.
0 D0Sup
1: Power state D0 is supported. Table 31. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h) 31:16 Reserved. Read as 0’s. 15:8 NumCoeff. Number of Coefficient.
Table 32. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h) The ALC269 does not support GPIO wake up function. The ALC269 supports GPIO unsolicited response. 29:24 Reserved. Read as 0’s. Two GPIO pins are supported. Table 33. Parameter – Volume Knob Capab ilities (Verb ID=F00h, Parameter ID=13h) The number of steps in the range of the V olume Control Knob. Note: The ALC269 does not support volume control knob.
Table 34. Verb – Get Connection Select Control (Verb ID=F01h) 7:0 Connection Index currently Set (Default value is 00h). 7:0 Connection Index Currently Set (Default value is 00h). 31:0 Not Supported (returns 00000000h). Table 35. Verb – Set Connection Select (Verb ID=701h)
Table 36. Verb – Get Connection List Entry (Verb ID=F02h) 31:8 Connection List Entry (N+3), (N+2), (N+1). 7:0 Connection List Entry (N). Returns 24h (Sum Widget) for N=0~3. Returns 00h for N>3. 31:8 Connection List Entry (N+3), (N+2), (N+1). 7:0 Connection List Entry (N). Returns 23h (Sum Widget) for N=0~3. Returns 00h for N>3. 31:16 Connection List Entry (N+3), (N+2). 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 02h (LOUT1 DAC) for N=0~3. Returns 00h for N>3. 31:16 Connection List Entry (N+3), (N+2). 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 03h (LOUT2 DAC) for N=0~3. Returns 00h for N>3. 31:16 Connection List Entry (N+3), (N+2). 15:8 Connection List Entry (N+1). Returns 0Dh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 0Ch (Mixer) for N=0~3. Returns 00h for N>3.
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 34 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=14h~15h, 18h~1Bh Bit Description 31:16 Connection List Entry (N+3), (N+2). Returns 0000h. 15:8 Connection List Entry (N+1). Returns 0Dh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 0Ch (Mixer) for N=0~3. Returns 00h for N>3. Codec Response for NID=16h Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1). Returns 000000h. 7:0 Connection List Entry (N). Returns 0Eh (Mixer) for N=0~3. Returns 00h for N>3. Codec Response for NID=1Eh) Bit Description 31:8 Connection List Entry (N+3, (N+2), (N+1). Returns 000000h. 7:0 Connection List Entry (N). Return 06h (First S/PDIF-OUT converter) for N=0~3. Returns 00h for N>3. Codec Response for NID=11h) Bit Description 31:8 Connection List Entry (N+3, (N+2), (N+1). Returns 000000h. 7:0 Connection List Entry (N). Return 10h (Secondary S/PDIF-OUT converter) for N=0~3. Returns 00h for N>3. Codec Response for NID=23h (MUX Widget) Bit Description 31:24 Connection List Entry (N+3). Return 1Bh (Pin Complex - LINE2) for N=0~3. Return 00h for N>3. 23:16 Connection List Entry (N+2). Return 1Ah (Pin Complex - LINE1) for N=0~3. Return 0Bh (Mixer Widget) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 19h (Pin Complex - MIC2) for N=0~3. Return 12h (Pin Complex – DMIC-DATA) for N=4~7. Return 00h for N>7. 7:0 Connection List Entry (N). Return 18h (Pin Complex - MIC1) for N=0~3. Return 1Dh (Pin Complex - PCBEEP) for N=4~7. Return 00h for N>7.
31:24 Connection List Entry (N+3). Return 1Bh (Pin Complex - LINE2) for N=0~3. Return 00h for N>3. 23:16 Connection List Entry (N+2). Return 1Ah (Pin Complex - LINE1) for N=0~3. Return 00h for N>3. 15:8 Connection List Entry (N+1). Return 19h (Pin Complex - MIC2) for N=0~3. Return 0Bh (Mixer Widget) for N=4~7. Return 00h for N>3. 7:0 Connection List Entry (N). Return 18h (Pin Complex - MIC1) for N=0~3. Return 1Dh (Pin Complex - PCBEEP) for N=4~7. Return 00h for N>7. 31:0 Not Supported (returns 00000000h). Table 37. Verb – Get Processing State (Verb ID=F03h) 31:0 Not Supported (returns 00000000h). Table 38. Verb – Set Processing State (Verb ID=703h)
Table 39. Verb – Get Coefficient Index (Verb ID=Dh) 31:16 Reserved. Read as 0’s. 31:0 Not Supported (returns 00000000h). Table 40. Verb – Set Coefficient Index (Verb ID=5h)
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch) 31:16 Reserved. Read as 0’s. 15:0 Processing Coefficient. 31:0 Not Supported (returns 00000000h). Table 42. Verb – Set Processing Coefficient (Verb ID=4h)
This verb is used to get gain/attenuation settings from each widget. Table 43. Verb – Get Amplifier Gain (Verb ID=Bh) 3:0 Index[3:0] for Input Source. Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored. 7 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0 (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0’s (No Input Amplifier Gain). 7 Payload[15] is 0 in ‘Get Amplifier Gain’: 1: Mute, 0:Unmute (Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain).
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 39 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=18h, 19h, 1Ah and 1Bh (Pin widget: MIC1, MIC2, LINE1 and LINE2) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: 1: Mute, 0:Unmute (Output Amplifier Mute, default=1). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. The volume 0dB/10dB/20dB/30dB in 10dB per step (default=0, 0dB). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). Codec Response for NID=14h, 15h and 16h (Pin widget: SPK-OUT, HP-OUT and MONO-OUT) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: 1: Mute, 0:Unmute (Output Amplifier Mute, default=1). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). Codec Response for NID=0Bh (Mixer) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute, 1: Mute (Default for all) Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. Specifying the volume from -34.5dB~+12dB in 1.5dB step (Default: 17h, 0dB). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). Index=0 (MIC1) Index=1 (MIC2) Index=2 (LINE1) Index=3 (LINE2) Index=4 (PCBEEP) Index>5 (Other) Mute [7] 0/1 0/1 0/1 0/1 0/1 0 Gain [6:0] 0s 0s 0s 0s 0s 0 Default[7:0] 10010111 10010111 10010111 10010111 10010111 00000000 Codec Response for NID=07h, 08h (ADCs) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute, 1: Mute (Default) Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0]. Specifying the volume from –17dB~ 29dB in 1.0dB step. Node Gain[6:0] Default Gain Range MIC ADC(NID=07h) 0010001b=11h (0dB) –17dB~29dB in 1.0dB step LINE ADC( NID=08h) 0010001b=11h (0dB) –17dB~29dB in 1.0dB step Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). 31:0 Not Supported (returns 00000000h). This verb is used to set amplifier gain/attenuation in each widget. Table 44. Verb – Set Amplifier Gain (Verb ID=3h) 15 Set Output Amp. 1 indicates output amplifier gain will be set. 14 Set Input Amp. 1 indicates input amplifier gain will be set. 13 Set Left Amp. 1 indicates left amplifier gain will be set. 12 Set Right Amp. 1 indicates right amplifier gain will be set. 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets). 6:0 Gain[6:0]. A 7-bit step value specifying the amplifier gain.
Table 45. Verb – Get Converter Format (Verb ID=Ah) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV). The ALC269 does not support Divisor. Always read as 000b. 31:0 Not Supported (returns 00000000h).
Table 46. Verb – Set Converter Format (Verb ID=2h) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV).
Table 47. Verb – Get Power State (Verb ID=F05h) 5:4 PS-Act. Actual Power State [1:0]. (NID=01h), PS-Act is always equal to PS-Set. 1:0 PS-Set, Set Power State [1:0]. PS-Set controls the current power setting of the referenced node. Note: Specific blocks will be powered down in each power state. Refer to section 7.5 Power Management, page 23. 31:0 Not Supported (returns 00000000h). Table 48. Verb – Set Power State (Verb ID=705h) 5:4 PS-Act. Actual Power State [1:0]. PS-Act indicates the actual power state of the referenced node. 1:0 PS-Set. Set Power State [1:0].
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 31:0 Not Supported (returns 00000000h). Table 50. Verb – Set Converter Stream, Channel (Verb ID=706h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. (NID=07h, 08h). Other widgets will ignore this verb.
Table 51. Verb – Get Pin Widget Control (Verb ID=F07h) SPK-OUT, HP-OUT, MONO-OUT, MIC1, MIC2, LINE1, LINE2, PCBEEP, S/PDIF_OUT, and S/PDIF-OUT2). 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit). 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit). 2:0 VrefEn (Vrefout Enable Control). 31:0 Not Supported (returns 00000000h). Table 52. Verb – Set Pin Widget Control (Verb ID=707h) 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit). 2:0 VrefEn (Vrefout Enable Control).
unsolicited response to inform software of a real time event. Table 53. Verb – Get Unsolicited Response Control (Verb ID=F08h) 7 Unsolicited Response is Enabled. 3:0 Assigned Tag for Unsolicited Response. The tag[3:0] is assigned by software to determine which widget generates unsolicited responses. 31:0 Not Supported (returns 00000000h). Enable a widget to generate an unsolicited response. Table 54. Verb – Set Unsolicited Response Control (Verb ID=708h) 7 Enable Unsolicited Response. 3:0 Tag for Unsolicited Response.
Returns the Presence Detect status and the impedance of a device attached to the pin. Table 55. Verb – Get Pin Sense (Verb ID=F09h) Note: The ALC269 does not support impedance sensing. Read as 0’ s. 31:0 Not Supported (returns 00000000h). Table 56. Verb – Execute Pin Sense (Verb ID=709h) 0 Right (Ring) Channel Select. Note: The ALC269 does not support ‘Execute Pin Sense’ and will ignore this verb and respond with 0’ s.
Read the 32-bit sticky register for each Pin Widget configured by software. Table 57. Verb – Get Configuration Default (Verb ID=F1Ch) 31:0 32-bit configuration info rmation for each pin widget. 1Eh~1Fh such as placement and expected default device. Table 58. Verb – Set Configuration Default Bytes 0, 1, 2, 3
Table 59. Verb – Get BEEP Generator (Verb ID=F0Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Table 60. Verb – Set BEEP Generator (Verb ID=70Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 61. Verb – Get GPIO Data (Verb ID=F15h) 7:2 GPIO[7:2] Data. Not supported in the ALC269. The value written (output) or sensed (input) on the corresponding pin if it is enabled. Table 62. Verb – Set GPIO Data (Verb ID=715h) 7:2 GPIO[7:2] Output Data. Not supported in the ALC269. The value written determines the value driven on a pin that is configured as an output pin.
Table 63. Verb – Get GPIO Enable Mask (Verb ID=F16h) 0: The corresponding GPIO pin is disabled and is in Hi-Z state. 1: The corresponding GPIO pin is enabled. It’s behavior is determined by the GPIO direction control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 64. Verb – Set GPIO Enable Mask (Verb ID=716h) 7:2 GPIO[7:2] Enable Mask. Not supported in the ALC269. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 65. Verb – Get GPIO Direction (Verb ID=F17h) 7:2 GPIO[7:2] Direction Control. Not supported in the ALC269. 1:0 GPIO[1:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 66. Verb – Set GPIO Direction (Verb ID=717h) 7:2 GPIO[7:2] Direction Control. Not supported in the ALC269. 1:0 GPIO[1:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 67. Verb – Get GPIO Wake Enable Mask (Verb ID=F18h) 7:2 GPIO[7:2] Wake Enable Mask. Not supported in the ALC269. 1:0 GPIO[1:0] Wake Enable Mask. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 68. Verb – Set GPIO Wake Enable Mask (Verb ID=718h) 1:0 GPIO[1:0] Wake Enable Mask. Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Table 69. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) 7:2 GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC269. 1:0 GPIO[1:0] Unsolicited Enable Mask. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 70. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) 1:0 GPIO[1:0] Unsolicited Enable Mask. Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled.
Table 71. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets in the ALC269 to return to their power-on default state. Table 72. Verb –Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh) NID=06h, 10h (S/PDIF-OUT, S/PDIF-OUT2) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0]). 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame).
Table 73. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 6:0 CC[6:0] (Category Code).
Table 74. Get/Set Volume Knob Widget (Verb ID=F0Fh/70Fh) 0: The volume generated by an external HW volume control will be sent by unsolicited response. Note: The ALC269 does not support volume knob widget and will ignore this verb and respond with 0’ s. 0: The volume generated by an external HW volume control will be sent by unsolicited response. Note: The ALC269 does not support volume knob widget and will ignore this verb and respond with 0’ s. Table 75. Get/Set Subsystem ID [31:0] (Verb ID=F20h / 723h~720h to Set Bit[31:0]) 31:16 Subsystem ID[23:8] (Default=10Ech). 15:8 Subsystem ID[7:0] (Default=02h). 7:0 Assembly ID[7:0] (Default=69h).
Table 76. Get/Set EAPD Enable (Verb ID=F0Ch / 70Ch ) The ALC269 does not support swapping left and right channel, it is read as 0. 0: EAPD pin state is low potential to power down external amplifier in all power state of AFG. 1: EAPD pin state is high potential to power up external amplifier in all power state of AFG. The ALC269 does not support BTL output, it is read as 0. The ALC269 does not support swapping left and right channel, it is read as 0. 0: EAPD pin state is low potential to power down external amplifier in all power state of AFG. 1: EAPD pin state is high potential to power up external amplifier in power state of AFG. The ALC269 does not support BTL output, it is read as 0.
- Electrical Characteristics
Table 77. Absolute Maximum Ratings Note1: DVDD-IO must be lower than DVDD. Note2: PVDD must be greater than AVDD, and keep PVDD-AVDD ≤ 0.8V for best performance. When (PVDD ≥ AVDD + 1V), THD+N will be degraded when playing at full power output. suppress such surges, 10µF tantalum capacitors are required at PVDD1 and PVDD2. DVDD-IO=3.3V±5%, Tambient=25°C, with 50pF external load. Table 78. Threshold Voltage
Table 79. Digital Filter Characteristics DVDD=3.3V, Tambient=25°C, with 75Ω external load. Table 80. S/PDIF Input/Output Characteristics
Table 81. Link Reset and Initialization Timing
4 BCLK 4 BCLK > = 4 BCLK Initialization Sequence
Figure 15. Link Reset and Initialization Timing
Table 82. Link Timing Parameters at the Codec Figure 16. Link Signals Timing
Table 83. S/PDIF Output Timing *1: Bit parameters for 48kHz sample rate of S/PDIF-OUT. Figure 17. Output Timing The ALC269 does not support codec test mode or Automatic Test Equipment (ATE) mode.
- 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
- 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 84. Analog Performance Note: FSA=Full-Scale with A-weighting filter. FS=Full-Scale.
Table 85. Class-D Power Amplifier Performance
Figure 18. Filter Connection
Figure 19. Power and Jack Connection
Figure 20. S/PDIF-OUT Connection
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 69 Track ID: JATR-1076-21 Rev. 1.3 11. Mechanical Dimensions Optional support bar does not appear in the ALC269Q package 0.129mm0.40mm 0.28mm (mm)(mm )
High Definition Audio Codec with Embedded Class-D Speaker Amplifier 70 Track ID: JATR-1076-21 Rev. 1.3 11.1. Mechanical Dimensions Notes SYMBOL MILLIMETER INCH MIN. TYPICAL MAX. MIN. TYPICAL MAX A3 0.20 REF 0.008 REF D 7.00 BSC 0.276 BSC D1 6.75 BSC 0.266 BSC E 7.00 BSC 0.276 BSC E1 6.75 BSC 0.266 BSC e 0.50 BSC 0.020 BSC θ 0 o - 14 o 0 o - 14 o
Table 86. Ordering Information Note: See page 7 for ‘Green’ package and version identification.