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(ALC268-GR, ALC268Q-GR, ALC268-VB1-GR) 2+2 CHANNEL HIGH DEFINITION AUDIO CODEC DATASHEET Rev. 1.3

25 April 2008

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

2+2 Channel High Definition Audio Codec ii Track ID: JATR-1076-21 Rev. 1.3 COPYRIGHT ©2008 Realtek Semiconductor Corp. A ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular pu rpose. Realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC268 Series Audio codecs. Though every effort has been made to assure that this document is current and accurate, more information may have become available subsequent to the productio n of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2006/09/04 First release. 1.1 2007/12/12 Add ALC268-VB (Version B) information (Intermediate Release) 1.2 2008/01/07 Updated ALC268 version B part number in section 12 Ordering Information, page 72 (Intermediate Release). 1.3 2008/04/25 Updated ALC268 version B part number in section 12 Ordering Information, page 72.

2+2 Channel High Definition Audio Codec iii Track ID: JATR-1076-21 Rev. 1.3 Table of Contents

2+2 Channel High Definition Audio Codec iv Track ID: JATR-1076-21 Rev. 1.3 8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 50

2+2 Channel High Definition Audio Codec v Track ID: JATR-1076-21 Rev. 1.3

TABLE 58. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)50

2+2 Channel High Definition Audio Codec 1 Track ID: JATR-1076-21 Rev. 1.3 1. General Description The ALC268 series (ALC268-VB1/ALC268/ALC268Q) 4-Channel ADC High Definition Audio Codecs with UAA (Universal Audio Architecture). Featuri ng two stereo DACs and two stereo ADCs, the 4 DAC channels support stereo sound playback on the rear panel and independent stereo sound output on the front panel simultaneously (multiple streaming). The two stereo ADCs integrate two stereo and independent analog sound inputs. The ALC268-GR and ALC268Q-GR meet the current WLP3.10 (Windows ® Logo Program) requirements. The ALC268-VB1-GR is the B ve rsion of the ALC268 and meets future WLP requirements that become effective from 01 June 2008, bringing PC sound quality closer to consumer electronic devices. The ALC268 series support up to 4 digital microphone channels (micro phone array) with Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously, significantly improving sound quality for PC VoIP applications. The S/PDIF output offers easy connection of PCs to high quality consumer electronic products such as digital decoders and speakers. The ALC268 series support host audi o controller from the Intel ICH series and upcomi ng PCH chipset, and also from any other HDA compatible audio c ontroller. With EAX/Dire ct Sound 3D/I3DL2/A3D compatibility, and excellent software utilities like environment sound emulation, multiple and independent software equalizer bands, dynamic range control, optional Dolby ® Digital Live, Dolby ® PCEE programs and SRS ® TrueSurround HD, the ALC268 provides an excellent multimedia experience for PC users. Model Differences The ALC268-VB1 is fully pin compatible and soft ware backward compatible with the ALC268. Board designs using the ALC268 can use the ALC268-VB1 di rectly without PCB (Printed Circuit Board) or software changes. Three main functions have been added in the ALC268-VB:

  • Meets future Windows® Logo Program (WLP) requirements that become effective from 01 June 2008
  • Integrates a DC cancellation filter to cancel DC offset from digital microphones (becoming common in notebook and Ultra Mobile PCs)
  • ADCs support 24-bit format recording

2+2 Channel High Definition Audio Codec 2 Track ID: JATR-1076-21 Rev. 1.3 2. Features 2.1. Hardware Features „ Meets WLP (Windows Logo Program) 3.10 premium audio requirements „ ALC268-VB1 meets future WLP requirements that become effective from 01 June 2008 „ 95dB Signal-to-Noise Ratio DAC performance and 90dB Signal-to-Noise Ratio ADC performance „ Two stereo DACs support independent 16/20/24-bit PCM format playback „ Two stereo ADCs support independent 16/20-bit PCM format recording „ Two stereo ADCs support independent 16/20/24-bit PCM format recording (ALC268-VB1) „ All DACs supports 44.1/48/96/192kHz sample rate „ All ADCs support 44.1/48/96kHz sample rate „ 16/20/24-bit S/PDIF-OUT supports 44.1/48/96/192kHz sample rate „ Up to four channels of microphone input are supported for AEC/BF applications „ Supports MONO line output with independent volume control „ High-quality analog differential CD input „ Supports external PCBEEP input and built-in digital BEEP generator „ Software selectable 2.5V/3.75V/4.2V VREFOUT „ Two jack detection pins, each designed to detect up to 4 jacks „ 1dB resolution of analog output volume control „ Programmable 20dB and 40dB boost for analog microphone input „ Supports hardware digital volume control for digital microphone input „ Built-in headphone amplifiers for port-A and port-D „ 4 GPIOs (GPIO0/GPIO3 are digital GPIO shared with digital MIC interface, GPIO1/GPIO2 are analog) for customized applications „ EAPD (External Amplifier Power Down) is supported

2+2 Channel High Definition Audio Codec 3 Track ID: JATR-1076-21 Rev. 1.3 „ Supports Anti-pop mode when analog power AVDD is on and digital power is off analog power „ The ALC268-VB integrates a DC cancellation filter to cancel DC offset from digital microphones „ 48-pin LQFP ‘Green’ package (ALC268, ALC268-VB) „ 48-pin QFN ‘Green’ package (ALC268Q only) 2.2. Software Features „ Meets Microsoft Windows Logo Program requirements „ EAX™ 1.0 & 2.0 compatible „ Direct Sound 3D™ compatible „ A3D™ compatible „ I3DL2 compatible „ HRTF 3D Positional Audio „ Emulation of 26 sound environments to enhance gaming experience „ Multi-band software equalizer and tools „ Voice Cancellation and Key Shifting effect „ Dynamic range control (expander, compressor and limiter) with adjustable parameters „ Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience „ Provides 10-foot GUI for Windows Media Center „ Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application „ Smart multiple streaming operation „ HDMI audio driver for AMD platform „ Dolby® PCEE program™ (optional software feature)

2+2 Channel High Definition Audio Codec 4 Track ID: JATR-1076-21 Rev. 1.3 „ SRS® TrueSurround HD (optional software feature) „ Fortemedia® SAM™ technology for voice processi ng (Beam Forming and Acoustic Echo Cancellation) (optional software feature) 3. System Applications „ Windows Vista premium desktop and notebook PCs „ Ultra Mobile PCs

Figure 3. Pin Assignments ALC268/ALC268-VB (LQFP-48) Note: The ALC268-VB and ALC268 are pin-to-pin compatible.

Figure 4. Pin Assignments ALC268Q (QFN-48) Note: The ALC268Q is NOT pin compatible with the ALC268/ALC268-VB1.

Table 1. Digital I/O Pins

Table 2. Analog I/O Pins

Table 3. Filter/Reference Table 4. Power/Ground

  1. High Definition Audio Link Protocol

with a 48kHz frame rate. Figure 5 shows the basic concept of the HDA link protocol. Figure 5. HDA Link Protocol

Table 5. Link Signal Definitions BCLK 24.0MHz of bit clock sourced from the HDA controller and connecting to all codecs. controller and connects to all codecs. least one SDO. To extend outbound bandwidth, multiple SDOs may be supported. rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID. HDA controller and connects to all codecs. Table 6. HDA Signal Definitions BCLK Controller Output Global 24.0MHz Bit Clock. SYNC Controller Output Global 48kHz Frame Sync and Outbound Tag Signal. SDO Controller Output Serial Data Output from Controller. SDI Codec/Controller Input/Output Serial Data Input from Codec. Weakly pulled down by the controller. RST# Controller Output Global Active Low Reset Signal. Figure 6. Bit Timing

stream data is always carried on SDO0, the second bit on SDO1 and so forth. is always transmitted on SDO0, and copied on SDO1. Figure 10. Striped Stream on Multiple SDOs

Figure 13. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz. blocks are transmitted every 160 frames.

rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames. and interleave an empty frame between non-empty frames (Table 9, page 19). Table 7. Defined Sample Rate and Transmission Rate Table 8. 48kHz Variable Rate of Delivery Timing

Table 9. 44.1kHz Variable Rate of Delivery Timing

2+2 Channel High Definition Audio Codec 20 Track ID: JATR-1076-21 Rev. 1.3 7.3. Reset and Initialization There are two types of reset within an HDA link:

  • Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
  • Codec Reset. Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events: 1. Link Reset 2. Codec Reset 3. Codec changes its power state (For example, hot docking a codec to an HDA system) 7.3.1. Link Reset A link reset may be caused by 3 events: 1. The HDA controller asserts RST# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ b it in the Global Control Re gister (GCR) of the HDA controller 3. Software initiates power management sequences. Figure 14, page 21, shows th e ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v) Enter ‘Link Reset’: n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset o As the controller completes the current frame, it does not signal the normal 8-Bit frame SYNC at the end of the frame p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state r All link signals driven by controller and codecs should be tri-state via internal pull-low resistors

4 BCLK 4 BCLK

Figure 14. Link Reset Timing

o The codec will stop driving the SDI during this turnaround period. pqrs The controller drives SDI to assign a CAD to the codec. t The controller releases the SDI after the CAD has been assigned. Figure 15. Codec Initialization Sequence

controls parameters in the codec. Table 10. 40-Bit Commands in 4-Bit Verb Format Table 11. 40-Bit Commands in 12-Bit Verb Format software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 12. Solicited Response Format Table 13. Unsolicited Response Format

changes in widgets are driven by software. Table 14 shows the System Power State Definitions. various power states depending on system configuration. and input converters (ADCs) have no individual power control to supply fine-grained power control. Table 14. System Power State Definitions D0 All power on. Individual DACs and ADCs can be powered up or down as required. reference off (D1 + analog reference off). D3 (Hot) Power still supplied. The codec stops the internal clock. State is maintained. D3 (Cold) All power removed. State lost. Table 15. Power Controls in NID=01h Table 16. Powered Down Conditions sequences are supported. All states are maintained if DVDD is supplied. DAC powered down Analog block and digital filter are powered down. ADC powered down Analog block and digital filter ar e powered down. The data on SDATA-IN is quiet. Headphone Driver powered down All headphone drivers are powered down. individual pin complex are still alive.

  1. Supported Verbs and Parameters

not supported by the addressed widget, it will respond with 32 bits of ‘0’. detailed information about supported parameters. Table 17. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) 31:16 Vendor ID=10Ech (Realtek’s PCI vendor ID). Note: The Root Node (NID=00h) supports this parameter. Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 31:24 Reserved. Read as 0’s. 23:20 MajRev. The major version number (in decimal) of the HDA Spec to which the ALC268 is fully compliant. 15:8 Revision ID. The vendor’s revision number. 00h is for the first silicon version A, 01h is for the second version B, etc. 7:0 Stepping ID. The vendor’s stepping number within the given Revision ID. Note: The Root Node (NID=00h in the ALC268) supports this parameter. For example the Revision ID=00h and Stepping ID=01h stand for the silicon is A1 version.

associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) 31:24 Reserved. Read as 0’s. 23:16 Starting Node Number. The starting node number in the sequential widgets. 7:0 Total Number of Nodes. For a root node, the total number of function groups in the root node. For a function group, the total number of widget nodes in the function group. Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) 03h~7Fh: Reserved 80h~FFh: Vendor Defined Function. Note: The Audio Function Group (NID=01h) supports this parameter. Table 22. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h) 31:17 Reserved. Read as 0’s. 16 Beep Generator. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0’s. Note: The Audio Function Group (NID=01h) supports this parameter.

Table 23. Parameter – Audio Widget Capa bilities (Verb ID=F00h, Parameter ID=09h) 31:24 Reserved. Read as 0’s. 19:16 Delay. Samples delayed between the HDA link and widgets. 15:11 Reserved. Read as 0’s. 8 ConnList. Connection List. 7 UnsolCap. Unsolicited Capable. 6 ProcWidget. Processing Widget. 3 AmpParOvr, AMP Param Override. 2 OutAmpPre, Out AMP Present.

own parameters to provide supported formats if their ‘Format Override’ bit is set. Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) 31:21 Reserved. Read as 0’s. 20 B32: Indicates whether 32-bit audio format is supported. 19 B24: Indicates whether 24-bit audio format is supported. 18 B20: Indicates whether 20-bit audio format is supported. 17 B16: Indicates whether 16-bit audio format is supported. 16 B8: Indicates whether 8-bit audio format is supported. 15:12 Reserved. Read as 0’s. 11 R12: Indicates whether 384kHz (=8*48kHz) rate is supported. 10 R11: Indicates whether 192kHz (=4*48kHz) rate is supported. 9 R10: Indicates whether 176.4kHz (=4*44.1kHz) rate is supported. 8 R9: Indicates whether 96kHz (=2*48kHz) rate is supported. 7 R8: Indicates whether 88.2kHz (=2*44.1kHz) rate is supported. 6 R7: Indicates whether 48kHz rate is supported. 5 R6: Indicates whether 44.1kHz rate is supported. 4 R5: Indicates whether 32kHz (=2/3*48kHz) rate is supported. 3 R4: Indicates whether 22.05kHz (=1/2*44.1kHz) rate is supported. 2 R3: Indicates whether 16kHz (=1/3*48kHz) rate is supported. 1 R2: Indicates whether 11.025kHz (=1/4*44.1kHz) rate is supported. 0 R1: Indicates whether 8kHz (=1/6*48kHz) rate is supported.

have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Note: Input converters and output converters support this parameter. The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 26. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch) 31:16 Reserved. Read as 0’s. 15:8 VREF Control Capability. 7 L-R Swap. Indicates the capability of swapping the left and rights. 6 Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins. 5 Input Capable. ‘1’ indicates this pin complex supports input. 4 Output Capable. ‘1’ indicates this pin complex supports output. 3 Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone. 2 Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in. 1 Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement. ‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type. Note: Only Pin Complex widgets support this parameter.

their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 27. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. Indicates which step is 0dB. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 28. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. Indicates which step is 0dB.

Parameters in this node provide audio function widget connection information. Table 29. Parameter – Connect List Le ngth (Verb ID=F00h, Parameter ID=0Eh) input, and there is no Connection Select Control (Not a MUX widget). Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) 1: Power state D3 is supported. 1: Power state D2 is supported. 1: Power state D1 is supported. 1: Power state D0 is supported. Table 31. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h) 31:16 Reserved. Read as 0’s. 15:8 NumCoeff. Number of Coefficient.

Table 32. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h) The ALC268 does not support GPIO wake up function. The ALC268 supports GPIO unsolicited response. 29:24 Reserved. Read as 0’s. Two GPIO pins are supported. Table 33. Parameter – Volume Knob Capa bilities (Verb ID=F00h, Parameter ID=13h) The number of steps in the range of the Volume Control Knob. Note: The ALC268 does not support volume control knob.

Table 34. Verb – Get Connection Select Control (Verb ID=F01h) 7:0 Connection Index Currently Set (Default value is 00h). 7:0 Connection Index Currently Set (Default value is 00h). 31:0 Not Supported (returns 00000000h). Table 35. Verb – Set Connection Select (Verb ID=701h) Note: Only MUX NID-23h and 24h support this verb.

Table 36. Verb – Get Connection List Entry (Verb ID=F02h) 31:8 Connection List Entry (N+3), (N+2), and (N+1). 7:0 Connection List Entry (N). Returns 24h (Sum Widget) for N=0~3. Returns 00h for N>3. 31:8 Connection List Entry (N+3), (N+2), and (N+1). 7:0 Connection List Entry (N). Returns 23h (Sum Widget) for N=0~3. Returns 00h for N>3. 31:24 Connection List Entry (N). 23:16 Connection List Entry (N+2). 15:8 Connection List Entry (N+1). Returns 03h (LOUT2 DAC) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 02h (LOUT1 DAC) for N=0~3. Returns 00h for N>3. 31:24 Connection List Entry (N). 23:16 Connection List Entry (N+2). 15:8 Connection List Entry (N+1). Returns 1Dh (PCBEEP) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 02h (LOUT1 DAC) for N=0~3. Returns 00h for N>3.

2+2 Channel High Definition Audio Codec 35 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=10h) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 1Dh (PCBEEP) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 03h (LOUT2 DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID =18h (MIC1, port-B), 1Ah (LINE1, port-C) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 02h (LOUT1 DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID =14h (LOUT, port-D) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Fh (Mixer) for N=0~3. Returns 00h for N>3. Codec Response for NID =15h (HPOUT, port-A) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 10h (Mixer) for N=0~3. Returns 00h for N>3.

2+2 Channel High Definition Audio Codec 36 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=16h (Pin Widget: MONO-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Returns 000000h. 7:0 Connection List Entry (N). Returns 0Eh for N=0~3. Returns 00h for N>3. Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Returns 000000h. 7:0 Connection List Entry (N). Returns 06h (S/PDIF-OUT Converter) for N=0~3. Returns 00h for N>3. Codec Response for NID=23h (MUX Widget) Bit Description 31:24 Connection List Entry (N+3). Returns 1Ch (Pin Complex – CD) for N=0~3. Returns 00h for N>3. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1, port-C) for N=0~3. Returns 12h (Pin Complex – Digital MIC 1&2) for N=4~7. Returns 00h for N>7. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2, port-F) for N=0~3. Returns 15h (Pin Complex – HPOUT, port-A) for N=4~7. Returns 00h for N>7. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1, port-B) for N=0~3. Returns 14h (Pin Complex – LOUT, port-D) for N=4~7. Returns 00h for N>7. Codec Response for NID=24h (MUX Widget) Bit Description 31:24 Connection List Entry (N+3). Returns 1Ch (Pin Complex – CD) for N=0~3. Returns 00h for N>3. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1, port-C) for N=0~3. Returns 13h (Pin Complex – Digital MIC 3&4) for N=4~7. Returns 00h for N>7. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2, port-F) for N=0~3. Returns 15h (Pin Complex – HPOUT, port-A) for N=4~7. Returns 00h for N>7. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1, port-B) for N=0~3. Returns 14h (Pin Complex – LOUT, port-D) for N=4~7. Returns 00h for N>7. Codec Response for Other NID Bit Description 31:0 Not Supported (returns 00000000h).

Table 37. Verb – Get Processing State (Verb ID=F03h) 31:0 Not Supported (returns 00000000h). Table 38. Verb – Set Processing State (Verb ID=703h) Table 39. Verb – Get Coefficient Index (Verb ID=Dh) 31:16 Reserved. Read as 0’s. 31:0 Not Supported (returns 00000000h).

Table 40. Verb – Set Coefficient Index (Verb ID=5h) Table 41. Verb – Get Processing Coefficient (Verb ID=Ch) 31:16 Reserved. Read as 0’s. 15:0 Processing Coefficient. 31:0 Not Supported (returns 00000000h). Table 42. Verb – Set Processing Coefficient (Verb ID=4h)

This verb is used to get gain/attenuation settings from each widget. Table 43. Verb – Get Amplifier Gain (Verb ID=Bh) 3:0 Index[3:0] for Input Source. Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored. 7 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 4 (No Output Amplifier Gain).

2+2 Channel High Definition Audio Codec 40 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=0Fh (LINE-OUT Sum Widgets) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute; 1: Mute Node Index[3:0]=0 (from LOUT1) Index[3:0]=1 (from BEEP) Index[3:0]=Other Default of Bit [7] Default of Bit [7] LINE-OUT Sum 0 (Unmute) 1 (Mute) 0 Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain). Codec Response for NID=10h (HP-OUT Sum Widgets) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute; 1: Mute Node Index[3:0]=0 (from LOUT2) Index[3:0]=1 (from BEEP) Index[3:0]=2 (from LOUT1) Index[3:0]=Other Default of Bit [7] Default of Bit [7] Default of Bit [7] LINE-OUT Sum 1 (Mute) 1 (Mute) 1 (Mute) 0 Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain). Codec Response for NID=18h (MIC1, port-B) and 1Ah (LINE1, port-C) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0 (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0:Unmute; 1:Mute (Default=1) 6:0 Payload[15] is 0 in ‘Get Amplifie r Gain’: Input Amplifier Gain [6:0]. The volume 0dB/20dB/40dB in 20dB per step (Default=0, 0dB). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain). Codec Response for NID=19h (MIC2, port-F) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0 (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifie r Gain’: Input Amplifier Gain [6:0]. The volume 0dB/20dB/40dB in 20dB per step (Default=0, 0dB). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain).

2+2 Channel High Definition Audio Codec 41 Track ID: JATR-1076-21 Rev. 1.3 Codec Response for NID=14h (LINE-OUT, port-D) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0 (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0:Unmute; 1:Mute (Default=1) 6:0 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain). Codec Response for NID=15h (HP-OUT, port-A) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0 (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0:Unmute; 1:Mute (Default=1) 6:0 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain). Codec Response for NID=1Dh (PCBEEP) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0 (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0] specifying the volume from –24dB to 0dB in 3dB per step (Default=0000001b, -21dB). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute). Codec Response for NID=12h (Digital MIC DMIC-12) and 13h (Digital MIC DMIC-34) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0 (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain). Codec Response for NID=16h (MONO-OUT) Bit Description 31:8 0’s. 7 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0 (No Input Amplifier Mute). Payload[15] is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute. 0:Unmute; 1:Mute (Default=1) 6:0 Payload[15] is 0 in ‘Get Amplifier Gain ’: Read as 0’s (No Input Amplifier Gain). Payload[15] is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Gain).

7 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Mute for all index). 6:0 Payload[15] is 0 in ‘Get Amplifier Gain’: Read as 0’s (No Input Amplifier Gain for all index). to 30dB in 1.5dB per step (Default=0000001b, -15dB). 31:0 Not Supported (returns 00000000h). This verb is used to set amplifier gain/attenuation in each widget. Table 44. Verb – Set Amplifier Gain (Verb ID=3h) 1 indicates output amplifier gain will be set. 1 indicates input amplifier gain will be set. 1 indicates left amplifier gain will be set. 1 indicates right amplifier gain will be set. 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets). A 7-bit step value specifying the amplifier gain.

Table 45. Verb – Get Converter Format (Verb ID=Ah) Codec Response for NID=02h, 03h, 06h (Output Converters: LOUT1 DAC, LOUT2 DAC, S/PDIF-OUT). 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV). The ALC268 does not support Divisor. Always read as 000b. 31:0 Not Supported (returns 00000000h).

Table 46. Verb – Set Converter Format (Verb ID=2h) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV). Table 47. Verb – Get Power State (Verb ID=F05h) 5:4 PS-Act. Actual Power State [1:0]. (NID=01h), PS-Act is always equal to PS-Set. 1:0 PS-Set. Set Power State [1:0]. PS-Set controls the current power setting of the referenced node. Note: Specific blocks will be powered down in each power state. Refer to section 7.5 Power Management, page 24. 31:0 Not Supported (returns 00000000h).

Table 48. Verb – Set Power State (Verb ID=705h) 5:4 PS-Act. Actual Power State [1:0]. PS-Act indicates the actual power state of the referenced node. 1:0 PS-Set. Set Power State [1:0]. Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h) Codec Response for NID=02h, 03h, 06h (Output Converters: LOUT1 DAC, LOUT2 DAC, S/PDIF-OUT). The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 31:0 Not Supported (returns 00000000h).

Table 50. Verb – Set Converter Stream, Channel (Verb ID=706h) 7:4 Set Stream[3:0]. The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. well as n+1 for its left and right channel. (NID=07h, 08h). Other widgets will ignore this verb. Table 51. Verb – Get Pin Widget Control (Verb ID=F07h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O unit). Note: Only HP-OUT (NID=15h) and LINE-OUT (NID=14h) support the headphone amplifier. 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit). PCBEEP (NID=1Dh) do not support output. 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit). Note: MONO-OUT (NID-16h) does not support input. 2:0 VrefEn (Vrefout Enable Control). Note: Only MIC1 (NID=18h), MIC2 (NID=19h), and LINE1 (NID=1Ah) support reference voltage outputs. 31:0 Not Supported (returns 00000000h).

Table 52. Verb – Set Pin Widget Control (Verb ID=707h) Note: Only HP-OUT (NID=15h) and LINE-OUT (NID=14h) support the headphone amplifier. PCBEEP (NID=1Dh) do not support output. 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O unit). Note: MONO-OUT (NID-16h) does not support input. 2:0 VrefEn (Vrefout Enable Control). Note: Only MIC1 (NID=18h), MIC2 (NID=19h), and LINE1 (NID=1Ah) support reference voltage outputs. unsolicited response to inform software of a real-time event. Table 53. Verb – Get Unsolicited Response Control (Verb ID=F08h) 7 Unsolicited Response is Enabled. 3:0 Assigned Tag for Unsolicited Response. The tag[3:0] is assigned by software to determine which widget generates unsolicited responses. 31:0 Not Supported (returns 00000000h).

Enable a widget to generate an unsolicited response. Table 54. Verb – Set Unsolicited Response Control (Verb ID=708h) 7 Enable Unsolicited Response. enabled to generate unsolicited responses. Returns the Presence Detect status and the impedance of a device attached to the pin. Table 55. Verb – Get Pin Sense (Verb ID=F09h) Note: The ALC268 does not support impedance sensing. Read as 0’ s. 31:0 Not Supported (returns 00000000h).

Table 56. Verb – Execute Pin Sense (Verb ID=709h) 0 Right (Ring) Channel Select. Note: The ALC268 does not support ‘Execute Pin Sense’ and will ignore this verb and respond with 0’ s. Read the 32-bit sticky register for each Pin Widget configured by software. Table 57. Verb – Get Configuration Default (Verb ID=F1Ch) 31:0 32-bit configuration info rmation for each pin widget.

1Eh~1Fh such as placement and expected default device. Table 58. Verb – Set Configuration Default Bytes 0, 1, 2, 3 Table 59. Verb – Get BEEP Generator (Verb ID=F0Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.

Table 60. Verb – Set BEEP Generator (Verb ID=70Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 61. Verb – Get GPIO Data (Verb ID=F15h) 7:4 GPIO[7:4] Data. Not supported in the ALC268. The value written (output) or sensed (input) on the corresponding pin if it is enabled.

Table 62. Verb – Set GPIO Data (Verb ID=715h) 7:4 GPIO[7:4] Output Data. Not supported in the ALC268. The value written determines the value driven on a pin that is configured as an output pin. Table 63. Verb – Get GPIO Enable Mask (Verb ID=F16h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 64. Verb – Set GPIO Enable Mask (Verb ID=716h) 7:4 GPIO[7:4] Enable Mask. Not supported in the ALC268. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 65. Verb – Get GPIO Direction (Verb ID=F17h) 7:4 GPIO[7:4] Direction Control. Not supported in the ALC268. 3:0 GPIO[3:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 66. Verb – Set GPIO Direction (Verb ID=717h) 7:4 GPIO[7:4] Direction Control. Not supported in the ALC268. 3:0 GPIO[3:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 67. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) 7:4 GPIO[7:4] Unsolicited Enable Mask. Not supported in the ALC268. 3:0 GPIO[3:0] Unsolicited Enable Mask. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 68. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) 3:0 GPIO[3:0] Unsolicited Enable Mask. Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled. Table 69. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets in the ALC268 to return to their power-on default state.

Table 70. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh) NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0]). 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame).

Table 71. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 6:0 CC[6:0] (Category Code).

Table 72. Get/Set Volume Knob Widget (Verb ID=F0Fh/70Fh) Note: The ALC268 does not support volume knob widget will ignore this verb and respond with 0’ s. Note: The ALC268 does not support volume knob widget will ignore this verb and respond with 0’ s. Table 73. Get/Set Subsystem ID [31:0] (V erb ID=F20h / 723h~720h to Set Bit[31:0]) 31:16 Subsystem ID[23:8] (Default=10Ech). 15:8 Subsystem ID[7:0] (Default=02h). 7:0 Assembly ID[7:0] (Default=68h).

  1. Electrical Characteristics

Table 74. Absolute Maximum Ratings Note: DVDD-IO must be lower than DVDD. If customers have lower AVDD(=3.0V) request, please contact Realtek sales representatives or agents. DVDD-IO=3.3V±5%, Tambient=25°C, with 50pF external load. Table 75. Threshold Voltage

Table 76. Digital Filter Characteristics DVDD=3.3V, Tambient=25°C, with 75Ω external load. Table 77. S/PDIF Input/Output Characteristics

Table 78. Link Reset and Initialization Timing

4 BCLK 4 BCLK >= 4 BCLK

Figure 16. Link Reset and Initialization Timing

Table 79. Link Timing Parameters at the Codec Figure 17. Link Signals Timing

Table 80. S/PDIF Output Timing *1: Bit parameters for 48kHz sample rate of S/PDIF-OUT. Figure 18. Output Timing The ALC268 does not support codec test mode or Automatic Test Equipment (ATE) mode.

  • 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
  • 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz

Table 81. Analog Performance Note: FSA=Full-Scale with A-weighting filter. FS=Full-Scale.

application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet. Figure 19. Filter Connection

Figure 20. Power and Rear Panel Jack Connection

Figure 21. Front Panel Header and Front Panel I/O Cable

Figure 22. S/PDIF-OUT Connection

2+2 Channel High Definition Audio Codec 70 Track ID: JATR-1076-21 Rev. 1.3 11. Mechanical Dimensions 11.1. LQFP-48 Mechanical Dimensions (ALC268/ALC268-VB) L SYMBOL MILLIMETER INCH MIN. TYP MAX. MIN. TYP MAX A1 0.05 - 0.15 0.002 - 0.006 c 0.09 - 0.20 0.004 - 0.008 D 9.00 BSC 0.354 BSC TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm D1 7.00 BSC 0.276 BSC LEADFRAME MATERIAL D2 5.50 0.217 APPROVE DOC. NO. E 9.00 BSC 0.354 BSC VERSION 02 E1 7.00 BSC 0.276 BSC CHECK DWG NO. PKGC-065 E2 5.50 0.217 DATE e 0.50 BSC 0.0196 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o

2+2 Channel High Definition Audio Codec 71 Track ID: JATR-1076-21 Rev. 1.3 11.2. QFN-48 Mechanical Dimensions (ALC268Q) MILLIMETER INCH SYMBOL MIN. TYP MAX. MIN. TYP MAX A2 - 0.65 1.00 - 0.026 0.039 A3 - 0.20 0 - 0.008 - D 7.00BSC 0.276BSC D1 6.75BSC 0.266BSC E 7.00BSC 0.276 BSC E1 6.75BSC 0.266 BSC e 0.50BSC 0.020BSC TH 0 o - 12 o 0 o - 12 o chamfer - - 0.60 - - 0.024 TITLE: QFN-48 (7.0x7.0x1.0mm) PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL DOC. NO. APPROVE VERSION DWG NO. CHECK DATE REALTEK SEMICONDUCTOR CORP.

Table 82. Ordering Information Note 1: See page 6 and page 7 for Green package and version identification.