ALC262SRS-GR

ALC262-GR REALTEK | Alldatasheet

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4-CHANNEL DAC and 6-CHANNEL ADC HIGH DEFINITION AUDIO CODEC DATASHEET Rev. 1.7

22 March 2007

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

4-Ch DAC and 6-Ch ADC High Definition Audio Codec ii Track ID: JATR-1076-21 Rev. 1 .7 COPYRIGHT ©2007 Realtek Semiconductor Corp. A ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular pu rpose. Realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC262 Series Audio Codecs. Though every effort has been made to assure that this document is current and accurate, more information may have become available subsequent to the productio n of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2005/05/02 First release. 1.1 2005/06/09 Update section 13 Ordering Information, page 64. Revise analog output port information in section 1 General Description, page 1. 1.2 2005/08/25 Add ordering information note (see section 13 Ordering Information, page 64). 1.3 2005/10/17 Revise Figure 2, page 5. Revise Table 80, page 63. Update section 13 Ordering Information, page 64. 1.4 2005/11/25 Update section 13 Ordering Information, page 64. 1.5 2006/06/22 Release for ALC262 ‘C’ version. Revise section 4 Block Diagram, page 4 Improve DAC/ADC filter characteristics, Table 75, page 59. Support low voltage (1.5V~3.3V) IO for HAD link. Add digital microphone input support (pins 2 and 46), see Figure 4, page 7. Add digital microphone application note (section 11.4 Digital Microphone Implementation, page 65). Update section 13 Ordering Information, page 64. 1.6 2007/01/15 Update section 13 Ordering Information, page 64. 1.7 2007/01/22 Cosmetic changes to Figure 4, page 7.

4-Ch DAC and 6-Ch ADC High Definition Audio Codec iii Track ID: JATR-1076-21 Rev. 1 .7 Table of Contents

4-Ch DAC and 6-Ch ADC High Definition Audio Codec iv Track ID: JATR-1076-21 Rev. 1 .7 9.26. V ERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR

4-Ch DAC and 6-Ch ADC High Definition Audio Codec v Track ID: JATR-1076-21 Rev. 1 .7

Table 28. Parameter – Amplifier Capabilities (V erb ID=F00h, Output Amplifier Parameter ID=12h) ...29

Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 1 Track ID: JATR-1076-21 Rev. 1. 7 1. General Description The ALC262 series are 4-Channel DAC and 6-Cha nnel ADC High Definition Audio Codecs with UAA (Universal Audio Architecture). Featuring two 24-bit stereo DACs and three 20-bit stereo ADCs, they are designed for high performance multimedia desktop and la ptop systems. The ALC262 series incorporates proprietary converter technology to achieve over 100dB Signal-to-Noise ratio playback quality; meeting Windows® Vista Premium requirement s and bringing PC sound quality closer to consumer electronic devices. The ALC262 series provide 4 channels of DAC, s upporting stereo sound playb ack on the rear panel and independent stereo sound output on the front pane l simultaneously (multiple streaming), along with flexible mixing, mute, and fine gain control functions to provide a complete integrated audio solution. The ALC262 series also integrates three stereo ADCs that can support a microphone array with Acoustic Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously, significantly improving sound quality for PC VoIP app lications. With this unique feature (3 stereo ADCs), the ALC262 can provide high-quality audi o using S/PDIF to output analog data, or for multiple-source recording applications. All analog IO are input and output capable and can be re-tasked according to user’s definitions. Headphone amplifiers are also integrated at analog output ports A, B, C, D, E, and F. The ALC262 series supports 16/20/24 S/PDIF input an d output to offer easy connection of PCs to high quality consumer electronic products such as digital decoders and speakers. The ALC262 series supports host/soft audio from th e Intel ICH chipset, and also from any other HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compa tibility, and excellent software utilities like Karaoke mode, environment emulation, software equalizer, HRTF 3D positional audio, and optional Dolby ® audio technology to provide an excelle nt entertainment package and game experience for PC users. Two functions are added in ALC262 C version. The first one is the digital microphone interface is supported. The ALC262 C version supports all main ly digital microphones supplied on current market. With digital microphone implementation, especially the laptop system can ach ieve better voice input quality without noise interference caused by geomet ric PCB layout and radio frequency devices. The other one is ALC262 C version can support scalable I/O voltage (1.5V to 3.3V) on HDA link, which will be a requirement in future chipsets designed for low voltage operation. *Note: ALC262 version/audio software differences are listed in section 13 Ordering Information, page 64.

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 2 Track ID: JATR-1076-21 Rev. 1. 7 2. Features 2.1. Hardware Features „ High-performance DACs with 100dB SNR „ ADCs with 90dB SNR „ Meets Premium performance for Windows Logo Program 3.0 (Vista Requirements) „ Two stereo DACs support 16/20/24-bit PCM format for stereo audio playback on the rear panel, plus 2 channels of independent stereo sound output (multiple streaming) through the Front-Out-Left and Front-Out-Right channels „ Three stereo ADCs support 16/20-bit PCM format for multiple input streaming „ All DACs supports 44.1K/48K/96K/192kHz sample rate „ All ADCs support 44.1K/48K/96K sample rate „ 16/20/24-bit S/PDIF-OUT supports 44.1K/48K/96K/192kHz sample rate „ 16/20/24-bit S/PDIF-IN supports 44.1K/48K/96K/192kHz sample rate „ Up to four channels of microphone input are supported for AEC/BF applications „ Supports MONO line output with independent volume control „ High-quality analog differential CD input „ Supports external PCBEEP input and built-in digital BEEP generator „ Software selectable 2.5V/3.75V VREFOUT „ Two jack detection pins each designed to detect up to 4 jacks „ Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain „ All analog jacks are stereo input and output re-tasking for analog plug & play „ Built-in headphone amplifiers for port-A/D/E/F „ Supports both analog DC volume control and GPI digital volume control (requires driver support) „ 4 GPIOs (General Purpose Input/Output) for customized applications „ Optional EAPD (External Amplifier Power Down) is supported „ Power support: Digital: 3.3V; Analog: 3.3V/5.0V „ Power management and enhanced power saving features „ 48-pin LQFP ‘Green’ package; pin compatible with the ALC260 „ Supports low voltage (1.5V~3.3V) IO for HDA link (ALC262 C version) „ Support stereo digital microphone input (ALC262 C version)

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 3 Track ID: JATR-1076-21 Rev. 1. 7 2.2. Software Features „ Meets Microsoft WLP 3.0 audio requirements „ EAX™ 1.0 & 2.0 compatible „ Direct Sound 3D™ compatible „ A3D™ compatible „ I3DL2 compatible „ HRTF 3D Positional Audio „ Emulation of 26 sound environments to enhance gaming experience „ 10 Software Equalizer Bands „ Voice Cancellation and Key Shifting in Karaoke mode „ Realtek Media Player „ Enhanced Configuration Panel and device sensing wizard to improve user experience „ Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice applications „ Optional audio software technology ‹ ALC262SRS-GR features SRS TruSurround XT ‹ ALC262H-GR features Dolby® Home Theater 3. System Applications „ Multimedia desktop and laptop PCs „ 3D PC games „ Information appliances (IA) „ Voice recognition „ Audio conferencing

Figure 1. Block Diagram – ALC262 A/B Version

Figure 2. Block Diagram – ALC262 C Version

Pin Complex widgets NID=14h~16h, 18h~1Bh are re-tasking IO. Figure 3. Analog Input/Output Unit

Note: C version (next page) supports digital MIC (pin 2, 46) and Scalable I/O Power (pin 9). Figure 4. Pin Assignments The ALC262 series includes the parts listed in section 13 Ordering Information, page 64. in the location marked ‘VV’.

The C version (Figure 5) supports digital MIC (pin 2, 46) and Scalable I/O Power (pin 9). Figure 5. Pin Assignments The ALC262 series includes the parts listed in section 13 Ordering Information, page 64. in the location marked ‘VV’.

Table 1. Digital I/O Pins SPDIFO O 48 S/PDIF output Output has 12mA@75Ω driving capability. I/O 2 General Purpose Input/Output 2. Note: Only the C version supports DMIC-DATA and DMIC-CLK. Table 2. Analog I/O Pins

Table 3. Filter/Reference Table 4. Power/Ground B version: Digital power for core and HDA link. C version: Scalable digital power for HDA link.

1. High Definition Audio Link Protocol

with a 48kHz frame rate. Figure 6 shows the basic concept of the HDA link protocol. Figure 6. HDA Link Protocol

Table 5. Link Signal Definitions BCLK 24.0MHz of bit clock sourced from the HDA controller and connecting to all codecs. controller and connects to all codecs. extend outbound bandwidth, multiple SDOs may be supported. controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported. BCLK. SDI can be driven by the controller to initialize the codec’s ID. HDA controller and connects to all codecs. Table 6. HDA Signal Definitions BCLK Controller Output Global 24.0MHz bit clock. SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal. SDO Controller Output Serial data output from controller. RST# Controller Output Global active low reset signal. Figure 7. Bit Timing

stream data is always carried on SDO0, the second bit on SDO1 and so forth. is always transmitted on SDO0, and copied on SDO1. Figure 11. Striped Stream on Multiple SDOs

Figure 14. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz.

Table 7. Defined Sample Rate and Transmission Rate Table 8. 48kHz Variable Rate of Delivery Timing Table 9. 44.1kHz Variable Rate of Delivery Timing

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 19 Track ID: JATR-1076-21 Rev. 1. 7 44.1kHz 12- =Contiguous 12 frames containing 1 samp le blocks each, followed by one frame with no sample block. 88.2kHz 12 2- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with no sample block. 174.4kHz 12 4- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with no sample block. 8.3. Reset and Initialization There are two types of reset within an HDA link:

• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events: 1. Link Reset 2. Codec Reset 3. Codec changes its power state (For example, hot docking a codec to an HDA system) 8.3.1. Link Reset A link reset may be caused by 3 events: 1. The HDA controller asserts RST# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Re gister (GCR) of the HDA controller 3. Software initiates power management sequences. Figure 15, page 20, shows the ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)

4 BCLK 4 BCLK

Figure 15. Link Reset Timing

o The codec will stop driving the SDI during this turnaround period. pqrs The controller drives SDI to assign a CAD to the codec. t The controller releases the SDI after the CAD has been assigned. Figure 16. Codec Initialization Sequence

controls parameters in the codec. Table 10. 40-Bit Commands in 4-Bit Verb Format Table 11. 40-Bit Commands in 12-Bit Verb Format software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 12. Solicited Response Format Table 13. Unsolicited Response Format an unsolicited response was sent.

changes in widgets are driven by software. Table 14, shows the System Power State Definitions. various power states depending on system configuration. and input converters (ADCs) have no individual power control to supply fine-grained power control. Table 14. System Power State Definitions D0 All power on. Individual DACs and ADCs can be powered up or down as required. reference off (D1 + analog reference off). D3 (Hot) Power still supplied. The codec stops the internal clock. State is maintained. D3 (Cold) All power removed. State lost. Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h Table 16. Powered Down Conditions LOUT DAC powered down Analog block and digital filter are powered down. Headphone Driver powered down All headphone drivers are powered down. VREFOUTx at individual pin complex are still alive.

1. Supported Verbs and Parameters

not supported by the addressed widget, it will respond with 32 bits of ‘0’. detailed information about supported parameters. Table 17. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) 31:16 Vendor ID=10ECh (Realtek’s PCI vendor ID). Note: The Root Node (NID=00h) supports this parameter. Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 31:24 Reserved. Read as 0’s. 15:8 Revision ID. The vendor’s revision number. 00h is for the first silicon version, 01h is for the second version, etc. 7:0 Stepping ID. The vendor’s stepping number within the given Revision ID. Note: The Root Node (NID=00h in the ALC262) supports this parameter.

associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) 31:24 Reserved. Read as 0’s. The starting node number in the sequential widgets. For a root node, the total number of function groups in the root node. For a function group, the total number of widget nodes in the function group. Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) 80h~FFh: Vendor Defined Function. Note: The Audio Function Group (NID=01h) supports this parameter. Table 22. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h) 31:17 Reserved. Read as 0’s.

16 Beep Generator

A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0’s. Note: The Audio Function Group (NID=01h) supports this parameter.

Table 23. Parameter – Audi o Widget Capabilities (Verb ID=F00h, Parameter ID=09h) 31:24 Reserved. Read as 0’s. 19:16 Delay. Samples delayed between the HDA link and widgets. 15:11 Reserved. Read as 0’s. 8 ConnList. Connection List. 7 UnsolCap. Unsolicited Capable. 6 ProcWidget. Processing Widget. 3 AmpParOvr, AMP Param Override. 2 OutAmpPre, Out AMP Present. own parameters to provide supported formats if their ‘Format Override’ bit is set. Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) 31:21 Reserved. Read as 0’s. 20 B32: Indicates whether 32-Bit audio format is supported.

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 27 Track ID: JATR-1076-21 Rev. 1. 7 Codec Response Format Bit Description 19 B24: Indicates whether 24-Bit audio format is supported. 0: Not supported 1: Supported 18 B20: Indicates whether 20-Bit audio format is supported. 0: Not supported 1: Supported 17 B16: Indicates whether 16-Bit audio format is supported. 0: Not supported 1: Supported 16 B8: Indicates whether 8-Bit audio format is supported. 0: Not supported 1: Supported 15:12 Reserved. Read as 0’s. 11 R12: Indicates whether 384kHz (=8*48kHz) rate is supported. 0: Not supported 1: Supported 10 R11: Indicates whether 192kHz (=4*48kHz) rate is supported. 0: Not supported 1: Supported 9 R10: Indicates whether 176.4kHz (=4*44.1kHz) rate is supported. 0: Not supported 1: Supported 8 R9: Indicates whether 96kHz (=2*48kHz) rate is supported. 0: Not supported 1: Supported 7 R8: Indicates whether 88.2kHz (=2*44.1kHz) rate is supported. 0: Not supported 1: Supported 6 R7: Indicates whether 48kHz rate is supported. 0: Not supported 1: Supported 5 R6: Indicates whether 44.1kHz rate is supported. 0: Not supported 1: Supported 4 R5: Indicates whether 32kHz (=2/3*48kHz) rate is supported. 0: Not supported 1: Supported 3 R4: Indicates whether 22.05kHz (=1/2*44.1kHz) rate is supported. 0: Not supported 1: Supported 2 R3: Indicates whether 16kHz (=1/3*48kHz) rate is supported. 0: Not supported 1: Supported 1 R2: Indicates whether 11.025kHz (=1/4*44.1kHz) rate is supported. 0: Not supported 1: Supported 0 R1: Indicates whether 8kHz (=1/ 6*48kHz) rate is supported. 0: Not supported 1: Supported

have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Note: Input converters and output converters support this parameter. The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 26. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch) 31:16 Reserved. Read as 0’s. 15:8 VREF Control Capability. 7 L-R Swap. Indicates the capability of swapping the left and rights. ‘1’ indicates this pin complex has balanced pins. ‘1’ indicates this pin complex supports input. ‘1’ indicates this pin complex supports output. ‘1’ indicates this pin complex has an amplifier to drive a headphone. ‘1’ indicates this pin complex can detect whether there is anything plugged in. ‘1’ indicates whether a software trigger is required for an impedance measurement. ‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type. Note: Only Pin Complex widgets support this parameter.

their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 27. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. Indicates which step is 0dB. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 28. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 6:0 Offset. Indicates which step is 0dB.

Parameters in this node provide audio function widget connection information. Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) input, and there is no Connection Select Control (Not a MUX widget). Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) 1: Power state D3 is supported. 1: Power state D2 is supported. 1: Power state D1 is supported.

0 D0Sup

1: Power state D0 is supported. Table 31. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h) 31:16 Reserved. Read as 0’s.

Table 32. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h) The ALC262 does not support GPIO wake up function. The ALC262 supports GPIO unsolicited response. 29:24 Reserved. Read as 0’s. Two GPIO pins are supported. Table 33. Parameter – Volume Knob Capab ilities (Verb ID=F00h, Parameter ID=13h)

Table 34. Verb – Get Connection Select Control (Verb ID=F01h) 7:0 Connection Index currently set (Default value is 00h). 7:0 Connection Index currently set (Default value is 00h). 7:0 Connection Index currently set (Default value is 00h). 31:0 Not supported (returns 00000000h).

Table 35. Verb – Set Connection Select (Verb ID=701h) Table 36. Verb – Get Connection List Entry (Verb ID=F02h) 31:8 Connection List Entry (N+3), (N+2) and (N+1). 7:0 Connection List Entry (N). 31:8 Connection List Entry (N+3), (N+2) and (N+1). 7:0 Connection List Entry (N). 15:8 Connection List Entry (N+3), (N+2) and (N+1). 7:0 Connection List Entry (N). 31:8 Connection List Entry (N+3), (N+2) and (N+1). 7:0 Connection List Entry (N).

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 34 Track ID: JATR-1076-21 Rev. 1. 7 Codec Response for NID=0Bh (Mixer) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex - LINE2) for N=0~3 Returns 00h for N>3. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex - LINE1) for N=0~3 Returns 00h for N>3. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex - MIC2) for N=0~3 Returns 1Dh (Pin Complex - BEEP) for N=4~7 Returns 00h for N>7 7:0 Connection List Entry (N). Returns 18h (Pin Complex - MIC1) for N=0~3 Returns 1Ch (Pin Complex - CD) for N=4~7 Returns 00h for N>7 Codec Response for NID=0Ch Bit Description 31:24 Connection List Entry (N). Returns 00h 23:16 Connection List Entry (N+2). Returns 00h 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N). Returns 02h (LOUT DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID=0Dh Bit Description 31:24 Connection List Entry (N). Returns 00h 23:16 Connection List Entry (N+2). Returns 00h 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N). Returns 03h (HP-OUT DAC) for N=0~3 Returns 00h for N>3

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 35 Track ID: JATR-1076-21 Rev. 1. 7 Codec Response for NID=0Eh) Bit Description 31:24 Connection List Entry (N). Returns 00h 23:16 Connection List Entry (N+2). Returns 00h 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N). Returns 02h (LINE-OUT DAC) for N=0~3 Returns 00h for N>3 Codec Response for NID =14h~15h, 18h~1Bh (PORT-A ~ PORT-F) Bit Description 31:24 Connection List Entry (N+3). Returns 00h 23:16 Connection List Entry (N+2). Returns 00h 15:8 Connection List Entry (N+1). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3 Returns 00h for N>7 7:0 Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3 Returns 00h for N>7 Codec Response for NID=16h (Pin Widget: MONO-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2) and (N+1). Returns 000000h 7:0 Connection List Entry (N). Returns 0Eh for N=0~3 Returns 00h for N>3 Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT) Bit Description 31:16 Connection List Entry (N+3) and (N+2). Returns 0000h 15:8 Connection List Entry (N+1). Returns 00h for N>3 7:0 Connection List Entry (N). Returns 06h (S/PDIF-OUT converter) for N=0~3 Returns 00h for N>3

31:24 Connection List Entry (N+3). 23:16 Connection List Entry (N+2). 15:8 Connection List Entry (N+1). 7:0 Connection List Entry (N). 31:0 Not supported (returns 00000000h). Table 37. Verb – Get Processing State (Verb ID=F03h) 31:0 Not supported (returns 00000000h). Table 38. Verb – Set Processing State (Verb ID=703h)

Table 39. Verb – Get Coefficient Index (Verb ID=Dh) 31:16 Reserved. Read as 0’s. 31:0 Not supported (returns 00000000h). Table 40. Verb – Set Coefficient Index (Verb ID=5h) Table 41. Verb – Get Processing Coefficient (Verb ID=Ch) 31:16 Reserved. Read as 0’s. 31:0 Not supported (returns 00000000h).

Table 42. Verb – Set Processing Coefficient (Verb ID=4h) This verb is used to get gain/attenuation settings from each widget. Table 43. Verb – Get Amplifier Gain (Verb ID=Bh) 3:0 Index[3:0] for Input Source.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute, 1: Mute

volume from –16.5B~+30dB in 1.5dB steps.

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 39 Track ID: JATR-1076-21 Rev. 1. 7 Codec Response for NID=0Bh (MIXER Sum Widget) Bit Description 31:8 0’s.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplif ier Mute, 0: Unmute 1: Mute (Default for all

Index). Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifie r Gain [6:0]. 7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute) Codec Response for NID=0Ch~0Eh (Sum Widgets) Bit Description 31:8 0’s. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –46.5dB~0dB in 1.5dB steps. Codec Response for NID=14h, 15h, 18h~1Bh (Pin Complex: LINE-OUT/HP-OUT/MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0’s. 7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute, 0:Unmute, 1:Mute (Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain) Codec Response for NID=22h, 23h, 24h (Sum Widgets) – In C version, NID=22h is a selector will not support this verb. Bit Description 31:8 0’s. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain) Codec Response to Other NID Bit Description 31:0 Not supported (returns 00000000h).

This verb is used to set amplifier gain/attenuation in each widget. Table 44. Verb – Set Amplifier Gain (Verb ID=3h) 1 indicates output amplifier gain will be set. 1 indicates input amplifier gain will be set. 1 indicates left amplifier gain will be set. 1 indicates right amplifier gain will be set. 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets). A 7-bit step value specifying the amplifier gain. Table 45. Verb – Get Converter Format (Verb ID=Ah) Codec Response for NID=02h, 03h, 06h (Output Converters: LINE-OUT DAC, HP-OUT DAC, S/PDIF-OUT). 13:11 Sample Base Rate Multiple (MULT).

Codec Response for NID=02h, 03h, 06h (Output Converters: LINE-OUT DAC, HP-OUT DAC, S/PDIF-OUT). 10:8 Sample Base Rate Divisor (DIV). The ALC262 does not support Divisor. Always read as 000b. 31:0 Not supported (returns 00000000h). Table 46. Verb – Set Converter Format (Verb ID=2h) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV).

Table 47. Verb – Get Power State (Verb ID=F05h) 5:4 PS-Act. Actual Power State [1:0]. (NID=01h), PS-Act is always equal to PS-Set. 1:0 PS-Set. Set Power State [1:0]. PS-Set controls the current power setting of the referenced node. 31:0 Not supported (returns 00000000h).

Table 48. Verb – Set Power State (Verb ID=705h) 5:4 PS-Act. Actual Power State [1:0]. PS-Act indicates the actual power state of the referenced node. 1:0 PS-Set. Set Power State [1:0]. Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h) Codec Response for NID=02h, 03h, 06h (Output Converters: LINE-OUT DAC, HP-OUT DAC, S/PDIF-OUT). The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. for its left and right channel. 31:0 Not supported (returns 00000000h).

Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. for its left and right channel. (NID=07h~0Ah). Other widgets will ignore this verb. Table 50. Verb – Get Pin Widget Control (Verb ID=F07h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit). 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit). 2:0 VrefEn (Vrefout Enable Control). 31:0 Not supported (returns 00000000h).

Table 51. Verb – Set Pin Widget Control (Verb ID=707h) 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit). 2:0 VrefEn (Vrefout Enable Control).

unsolicited response to inform software of a real-time event. Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h) 7 Unsolicited Response is Enabled. 3:0 Assigned Tag for Unsolicited Response. The tag[3:0] is assigned by software to determine which widget generates unsolicited responses. 31:0 Not supported (returns 00000000h). Enable a widget to generate an unsolicited response. Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h) 7 Enable Unsolicited Response. 3:0 Tag for Unsolicited Response.

Returns the Presence Detect status and the impedance of a device attached to the pin. Table 54. Verb – Get Pin Sense (Verb ID=F09h) 0x7FFFFFFF or 0xFFFFFFFF: Valid sense is not available or is busy. 31:0 Not supported (returns 00000000h). Table 55. Verb – Execute Pin Sense (Verb ID=709h) 0 Right (Ring) Channel Select.

Read the 32-bit sticky register for each Pin Widget configured by software. Table 56. Verb – Get Configuration Default (Verb ID=F1Ch) 31:0 32-bit configuration info rmation for each pin widget. 1Eh~1Fh such as placement and expected default device. Note: Supported by Pin Widget NID=14h~16h, 18h~1Fh. Other widgets will ignore this verb.

Table 58. Verb – Get BEEP Generator (Verb ID=F0Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input. Table 59. Verb – Set BEEP Generator (Verb ID=70Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 60. Verb – Get GPIO Data (Verb ID=F15h) The value written (output) or sensed (input) on the corresponding pin if it is enabled. Table 61. Verb – Set GPIO Data (Verb ID=715h) The value written determines the value driven on a pin that is configured as an output pin.

Table 62. Verb – Get GPIO Enable Mask (Verb ID=F16h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 64. Verb – Get GPIO Direction (Verb ID=F17h) 3:0 GPIO[3:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 65. Verb – Set GPIO Direction (Verb ID=717h) 3:0 GPIO[3:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) 3:0 GPIO[3:0] Unsolicited Enable mask. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) 3:0 GPIO[3:0] Unsolicited Enable Mask. Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled.

Table 68. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets in the ALC262 to return to their power on default state. Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh) NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0]). 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer format). 5 /AUDIO (Non-Audio Data type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame).

NID=0Ah (S/PDIF-IN) Response to ‘Get verb (F0Dh)’. 31:16 Reserved. Read as 0’s. 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer format). 5 /AUDIO (Non-Audio Data type). 1 In‘V’alid. V bit in sub-frame of S/PDIF-IN. Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 56 Track ID: JATR-1076-21 Rev. 1. 7 ‘Payload’ in Set Control 1 for NID=06h (S/PDIF-OUT) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7 LEVEL (Generation Level). 6 PRO (Professional or Consumer format). 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type). 0: PCM data 1: AC3 or other digital non-audio data 4 COPY (Copyright). 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis). 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 0 Digital Enable. DigEn. 0: OFF 1: ON ‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7 Reserved. Read as 0’s. 6:0 CC[6:0] (Category Code). ‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7:1 Reserved. 0 Digital Enable. DigEn. 0: OFF 1: ON ‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7:0 Reserved. Read as 0’s. Note: Other widgets will ignore this verb.

Table 71. Get/Set Volume Knob Widget (NID=21h) (Verb ID=F0Fh/70Fh) 0: The volume generated by an external HW volume control will be sent by unsolicited response. 0: The volume generated by an external HW volume control will be sent by unsolicited response. Note: Other nodes will ignore this verb. Table 72. Get/Set Subsystem ID [31:0] (Verb ID=F20h / 723h~720h to Set Bit[31:0]) 31:16 Subsystem ID[23:8]. (Default=10ECh). 15:8 Subsystem ID[7:0]. (Default=02h). 7:0 Assembly ID[7:0]. (Default=62h).

1. Electrical Characteristics

Table 73. Absolute Maximum Ratings Note*: The digital link power DVDD-IO must be lower than the digital core power DVDD. different AVDD should contact Realtek technical support representatives for special testing support. DVDD-IO=3.3V±5%, Tambient=25°C, with 50pF external load. Table 74. Threshold Voltage

Table 75. Digital Filter Characteristics DVDD=3.3V, Tambient=25°C, with 75Ω external load. Table 76. S/PDIF Input/Output Characteristics

Table 77. Link Reset and Initialization Timing

4 BCLK 4 BCLK >= 4 BCLK

Figure 17. Link Reset and Initialization Timing

Table 78. Link Timing Parameters at the Codec Figure 18. Link Signals Timing

Table 79. S/PDIF Output and Input Timing Figure 19. Output and Input Timing The ALC262 does not support codec test mode or Automatic Test Equipment (ATE) mode.

• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz, 0dB attenuation

Table 80. Analog Performance

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 66 Track ID: JATR-1076-21 Rev. 1. 7 12. Mechanical Dimensions L See the Mechanical Dimensions notes on the next page.

4-Ch DAC and 6-Ch ADC High Definition Audio Codec 67 Track ID: JATR-1076-21 Rev. 1. 7 12.1. Mechanical Dimensions Notes MILLIMETER INCH SYMBOL MIN. TYP MAX. MIN. TYP MAX A 1.60 0.063 A1 0.05 0.15 0.002 0.006 c 0.09 0.20 0.004 0.008 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 E 9.00 BSC 0.354 BSC E1 7.00BSC 0.276 BSC E2 5.50 0.217 e 0.50 BSC 0.0196 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o L1 1.00 0.0393 TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm LEADFRAME MATERIAL DOC. NO. APPROVE VERSION 02 DWG NO. PKGC-065 CHECK DATE REALTEK SEMICONDUCTOR CORP.

Table 81. Ordering Information Note 1: See page 7 for Green package and version identification. sales representatives or agents.