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2 CHANNEL HIGH DEFINITION AUDIO CODEC

Rev. 1.4

15 August 2005

Track ID: JATR-1076-21 ALC260/ALC260D Series

ALC260(D) Datasheet 2 Channel High Definition Audio Codec ii Track ID: JATR-1076-21 Rev. 1.4 COPYRIGHT ©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited t o, the particular pu rpose. Realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and soft ware engineer’s general information on the Realtek ALC260(D) audio codec chip. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the productio n of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2004/07/20 Pre liminary release. 1.1 2004/09/29 First official release. Add HDA 1.0 compliant part number (Table 83, page 72). 1.2 2004/11/08 Updated to reflect modifications in ALC260, ALC260-VD, ALC260-VD-LF, ALC260-VE, ALC260-VE-LF. 1. Power-Off CD mode supported only in ALC260 & ALC260-LF. 2. Parameter ‘subsystem ID’ is read as 0s (Table 19, page 19). 3. Verb ‘subsystem verb’ is supported (Table 73, page 62, and Table 74, page 63). 1.3 2005/03/03 Add lead (Pb)-free and version package identification information on page 5 and in Table 83, on page 72. Add new versions with Dolby® Digital Live (see Table 83, page 72). 1.4 2005/08/15 Update section 9.1.1 Absolute Maximum Ratings, page 64 A VDD support range. Add a note to section 12 Ordering Information, page 72.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec iii Track ID: JATR-1076-21 Rev. 1.4 Table of Contents

ALC260(D) Datasheet 2 Channel High Definition Audio Codec iv Track ID: JATR-1076-21 Rev. 1.4 8.41. VERB – SET SUBSYSTEM ID [31:0]

TABLE 74. VERB – SET SUBSYSTEM ID [31:0]

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 1 Track ID: JATR-1076-21 Rev. 1.4 1. General Description The ALC260 and ALC260D* 2-Channel High Definition Audio (HDA) Codecs with UAA (Universal Audio Architecture), featuring a 24-bit two-channel DAC and two stereo 20-bit ADCs, are designed for commercial Deskt op and Notebook PC systems. The codecs incorporate proprietary converter technology to achieve 95dB sound quality; easily meeting PC2001 requirements and also bringing PC s ound quality closer to consumer electronic devices. The ALC260(D) provides 2 output channels, along with flexible mixing, mute, and fine gain control functions to provide a complete integrated audio solution for PCs. The DAC (with a highest sampling frequency of 192kHz) was previously only implemented in high-end consumer electronics, but is now achieve d by PCs equipped with the ALC260(D). The ALC260(D) provides high-quality audio usi ng S/PDIF to output analog data, or for multiple-source recording applications. Realtek’s proprietary impedance sensing and jack detect tec hniques allow device loads on inputs and outputs to be auto-detected. All analog IO are input and output capable, headphone amplifiers are also integrated at each analog output. All analog IOs can be re-tasked according to user’s definitions, or automatically switc hed depending on the connected device type (Universal Audio Jack®). The ALC260(D) supports 32-bit S/PDIF input and output functions and a sampling rate of up to 96kHz, offering easy connection of PCs to high-quality consumer electronic products such as AC-3 decoders/speakers, and mini disk devices. The ALC260(D) supports host/soft audio from the Intel ICH6 chipset, and also from any other HDA compatible audio controller. With power management setting, Realtek’s unique microphone application (AEC/Beam Forming/Noise Suppression), optional Dolby® Digital Live, and reliable driver support, the AL C260(D) is the ideal choice for Commercial Desktop and Notebook PC users. Note: ‘D’ directly after ALC260 indicates Dolby® Digital Live (software feature). See Table 83, page 72.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 2 Track ID: JATR-1076-21 Rev. 1.4 2. Features 2.1. Hardware Features „ Single-chip multi-bit Sigma-Delta converters with high S/N ratio „ 1 stereo DAC supports 16/20/24-bit PCM format with 44.1/48/96/192kHz sample rate „ 2 stereo ADCs support 16/20-bit PCM format with 44.1/48/96kHz sample rate „ Applicable for 2-Channel 192kHz DVD-Audio solutions „ LINE-OUT, HP-OUT, LINE1, LINE2, MIC1, and MIC2 are stereo input and output re-tasking „ MONO line level output to subwoofer speaker for 2.1 channel applications „ High-quality differential CD analog input „ External PCBEEP input is applicable, and internal BEEP generator is integrated „ Power-Off CD mode supported (Only in ALC260 & ALC260-LF) „ Power management and enhanced power saving features „ Power support: Digital: 3.3V; Analog: 3.8V/5.0V „ Selectable 2.5V/3.75V VREFOUT „ Two jack detection pins (each designed to detect 4 jacks) „ Supports 44.1/48/96/192kHz S/PDIF output „ Supports 44.1/48/96kHz S/PDIF input „ 48-pin LQFP packages (lead (Pb)-free packages also available) „ Supports external volume knob control „ External PCBEEP Pass-Through when link is in RESET state (Not supported in the ALC260(D)-VE and ALC260(D)-VE-LF) „ Reserve analog mixer architecture is backwards compatible with AC'97 „ –64dB ~ +30dB with 1dB mixer gain resolution for finer volume control „ Impedance sensing capability for each re-tasking jack „ Built-in headphone amplifier for each re-tasking jack „ Supports external volume knob control „ Supports GPIO (General Purpose Input/Output) for customized applications

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 3 Track ID: JATR-1076-21 Rev. 1.4 2.2. Software Features „ Meets Microsoft WHQL/WLP 2.0 audio requirements „ EAX™ 1.0 & 2.0 compatible „ Direct Sound 3D™ compatible „ A3D™ compatible „ I3DL2 compatible „ HRTF 3D Positional Audio „ Emulation of 26 sound environments to enhance gaming experience „ 10-band Software Equalizer „ Voice Cancellation and Key Shifting in Karaoke mode „ Realtek Media Player „ Enhanced Configuration Panel and device sensing wizard to improve user experience „ Content Copy Protection for S/PDIF interface „ Power Management setting „ Microphone Acoustic Echo Cancellation (AEC) and Beam Forming (BF) technology for voice application „ Mono/Stereo Microphone Noise Suppression „ ALC260D, ALC260D-LF, ALC260D-VE, and ALC260D-VE-LF feature Dolby® Digital Live 3. System Applications „ Multimedia PCs „ 3D PC Games „ Information Appliances (IA) „ Voice Recognition „ Audio Conferencing

24 LINE1-R

Figure 3. Pin Assignments Note: JDREF is used to calibrate reference current for jack detection. shown in the location marked ‘V’.

Table 1. Digital I/O Pins SPDIFO O 48 S/PDIF Output TTL output has 12 mA@75Ω driving capability. Table 2. Analog I/O Pins

MONO-OUT O 37 MONO output Analog mono output is summation of (L+R)/2. Table 3. Filter/Reference Table 4. Power/Ground

  1. High Definition Audio Link Protocol

a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol. Figure 4. HDA Link Protocol

Table 5. Link Signal Definitions BCLK 24.0MHz bit-clock sourced from the HDA controller and connecting to all codecs. controller and connects to all codecs. extend outbound bandwidth, multiple SDOs may be supported. BCLK. SDI can be driven by the controller to initialize the codec’s ID. controller and connects to all codecs. Table 6. HDA Signal Definitions BCLK Controller Output Global 24.0MHz bit clock. SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal. SDO Controller Output Serial data output from controller. RST# Controller Output Global active low reset signal. Figure 5. Bit Timing

rate, independent of any other stream. based on multiples or sub-multiples of one of the two base rates. of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid frequency drift. sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery rate. interleave an empty frame between non-empty frames (Table 9, page 14). Table 7. Defined Sample Rate and Transmission Rate Table 8. 48kHz Variable Rate of Delivery Timing

Table 9. 44.1kHz Variable Rate of Delivery Timing followed by one frame with no sample block. followed by one frame with no sample block. followed by one frame with no sample block.

  • Link Reset: Generated by assertion of the RST# signal; all codecs return to their power-on state
  • Codec Reset: Generated by software; directs a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events: 1. Link Reset 2. Codec Reset 3. Codec changes its power state (e.g., hot docking a codec to an HDA system)
  1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
  2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Re gister (GCR) of the HDA
  3. Software initiates power management sequences. Figure 11, page 15, shows the ‘Link Reset’ timing

4 BCLK 4 BCLK

Figure 11. Link Reset Timing

Figure 12. Codec Initialization Sequence

stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and controls parameters in the codec. Table 10. 40-Bit Commands in 4-Bit Verb Format Table 11. 40-Bit Commands in 12-Bit Verb Format software, opaque to the controller. Bit [31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 12. Solicited Response Format Table 13. Unsolicited Response Format indicate that an unsolicited response was sent.

changes in widgets are driven by software. Table 14 shows the System Power State Definitions. Table 14. System Power State Definitions D0 All power on. Individual DACs and ADCs can be powered up or down as required. reference off (D1 + analog reference off). D3 (Hot) Power still supplied. The codec stops the internal clock. State is maintained. D3 (Cold) All power removed. State lost. Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h Table 16. Powered Down Conditions are maintained if DVDD is supplied. LINE ADC powered down Analog block and digital filter are powered down. Headphone Driver powered down All headphone drivers are powered down. VREFOUTx at individual pin complexes are still alive.

  1. Supported Verbs and Parameters

is not supported by the addressed widget, it will respond with 32 bits of ‘0’. Refer to Figure 1, page 4, to get the NID (Node ID) assigned for each widget. The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA codec. to get detailed information about supported parameters. Table 17. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) 31:16 Vendor ID=10ECh (Realtek’s PCI vendor ID). Table 19. Parameter – Subsystem ID (Verb ID=F00h, Parameter ID=01h) 31:16 The SubSystem ID is used to identify the function group. SubSystem ID=0260h for the ALC260 and the ALC260-LF. SubSystem ID=0000h for other versions.

Table 20. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 31:24 Reserved. Read as 0’s. 23:20 MajRev. The major version number (in decimal) of the HDA Specification. 19:16 MinRev. The minor version number (in decimal) of the HDA Specification. 15:8 Revision ID. The vendor’s revision number. 00h is for the first silicon version, 01h is for the second version, etc. 7:0 Stepping ID. The vendor’s stepping number within the given Revision ID. associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 21. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) 31:24 Reserved. Read as 0’s. The starting node number in the sequential widgets. For a root node, the total number of function groups in the root node. For a function group, the total number of widget nodes in the function group.

Table 22. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) Table 23. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) 31:17 Reserved. Read as 0’s. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0’s.

Table 24. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) 31:24 Reserved. Read as 0’s. 19:16 Delay. Samples delayed between the HDA link and widgets. 15:11 Reserved. Read as 0’s. 8 ConnList. Connection List. DACs are directly connected to the HDA link. No connection list entry need be queried for DACs. 7 UnsolCap. Unsolicited Capable. The S/PDIF-IN converter, Pin Complexes, and DCVOL will generate unsolicited responses. 6 ProcWidget. Processing Widget. Only a Realtek defined widget has processing control. format (parameter ID=0Ah) must be queried. 3 AmpParOvr. AMP Param Override. 2 OutAmpPre. Out AMP Present. Supports amplifiers (Gain Control) in individual output pin complexes. Supports amplifiers (Gain Control) in individual ADCs and Mixer widgets.

supported formats if their ‘Format Override’ bit is set. Table 25. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) 31:21 Reserved. Read as 0’s. 20 B32. 32-bit audio format support. 19 B24. 24-bit audio format support. All DACs and S/PDIF-IN/OUT support 24-bit format. 18 B20. 20-bit audio format support. All DACs, ADCs, and S/PDIF-IN/OUT support 20-bit format. 17 B16. 16-bit audio format support. All DACs, ADCs, and S/PDIF-IN/OUT support 16-bit format. 16 B8. 8-bit audio format support. 15:12 Reserved. Read as 0’s. 11 R12. 384kHz (=8*48kHz) rate support. 10 R11. 192kHz (=4*48kHz) rate support. DAC and S/PDIF-OUT converter supports 192kHz rate. 8 R9. 96kHz (=2*48kHz) rate support. All DACs except Surr-Back DAC, ADCs, and S/PDIF-IN/OUT support 96kHz rate. 7 R8. 88.2kHz (=2*44.1kHz) rate support.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 24 Track ID: JATR-1076-21 Rev. 1.4 Codec Response Format Bit Description 6 R7. 48kHz rate support. 0: Not supported 1: Supported All DACs, ADCs, and S/PDIF-IN/OUT support 48kHz rate. 5 R6. 44.1kHz rate support. 0: Not supported 1: Supported All DACs, ADCs, and S/PDIF-IN/OUT support 48kHz rate. 4 R5. 32kHz (=2/3*48kHz) rate support. 0: Not supported 1: Supported 3 R4. 22.05kHz (=1/2*44.1kHz) rate support. 0: Not supported 1: Supported 2 R3. 16kHz (=1/3*48kHz) rate support. 0: Not supported 1: Supported 1 R2. 11.025kHz (=1/4*44.1kHz) rate support. 0: Not supported 1: Supported 0 R1. 8kHz (=1/6*48kHz) rate support. 0: Not supported 1: Supported

have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 26. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 27. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) 31:16 Reserved. Read as 0’s. 15:8 VREF Control Capability. 7 L-R Swap. Indicates the capability of swapping the left and rights. Not supported. This bit is read as 0. ‘1’ indicates this pin complex has balanced pins. ‘1’ indicates this pin complex supports input. ‘1’ indicates this pin complex supports output. ‘1’ indicates this pin complex has an amplifier to drive a headphone.

‘1’ indicates this pin complex can detect whether there is anything plugged in. Uses dedicated Jack-Detect pins to detect when a jack is plugged in. ‘1’ indicates whether a software trigger is required for an impedance measurement. ‘1’ indicates this pin complex can perform analog sensing on the attached device to determine its type. own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amp Parameter ID=0Dh) Indicates the size of each step in the gain range. Permanently set to ‘3’ (indicates a step of 1dB). Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. Indicates which step is 0dB.

own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 29. Parameter – Amplifier Capabilities Indicates the size of each step in the gain range. Permanently set to ‘3’ (indicates a step of 1dB). Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 6:0 Offset. Indicates which step is 0dB. Parameters in this node provide audio function widget connection information. Table 30. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) input, and there is no Connection Select Control (Not a MUX widget).

Table 31. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) 1: Power state D3 is supported. 1: Power state D2 is supported. 1: Power state D1 is supported. 1: Power state D0 is supported. Table 32. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) 31:16 Reserved. Read as 0’s. 15:8 NumCoeff. Number of Coefficient.

Table 33. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) GPIO wake up function not supported. GPIO unsolicited response not supported. 29:24 Reserved. Read as 0’s. 7:0 NumGPIOs=04h for LQFP-48. A total of 4 GPIO pins are supported. Table 34. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) The number of steps in the range of the V olume Control Knob.

Table 35. Verb – Get Connection Select Control (Verb ID=F01h) 7:0 Connection Index currently Set (Default value is 00h). 7:0 Connection Index currently Set (Default value is 02h). 7:0 Connection Index currently Set (Default value is 00h).

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 31 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=0Ch (MIC2 Selector) Bit Description 31:8 0’s. 7:0 Connection Index currently Set (Default value is 00h). 00h: LOUT1 Sum Widget (NID=08h) 01h: LOUT2 Sum Widget (NID=09h) Other: Reserved Codec Response for NID=0Dh (LINE1 Selector) Bit Description 31:8 0’s. 7:0 Connection Index currently Set (Default value is 00h). 00h: LOUT1 Sum Widget (NID=08h) 01h: LOUT2 Sum Widget (NID=09h) Other: Reserved Codec Response for NID=0Eh (LINE2 Selector) Bit Description 31:8 0’s. 7:0 Connection Index currently Set (Default value is 00h). 00h: LOUT1 Sum Widget (NID=08h) 01h: LOUT2 Sum Widget (NID=09h) Other: Reserved Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h).

Table 36. Verb – Set Connection Select (Verb ID=701h) Table 37. Verb – Get Connection List Entry (Verb ID=F02h) 31:24 Connection List Entry (N+3). Return 15h (=27, Pin Complex - LINE2) for N=0~3. 23:16 Connection List Entry (N+2). Return 14h (Pin Complex - LINE1) for N=0~3. Return 10h (Pin Complex-HP-OUT) for N=4~7. 15:8 Connection List Entry (N+1). Return 13h (Pin Complex-MIC2) for N=0~3. Return 0Fh (Pin Complex-LINE-OUT) for N=4~7. 7:0 Connection List Entry (N). Return 12h (Pin Complex-MIC1) for N=0~3. Return 16h (Pin Complex-CD) for N=4~7.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 33 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=05h (MIX ADC) Bit Description 31:24 Connection List Entry (N+3). Return 15h (=27, Pin Complex - LINE2) for N=0~3. Return 10h (Pin Complex-HP-OUT) for N=4~7. Return 00h for n>7. 23:16 Connection List Entry (N+2). Return 14h (Pin Complex - LINE1) for N=0~3. Return 0Fh (Pin Complex-LINE-OUT) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 13h (Pin Complex-MIC2) for N=0~3. Return 07h (Sum Widget-Mixer) for N=4~7. Return 00h for N>7. 7:0 Connection List Entry (N). Return 12h (Pin Complex-MIC1) for N=0~3. Return 16h (Pin Complex-CD) for N=4~7. Return 00h for N>7. Codec Response for NID=07h (Mixer) Bit Description 31:24 Connection List Entry (N+3). Return 15h (Pin Complex - LINE2) for N=0~3. Return 10h (Pin Complex-HP-OUT) for N=4~7. Return 00h for N>7. 23:16 Connection List Entry (N+2). Return 14h (Pin Complex - LINE1) for N=0~3. Return 0Fh (Pin Complex - LINE-OUT) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 13h (Pin Complex - MIC2) for N=0~3. Return 17h (Pin Complex - PCBEEP) for N=4~7. Return 00h for N>7. 7:0 Connection List Entry (N). Return 12h (Pin Complex - MIC1) for N=0~3. Return 16h (Pin Complex - CD) for N=4~7. Return 00h for N>7.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 34 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=08h (LOUT1 Sum) Bit Description 31:24 Connection List Entry (N). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 07h (Mixer) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 02h (DAC) for N=0~3. Return 00h for N>3. Codec Response for NID=09h (LOUT2 Sum) Bit Description 31:24 Connection List Entry (N). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 07h (Mixer) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 02h (DAC) for N=0~3. Return 00h for N>3. Codec Response for NID=0Ah (MONO Sum) Bit Description 31:24 Connection List Entry (N). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 07h (Mixer) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 02h (DAC) for N=0~3. Return 00h for N>3.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 35 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=0Bh (MIC1 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=0Ch (MIC2 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=0Dh (LINE1 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=0Eh (LINE2 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 36 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=0Eh (LINE2 Sel) Bit Description 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=0Fh (Pin Widget: LINE-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=10h (Pin Widget: HP-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=11h (Pin Widget: MONO-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Ah (MONO Sum Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=12h (Pin Widget: MIC1) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Bh (MIC1 Select Widget) for N=0~3. Return 00h for N>3.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 37 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=13h (Pin Widget: MIC2) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Ch (MIC2 Select Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=14h (Pin Widget: LINE1) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Dh (LINE1 Select Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=15h (Pin Widget: LINE2) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Eh (LINE2 Select Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=18h (Pin Widget: S/PDIF-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 03h (NID=03h, S/PDIF-OUT converter) for N=0~3. Return 00h for N>3. Codec Response for NID=18h (Pin Widget: S/PDIF-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 19h (NID=19h, S/PDIF-IN Pin Widget) for N=0~3. Return 00h for N>3. Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h). Note: Long Form list entry not supported. The Short Form bit of the Connection List Length parameter is always ‘0’.

Table 38. Verb – Get Coefficient Index (Verb ID=Dh) 31:16 Reserved. Read as 0’s. 31:0 Not supported (returns 00000000h). Table 39. Verb – Set Coefficient Index (Verb ID=5h)

Table 40. Verb – Get Processing Coefficient (Verb ID=Ch) 31:16 Reserved. Read as 0’s. 15:0 Processing Coefficient. 31:0 Not supported (returns 00000000h). Table 41. Verb – Set Processing Coefficient (Verb ID=4h)

This verb is used to get gain/attenuation settings from each widget. Table 42. Verb – Get Amplifier Gain (Verb ID=Bh) This bit should be ignored for output amplifier and MONO widget. 3:0 Index[3:0] for Input Source. Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.

7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute, 1: Mute

Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). The Index bits in ‘Get/Set Amplifier gain’ verb for MIC ADC and MIX ADC should be ignored. volume from 0B~+35dB in 1dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute). 7 Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute, 0: Unmute 1: Mute (Default for all Index). Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). volume from –35dB~+30dB in 1dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 41 Track ID: JATR-1076-21 Rev. 1.4 Codec Response for NID=08h~0Ah (Sum Widget: LOUT1, LOUT2, MONO Sum) Bit Description 31:8 0’s. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the volume from –64dB~0dB in 1dB steps. The Index bits in ‘Get/Set Amplifier gain’ for output amplifiers of LOUT1, LOUT2, and MONO Sum should be ignored. Codec Response for NID=0Fh, 10h, 12h~15h (Pin Complex: LINE-OUT/HP-OUT/MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0’s. 7 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute, 0: Unmute, 1: Mute (NID=0Fh~15h,Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0s. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). Codec Response for NID =11h (Pin Complex: MONO-OUT) Bit Description 31:8 0’s. 7 ‘Get Amplifier Gain’. [15]=0: Read as 0. ‘Get Amplifier Gain’. [15]=1 & ‘Get Amplifier Gain’.[13]=0: Read as 0. ‘Get Amplifier Gain’. [15]=1 & ‘Get Amplifier Gain’.[13]=1: Output Amplifier Mute: 0: Unmute 1: Mute The Index bits in ‘Get/Set Amplifier gain’ verb should be ignored. 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0s. Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). Codec Response to Other NID Bit Description 31:0 Not supported (returns 00000000h).

This verb is used to set amplifier gain/attenuation in each widget. Table 43. Verb – Set Amplifier Gain (Verb ID=3h) ‘1’ indicates output amplifier gain will be set. ‘1’ indicates input amplifier gain will be set. ‘1’ indicates left amplifier gain will be set.

12 Set Right Amp

‘1’ indicates right amplifier gain will be set. 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets). A 7-bit step value specifying the amplifier gain.

Table 44. Verb – Get Converter Format (Verb ID=Ah) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV). Not supported. Always read as 000b. 31:0 Not supported (returns 00000000h).

Table 45. Verb – Set Converter Format (Verb ID=2h) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV). Table 46. Verb – Get Power State (Verb ID=F05h) 5:4 PS-Act. Actual Power State [1:0]. (NID=01h), PS-Act is always equal to PS-Set.

1:0 PS-Set, Set Power State [1:0]. PS-Set controls the current power setting of the referenced node. 31:0 Not supported (returns 00000000h). Table 47. Verb – Set Power State (Verb ID=705h) 5:4 PS-Act. Actual Power State [1:0]. PS-Act indicates the actual power state of the referenced node. 1:0 PS-Set, Set Power State [1:0].

Table 48. Verb – Get Converter Stream, Channel (Verb ID=F06h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 31:0 Not supported (returns 00000000h). Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.

Table 50. Verb – Get Pin Widget Control (Verb ID=F07h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit). 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit). 2:0 VrefEn (Vrefout Enable Control). 31:0 Not supported (returns 00000000h).

Table 51. Verb – Set Pin Widget Control (Verb ID=707h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit). 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit). 2:0 VrefEn (Vrefout Enable Control).

unsolicited response to inform software of a real-time event. Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h) 7 Unsolicited Response is Enabled. 5:0 Assigned Tag for Unsolicited Response. The tag [5:0] is assigned by software to determine which widget generates unsolicited responses. 31:0 Not supported (returns 00000000h).

Enables a widget to generate an unsolicited response. Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h) 7 Enable Unsolicited Response. 5:0 Tag for Unsolicited Response. Returns the Presence Detect status and the impedance of a device attached to the pin. Table 54. Verb – Get Pin Sense (Verb ID=F09h) 0x7FFFFFFF or 0xFFFFFFFF: Valid sense is not available or busy. 31:0 Not supported (returns 00000000h).

Table 55. Verb – Execute Pin Sense (Verb ID=709h) 0 Right (Ring) Channel Select. Reads the 32-bit sticky register for each Pin Widget configured by software. Table 56. Verb – Get Configuration Default (Verb ID=F1Ch) 31:0 32-bit configuration info rmation for each pin widget.

such as placement and expected default device. Table 57. Verb – Set Configuration Default Bytes 0 ~ 3 Note: Supported by Pin Widget NID=14h~1Bh, 1Eh and 1Fh. Other widgets will ignore this verb. Table 58. Verb – Get BEEP Generator (Verb ID= F0Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.

Table 59. Verb – Set BEEP Generator (Verb ID= 70Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 60. Verb – Get GPIO Data (Verb ID= F15h) 7:4 GPIO [7:4] (not supported). The value written (output) or sensed (input) on the corresponding pin if it is enabled.

Table 61. Verb – Set GPIO Data (Verb ID= 715h) 7:4 GPIO [7:4] (not supported). The value written determines the value driven on a pin that is configured as an output pin. Table 62. Verb – Get GPIO Enable Mask (Verb ID= F16h)

Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h) 7:4 GPIO [7:4] Enable Mask (not supported). Table 64. Verb – Get GPIO Direction (Verb ID=F17h) 7:4 GPIO [7:4] Direction Control (not supported). 3:0 GPIO [3:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Table 65. Verb – Set GPIO Direction (Verb ID=717h) 7:4 GPIO [7:4] Direction Control (not supported). 3:0 GPIO [3:0] Direction Control. Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) 7:4 GPIO [7:4] Unsolicited Enable Mask (not supported). 3:0 GPIO [3:0] Unsolicited Enable mask.

Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) 7:4 GPIO [7:4] Unsolicited Enable Mask (not supported). 3:0 GPIO [3:0] Unsolicited Enable Mask. Table 68. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets to return to their power-on default state.

Table 69. Verb – Get Digital Converter Control (Verb ID= F0Dh) 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer format). Only consumer channel status format is supported. This bit is always 0. 5 /AUDIO (Non-Audio Data type). 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 31:16 Reserved. Read as 0’s. 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer format). Only consumer channel status format is supported. This bit is always 0. 5 /AUDIO (Non-Audio Data type).

1 In‘V’alid. V bit in sub-frame of S/PDIF-IN. Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) 6 PRO (Professional or Consumer format). 5 /AUDIO (Non-Audio Data type).

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 60 Track ID: JATR-1076-21 Rev. 1.4 ‘Payload’ in Set Control 1 for NID=06h (S/PDIF-OUT) Bit Description – SIC (S/PDIF IEC Control) Bit [7:0] 4 COPY (Copyright). 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis). 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 0 DigEn (Digital Enable). 0: OFF (S/PDIF-OUT is in Hi-Z) 1: ON ‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7 Reserved. Read as 0’s. 6:0 CC[6:0] (Category Code). ‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7:1 Reserved. 0 DigEn (Digital Enable). 0: OFF 1: ON (S/PDIF-IN is enabled) ‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN) Bit Description – SIC (S/PDIF IEC Control) Bit[7:0] 7:0 Reserved. Read as 0’s. Note: Other widgets will ignore this verb.

Table 71. Verb – Get/Set EAPD Enable (Verb ID= F0Ch/70Ch) Note: All nodes except NID=0Fh and NID=10h will ignore this verb.

Table 72. Get/Set Volume Knob Widget (NID=21h) (Verb ID= F0Fh/70Fh) Not supported. Response will be 0 for this bit. Not supported. This bit will be ignored. Table 73. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) 31:16 Subsystem ID (Default=0260h). Note: Not supported in the ALC260 and ALC260-LF .

Table 74. Verb – Set Subsystem ID [31:0] Note1: Supported by Audio Function Group NID=01h, other widgets will ignore this verb. Note2: The BIOS can use these verbs to set the customized sub-system ID for Audio Function Group (NID=01h). Note3: Not supported in the ALC260 and ALC260-LF .

Table 75. Absolute Maximum Ratings DVDD = 3.3V±5%, Tambient = 25°C, with 50pF external load. Table 76. Threshold Voltage

Table 77. Digital Filter Characteristics DVDD= 3.3V, Tambient=25°C, with 75Ω external load. Table 78. S/PDIF Input/Output Characteristics

Table 79. Link Reset and Initialization Timing

4 BCLK 4 BCLK >= 4 BCLK

Figure 13. Link Reset and Initialization Timing

Table 80. Link Timing Parameters at the Codec Figure 14. Link Signals Timing

Table 81. S/PDIF Output and Input Timing Figure 15. Input and Output Timing Codec test mode and Automatic Test Equipment (ATE) mode are not supported.

Table 82. Analog Performance

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 70 Track ID: JATR-1076-21 Rev. 1.4 10. Application Circuits Please contact Realtek for the latest application circu its. To get the best compatibility in hardware design and software driver, Realtek should confirm any modification of appli cation circuits. Realtek may upload the latest application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet.

ALC260(D) Datasheet 2 Channel High Definition Audio Codec 71 Track ID: JATR-1076-21 Rev. 1.4 11. Mechanical Dimensions L MILLIMETER INCH SYMBOL MIN. TYP MAX. MIN. TYP MAX A 1.60 0.063 A1 0.05 0.15 0.002 0.006 c 0.09 0.20 0.004 0.008 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 E 9.00 BSC 0.354 BSC E1 7.00BSC 0.276 BSC E2 5.50 0.217 e 0.50 BSC 0.0196 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o L1 1.00 0.0393 TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm LEADFRAME MATERIAL DOC. NO. APPROVE VERSION 02 DWG NO. PKGC-065 CHECK DATE REALTEK SEMICONDUCTOR CORP.

Table 83. Ordering Information Note 1: See page 5 for lead (Pb)-free package and version identification. Realtek sales representatives or agents. Hsinchu, 300, Taiwan, R.O.C.