ALC250-LF

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TWO-CHANNEL AC’97 2.3 AUDIO CODEC with EQUALIZER DATASHEET Rev. 1.3

06 December 2005

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw ALC250 ALC250-LF

Two-Channel AC’97 2.3 Audio Codec Rev1.3 ii COPYRIGHT ©2005 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Co rporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. CONFIDENTIALITY This document is confidential and should not be provided to a third-party without the permission of Realtek Semiconductor Corporation. USING THIS DOCUMENT This document is intended for the software engi neer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.00 2003/07/31 First release. 1.01 2003/08/06 Change cover page. 1.10 2003/10/24 Add ordering information. 1.20 2005/03/18 1.For ALC250-VD, pin- 43 is Disable# (Section 9.10) 2.Serial interface signals are shifted to pin-44 and pin-45. 3. Add lead (Pb)-free and version package identification information on page 3 and on page 43. 1.3 2005/12/06 Update section 6.1.12 MX1A Record Select, page 11. Update section 12. Ordering Information, page 43.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 iii Table of Contents

Two-Channel AC’97 2.3 Audio Codec Rev1.3 iv

Two-Channel AC’97 2.3 Audio Codec Rev1.3 1 1. General Description The ALC250 is a 20-bit DAC and 18-bit ADC full duplex AC'97 2.3 compatible stereo audio CODEC designed for PC multimedia systems, including host/soft audio and AMR/CNR based designs. The ALC250 incorporates proprietary converter technology to achieve a high SNR, greater than 100 dB, sensing logics for device reporting, and Universal Audio Jack® to enhance user convenience. The ALC250 AC'97 CODEC supports multiple CODEC extensions with independent variable sampling rates and built-in 3D effects. The ALC250 CODEC provides two pairs of stereo outputs with independent volume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain, and mute functions to provide a complete integrated audio solution for PCs. The circuitry of the ALC250 CODEC operates from a +3.3V digital power and +5V analog power supply with EAPD (External Amplifier Power Down) control for use in notebook a nd PC applications. The ALC250 integrates a 50mW/20Ω headset audio amplifier into the CODEC, saving BOM costs. The ALC250 also supports the SPDIF out function, which complies with AC'97 2.3, and offers easy connection of PCs to consumer electronic products, such as AC3 decoder/speaker and mini disk devices. The ALC250 CODEC supports host/soft audio from Intel IC Hx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ ATI chipset. Bundled Windows series drivers (WinXP/ME/2000/98/NT), EAX/ Direct Sound 3D/ I3DL2/ A3D compatible sound effect u tilities (supporting Karaoke, 26-kind of environment sound emulation, and 10 software equalizer bands), HRTF 3D positional audio and Sensaura™ 3D (optional) provide an excellent entertainment package and game experience for PC users. Integrated 14.318MÆ24.576MHz PLL generate required clock to eliminate the need for external crystal. The ALC250 also builds-in seven bands of digital hardware equalizer and cascades one lowpass filter, five bandpass filters, and one highpass filter. It optimizes frequency response on mobile PC speakers. 2. Features z Built- in 7 Bands of Digital Hardware Equalizer for Optimizing Speaker Response z Single chip with high S/N ratio (>100 dB) z Meets performance requirements for audio on PC99/2001 systems z Meets Microsoft WHQL/WLP 2.0 audio requirements z 20-bit DAC and 18-bit ADC resolution z Compliant with AC’97 2.3 specifications -LINE/HP-OUT, MIC-IN and LINE-IN sensing -14.318MHz-Æ24.576MHz PLL saves crystal -12.288MHz BITCLK input can be consumed -Integrated PCBEEP generator to save buzzer -Interrupt capability -Page registers and Analog Plug&Play z Support of S/PDIF out is fully compliant with AC’97 rev2.3 specifications z Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX z High quality differential CD input z Two analog line-level mono input: PCBEEP, PHONE-IN z Supports double sampling rate (96KHz) of DVD audio playback z Two software selectable MIC inputs z +6/12/20/30dB boost preamplifier for MIC input z Stereo output with 6-bit volume control z Mono output with 5-bit volume control z Headphone output with 50mW/20Ω amplifier z 3D Stereo Enhancement z Multiple CODEC extension capability z External Amplifier Power Down (EAPD) capability z Power management and enhanced power saving

features

z Stereo MIC record for AEC/BF application z DC Voltage volume control z Auxiliary power to support Power Off CD z Adjustable VREFOUT control z EQ operation can be controlled by 2 pins of serial bus z 2 Universal Audio Jack (UAJ)® for front panel z Support 32K/44.1K/48K/96KHz of S/PDIF output z Support 32K/44.1K/48KHz of S/PDIF input z Power support: Digital: 3.3V; Analog: 3.3V/5V z Standard 48-Pin LQFP Package z EAX™ 1.0&2.0 compatible z Direct Sound 3D™ compatible z A3D™ compatible z I3DL2 compatible z HRTF 3D Positional Audio z Sensaura™ 3D Enhancement (optional) z 10 Bands of Software Equalizer z Voice Cancellation and Key Shifting in Kara OK mode z AVRack® Media Player z Configuration Panel to improve Experience of User

Two-Channel AC’97 2.3 Audio Codec Rev1.3 1 3. Block Diagram

3.1 Analog Mixer

M U X MX1C Record Gain mono mix stereo mix ADC HeadPhone Volume phone mic-L line CD aux MX22 HP-OUT LINE-OUT MONO-OUT MX20.8 ALC250 MX02 AMP RESET# MX06 MX04 Yes No stereo analog mono analog * : default setting Record Gain MIC&EQ ADC MX18 MX6A.14 MX6A.7 MX6A.8 MX1E left channel right channel Boost Boost mic-R Boost MX6A.6 0*1 Figure. Analog Mixer Diagram

Two-Channel AC’97 2.3 Audio Codec Rev1.3 2

3.2 Digital Data Path

BlockEQ&MIC ADC SPDIF Output DAC Digital EQ AC- LINK CD-In Line-In MIC-In ... Digital Process Engine Analog outputs DVOL DVOL Digital Stereo Digital Mono Analog Stereo Analog Mono 20-bit PCM 20-bit SPDIF Out Left Right Left DVOL : Digital Volume Control Digital 3D0 SPDIF Input20-bit SPDIF In 0 0 Figure. Digial Data Path Diagram

Two-Channel AC’97 2.3 Audio Codec Rev1.3 3 4. Pin Assignments MONO-OUT/VREFOUT3 AVDD2 HP-OUT-L AVSS2 AUX-L SPDIFO MIC2 JD1 PHONE LINE-IN-R AVSS1 AFILT2 VAUX DVDD1 LINE-OUT-R CD-RHP-OUT-R LINE-OUT-L DCVOL AFILT1 VREFOUT VREF AVDD1 LINE-IN-L MIC1 CD-GND CD-L XTL-IN XTL-OUT DVSS1 SDATA-OUT BIT-CLK DVSS2 SDATA-IN DVDD2 SYNC RESET# PC-BEEP NC SPDIFI/EAPD AUX-R SCK SDA NC VREFOUT2 JD2 XTLSEL NC 36 35 34 33 32 31 30 29 28 27 26 25 123456789 1 0 1 1 1 2 2437 ALC250 LLLLLLL TXXXV

4.1 Lead (Pb)-Free Package and Version Identification

Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in the figures above. The version number is shown in the location marked ‘V’.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 4 5. Pin Descriptions In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.

5.1 Digital I/O Pins

Name Type Pin No Description Characteristic Definition RESET# I 11 AC'97 H/W rese t Schmitt trigger input XTL-IN I 2 Crystal input pad Crystal: 24.576M/14.318M crystal input External: 24.576M/14.318M external clock input XTL-OUT O 3 Crystal output pad Crystal: 24.576M/14.318M crystal output External: 24.576M/14.318M clock output SYNC I 10 Sample Sync ( 48KHz) Schmitt trigger input BIT-CLK O 6 12.288MHz bit clock output CMOS output SDATA-OUT I 5 Serial TDM input from AC’97 controller CMOS input , Vt=1.65V SDATA-IN O 8 Serial TDM AC’97 Codec output CMOS output SCK (B version) I 43 Serial bit clock input Schmitt trigger input, V IL=1.0V, VIH=2.0V SDA (B version) IO 44 Serial data input/out put Schmitt trigger input, V IL=1.0V, VIH=2.0V DISABLE# (D version) I 43 Pulled low to disable ACLINK signals. Schmitt trigger input, VIL=1.0V, VIH=2.0V (SDATA-IN and BITCLK are driven low) SCK (D version) I 44 Serial bit clock input Schmitt trigger input, V IL=1.0V, VIH=2.0V SDA (D version) IO 45 Serial data input/out put Schmitt trigger input, V IL=1.0V, VIH=2.0V XELSEL I 46 Pulled low to use external 14.318MHz clock source CMOS input, Vt=0.35Vdd, internally pulled high by a 50K resistor. SPDIFI/EAPD I/O 47 S/PDIF input / External Amplifier power down control CMOS input / output SPDIFO O 48 S/PDIF output Digital output has 12 mA@75Ω driving capability. Total: 12 Pins

5.2 Analog I/O Pins

Name Type Pin No Description Characteristic Definition PC-BEEP I 12 PC speaker input Analog input (1.6Vrms) PHONE I 13 Speakerphone input Analog input (1.6Vrms) AUX-L IO 14 AUX Left channel Analog input/output AUX-R IO 15 AUX Right channel Analog input/output JD2 I 16 Jack Detect pin-2 Internally pulled high to AVDD by a 50K resistor JD1 I 17 Jack Detect pin-1 Internally pulled high to AVDD by a 50K resistor CD-L I 18 CD audio Left channel Analog input (1.6Vrms) CD-GND I 19 CD audio analog GND Analog input CD-R I 20 CD audio Right channel Analog input (1.6Vrms) MIC1 I 21 First MIC input Analog input (1.6Vrms) MIC2 I 22 Second MIC input Analog input (1.6Vrms) LINE-IN-L I 23 Line input Left channel Analog input (1.6Vrms) LINE-IN-R I 24 Line input Right channel Analog input (1.6Vrms) LINE-OUT-L O 35 Line-Out Left channel Analog output w/o amplifier LINE-OUT-R O 36 Line-Out Right channel Analog output w/o amplifier

Two-Channel AC’97 2.3 Audio Codec Rev1.3 5 Name Type Pin No Description Characteristic Definition HP-OUT-L IO 39 Headphone Out Left channel ALC250: Analog output with amplifier / Analog input HP-OUT-R IO 41 Headphone Out Left channel ALC250: Analog output with amplifier / Analog input MONO-OUT/ VREFOUT3 O 37 Mono output / Third reference voltage Analog output / Voltage output (2.5V/4.0V) Total: 18 Pins

5.3 Filter/Reference/NC

Name Type Pin No Description Characteristic Definition VREF - 27 Reference voltage 1uf capacitor to analog ground VREFOUT O 28 Ref. voltage out Analog DC voltage output (2.5V / 4.0V) AFILT1 - 29 ADC anti-aliasing filter 1000pf capacitor to analog ground. AFILT2 - 30 ADC anti-aliasing filter 1000pf capacitor to analog ground. NC - 31 Not Connection DC VOL I 32 DC Voltage Volume Control Analog Input (AGND~AVDD) VREFOUT2 O 33 Secondary Ref. voltage out Analog DC voltage output (2.5V / 4.0V) VREFOUT3 O 37 Third Ref. voltage out Analog DC voltage output (2.5V / 4.0V) VAUX I 34 Auxiliary Power to keep CD and amplifier turned on. +5V analog stand-by power NC - 40 Not Connection NC (B version) - 45 Not Connection Total: 11 Pins

5.4 Power/Ground

Name Type Pin No Description Characteristic Definition AVDD1 I 25 Analog VDD (5.0V or 3.3V) AVDD2 I 38 Analog VDD (5.0V or 3.3V) AVSS1 I 26 Analog GND AVSS2 I 42 Analog GND DVDD1 I 1 Digital VDD (3.3V) DVDD2 I 9 Digital VDD (3.3V) DVSS1 I 4 Digital GND DVSS2 I 7 Digital GND Total: 8 Pins

Two-Channel AC’97 2.3 Audio Codec Rev1.3 6 6. Registers

6.1 Mixer Registers

Access to registers with an odd number will return a 0. Reading unimplemented registers will also return a 0. X=Reserved bit. REG. (HEX) NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DEFAU LT 00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0190h 02h Master Volume Mute X ML5 ML4 ML3 ML2 ML1 ML0 RM* X MR5 MR4 MR3 MR2 MR1 MR0 8000h 04h Headphone volume Mute X HPL HPL HPL HPL HPL HPL RM* X HPR HPR HPR HPR HPR HPR 8000h 06h Mono-Out Volume Mute X X X X X X X X X X MM MM MM MM MM 8000h 0Ah PC_BEEP Volume Mute X X F7 F6 F5 F4 F3 F2 F1 F0 PB3 PB2 PB1 PB0 X 8000h 0Ch PHONE Volume Mute X X X X X X X X X X PH4 PH3 PH2 PH1 PH0 8008h 0Eh MIC Volume Mute X X X X X BGO BGO X BC X MI4 MI3 MI2 MI1 MI0 8008h 10h Line-In Volume Mute X X NL4 NL3 NL2 NL1 NL0 RM* X X NR4 NR3 NR2 NR1 NR0 8808h 12h CD Volume Mute X X CL4 CL3 CL2 CL1 CL0 RM* X X CR4 CR3 CR2 CR1 CR0 8808h 16h Aux Volume Mute X X AL4 AL3 AL2 AL1 AL0 RM* X X AR4 AR3 AR2 AR1 AR0 8808h 18h PCM Out Volume Mute X X PL4 PL3 PL2 PL1 PL0 RM* X X PR4 PR3 PR2 PR1 PR0 8808h 1Ah Record Select X X X X X LRS LRS LRS X X X X X RRS RRS RRS 0000h 1Ch ADC Record Gain Mute X X X LRG LRG LRG LRG X X X X RRG RRG RRG RRG 8000h 1Eh MIC ADC Record Gain Mute X X X LM RG3 LM RG2 LM RG1 LM RG0 X X X X RM RG3 RM RG2 RM RG1 RM RG0 8000h 20h General Purpose POP X 3D X DRS DRS MIX MS LBK X X X X X X X 0400h 22h 3D Control X X X X X X X X X X X X X DP2 DP1 DP0 0000h 24h Audio Int. & Paging I4 I3 I2 I1 I0 X X X X X X X PG3 PG2 PG1 PG0 0000h 26h Power Down Ctrl/Status EAP D PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Fh 28h Extended Audio ID ID1 ID0 X X REV REV AM AP X X X X X X SPD IF DRA VRA 0A07h 2Ah Extended Audio Status X X X X X SPC V X X X X SPS SPS X SPD IF DRA VRA 0000h 2Ch PCM front Out Sample Rate FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR BB80h 32h PCM Input Sample Rate ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR BB80h 34h MIC Input Sample Rate MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR BB80h 3Ah S/PDIF Ctl V DRS SPS SPS L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COP Y /AU DIO PRO 2000h 60h/ 6Eh Vendor Define 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 76h GPIO Setup 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 78h GPIO Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 414Ch 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 DEV DEV DEV DEV DEV DEV DEV DEV 4750h

Two-Channel AC’97 2.3 Audio Codec Rev1.3 7

6.1.1 MX00 Reset

Default: 0190h Writing any value to this register will start a register reset, and cause all registers to revert to their default values. The written data is ignored. Reading this register returns the ID code of the specific part. Bit Type Function

15 Reserved

14:10 R Return 00000b

9 R Read as 0 (No support for 20-bit ADC)

8 R Read as 1 (Support for 18-bit ADC)

7 R Read as 1 (Support for 20-bit DAC)

6 R Read as 0 (No support for 18-bit DAC)

5 R Read as 0 (No support for Loudness)

4 R Read as 1 (Headphone output support)

3 R Read as 0 (No simulated stereo; for analog 3D block use)

2 R Read as 0 (No Bass & Treble Control)

1 R Reserved, Read as 0

0 R Read as 0 (No dedicated MIC PCM input)

6.1.2 MX02 Master Volume

Default: 8000h These registers control the overall volume level of the output f unctions. Each step on the left and right channels correspond t o 1.5dB in increase/decrease in volume. Bit Type Function

15 R/W Mute Control 0: Normal 1: Mute (-∞ dB)

14 Reserved

13:8 R/W Master Left Volume (MLV[5:0]) in 1.5 dB steps 7:6 Reserved 5:0 R/W Master Right Volume (MRV[5:0]) in 1.5 dB steps n For MRV/MLV: 00h 0 dB attenuation 3Fh 94.5 dB attenuation

6.1.3 MX04 Headphone

Default: 8000h Register 04h controls the headphone (ALC250) output volume. Each step in bits 5:0 and 13:8 correspond to 1.5dB in increase/decrease in volume, allowing 63 levels of volume, from 000000 to 111111. Bit Type Function 13:8 R/W Headphone/True Line Output Left Volume (HPL[5:0]) in 1.5 dB steps 7:6 Reserved 5:0 R/W Headphone/True Line Output Right Volume (HPR[5:0]) in 1.5 dB steps n For HPR/HPL: 00h 0 dB attenuation 3Fh 94.5 dB attenuation

Two-Channel AC’97 2.3 Audio Codec Rev1.3 8

6.1.4 MX06 MONO_OUT Volume

Default: 8000h Register 06h controls the mono volume output. Mono output is the same data sent on all output channels. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111. Bit Type Function 14:5 Reserved 4:0 R/W Mono Master Volume (MMV[4:0]) in 1.5 dB steps n For MMV: 00h 0 dB attenuation 1Fh 46.5 dB attenuation

6.1.5 MX0A PC BEEP Volume

Default: 8000h This register controls the input volume for the PC beep signal. Each step in bits 4:1 correspond to a 3dB increase/decrease in volume. 16 levels of volume are available, from 0000 to 1111. The purpose of this register is to allow the PC Beep signals to pass through the ALC250, eliminating the need for an external system speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the LINE-OUTL & R pins. If the PC speaker/buzzer is eliminated, it is recommended to connect the external speakers at all times so the POST codes can be heard during reset. Bit Type Function 14:13 Reserved 12:5 R/W Internal PCBEEP Frequency, F[7:0] The internal PCBEEP frequency is the result of dividing the 48KHz clock by 4 times the number specified in F[7:0]. The lowest tone is 48KHz/(255*4)=47Hz. The highest tone is 48KHz/(1*4)=12KHz. A value of 00h in F[7:0] disables internal PCBEEP generator and allows external PCBEEP input. 4:1 R/W PC Beep Volume (PBV[3:0]) in 3 dB steps

0 Reserved

n For PBV: 00h 0 dB attenuation 0Fh 45 dB attenuation

6.1.6 MX0C PHONE Volume

Default: 8008h Register 0Ch controls the telephone input volume for software modem applications. Because software modem applications may not have a speaker, the CODEC can offer a speaker-out service. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 14:5 Reserved 4:0 R/W Phone Volume (PV[4:0]) in 1.5 dB steps n For PV: 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain

Two-Channel AC’97 2.3 Audio Codec Rev1.3 9

6.1.7 MX0E MIC Volume

Default: 8008h Register 0Eh controls the microphone input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume, allowing 32 levels of volume, from 00000 to 11111. Bit 6 enables/disables a boost in volume to a magnification based on bits 9:8. Bit Type Function 14:10 Reserved 9:8 R/W Boost Gain Option (BGO) 00: 20 dB 01: 6 dB 10: 12 dB 11: 29.5 dB (V=30*Vmic-in)

7 Reserved

6 R/W Boost Control (BC)

0: Disable 1: Enable Boost

5 Reserved

4:0 R/W Mic Volume (MV[4:0]) in 1.5 dB steps n For MV: 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain o If 29.5dB boost gain is selected, input resistor can be reduced to save area of feedback resistor.

6.1.8 MX10 LINE_IN Volume

Default: 8808h Register 10h controls the LINE_IN input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 14:13 Reserved 12:8 R/W Line-In Left Volume (NLV[4:0]) in 1.5 dB steps 7:5 Reserved 4:0 R/W Line-In Right Volume (NRV[4:0]) in 1.5 dB steps n For NLV/NRV: 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain

6.1.9 MX12 CD Volume

Default: 8808h Register 12h controls the CD input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 14:13 Reserved 12:8 R/W CD Left Volume (CLV[4:0]) in 1.5 dB steps 7:5 Reserved 4:0 R/W CD Right Volume (CRV[4:0]) in 1.5 dB steps n For CLV/CRV: 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain

Two-Channel AC’97 2.3 Audio Codec Rev1.3 10

6.1.10 MX16 AUX Volume

Default: 8808h Register 16h controls the auxiliary input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 14:13 Reserved 12:8 R/W AUX Left Volume (ALV[4:0]) in 1.5 dB steps 7:5 Reserved 4:0 R/W AUX Right Volume (ARV[4:0]) in 1.5 dB steps n For ALV/ARV: 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain

6.1.11 MX18 PCM_OUT Volume

Default: 8808h Register 18h controls the PCM_OUT output volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. Bit Type Function 14:13 Reserved 12:8 R/W PCM Volume (PLV[4:0]) in 1.5 dB steps 7:5 Reserved 4:0 R/W PCM Right Volume (PRV[4:0]) in 1.5 dB steps n For PLV/PRV: 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain

Two-Channel AC’97 2.3 Audio Codec Rev1.3 11

6.1.12 MX1A Record Select

Default: 0000h Register 1Ah controls the record input source. Each bit in bits 2:0 selects a recording source for the right channel. Each bit in bits 10:8 selects a recording source for the left channel. Bit Type Function 15:11 Reserved 10:8 R/W Left Record Source Select (LRS[2:0]) 7:3 Reserved 2:0 R/W Right Record Source Select (RRS[2:0]) n For LRS

0 MIC

1 CD LEFT

2 Muted

3 AUX LEFT

4 LINE LEFT

5 STEREO MIXER OUTPUT LEFT

6 MONO MIXER OUTPUT

7 PHONE

1 CD RIGHT

3 AUX RIGHT

4 LINE RIGHT

5 STEREO MIXER OUTPUT RIGHT

6.1.13 MX1C Record Gain for Stereo ADC

Default: 8000h Register 1Ch controls the record gain. Each step in bits 3:0 correspond to 1.5dB in increase/decrease in gain for the right channel, allowing 16 levels of gain, from 0000 to 1111. Each step in bits 11:8 correspond to 1.5dB in increase/decrease in gain for the left channel, allowing 16 levels of gain, from 0000 to 1111. Bit Type Function 14:12 Reserved 11:8 R/W Left Record Gain Select (LRG[3:0]) in 1.5 dB steps 7:4 Reserved 3:0 R/W Right Record Gain Select (RRG[3:0]) in 1.5 dB steps nFor LRG/RRG: 0Fh +22.5dB 00h 0 dB (No Gain)

Two-Channel AC’97 2.3 Audio Codec Rev1.3 12

6.1.14 MX1E Record Gain for MIC ADC

Default: 8000h Register 1Eh controls the record gain. Each step in bits 3:0 correspond to 1.5dB in increase/decrease in gain for the right channel, allowing 16 levels of gain, from 0000 to 1111. Each step in bits 11:8 correspond to 1.5dB in increase/decrease in gain for the left channel, allowing 16 levels of gain, from 0000 to 1111. Bit Type Function 14:12 Reserved 11:8 R/W Left Record Gain Select (LMRG[3:0]) in 1.5 dB steps 7:4 Reserved 3:0 R/W Right Record Gain Select (RMRG[3:0]) in 1.5 dB steps nFor LRG/RRG: 0Fh +22.5dB 00h 0 dB (No Gain)

6.1.15 MX20 General Purpose Register

Default: 0000h This register is used to control several functions. Bit 13 enables or disables 3D control. Bit 9 allows selection of mono output. Bit 8 controls the MIC selector. Bit 7 enables loopback of the AD output to the DA input without involving the AC-Link, allowing for full system performance measurements. Bit Type Function 15:14 Reserved, Read as 0

13 R/W 3D Control 1: On 0: Off

12:9 Reserved, Read as 0

8 R/W MIC Select 0: MIC 1 1: MIC 2

7 R/W AD to DA Loop-back Control 0: Disable 1: Enable

6:0 Reserved

6.1.16 MX22 3D Control

Default: 0000h This register is used to control the 3D stereo enhancement function built into the AC’97 component. The register bits, DP2-DP0 are used to control the separation ratios in the analog 3D and digital 3D for both LINE_OUT and HP_OUT. The 3D stereo function provides for a deeper and wider sound experience. Note that the 3D bit in the MX20.[13] must be set to 1 to enable this function. Bit Type Function 15:3 Reserved, Read as 0 2:0 R/W Depth Control (DP[2:0]) n3D effect control DP[2:0] Function DP[2:0] Function 000 0% (off) 100 50% 001 12.5% 101 67.5% 010 25% 110 75% 011 37.5 111 100%

Two-Channel AC’97 2.3 Audio Codec Rev1.3 13

6.1.17 MX24 Audio interrupt and Paging

Default: 0000h Bit Type Function

15 Interrupt Status, I4

0: Interrupt is clear. 1: Interrupt was generated Interrupt event and status are clear by writing a 1 to this bit. The status will change regardless of interrupt enable (I0).

14 R Interrupt Cause, I3

I3=0: GPIO, SPDIF-IN and Jack-Detect interrupt status in MX78 are not changed. 1: GPIO, SPDIF-IN and Jack-Detect interrupt status in MX78 are changed. This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt status (I4) has been confirmed as interrupting. I3 will be zero when I4 is cleared.

13 R Interrupt Cause, I2

I2=0: Sense value in page ID-01h MX6A.[12:8] has not changed. 1: Sense cycle completed or new sense value in page ID-01h MX6A.[12:8] is available. This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt status (I4) has been confirmed as interrupting. I2 will be zero when I4 is cleared.

12 R/W Sense Cycle, I1

0: Sense cycle not in progress 1: Sense cycle start Writing a ‘1’ to this bit causes a sense cycle start. If a sense cycle is in progress, writing a ‘0’ to this bit will abort the sense cycle. Whether the data in the sense result register (page ID-01h MX6A) is valid or not is determined by the IV bit in MX6A, Page ID-1h.

11 R/W Interrupt Enable, I0

0: Interrupt is masked, interrupt status (I4) will not be shown in bit 0 in Slot 12 in SDATA-IN. 1: Interrupt is un-masked, interrupt status (I4) will be shown in bit 0 in Slot 12 in SDATA-IN. 10:4 NA Reserved, read as 0 3:0 R/W Page Selector, PG[3:0] 0000b: Vendor Specific 0001b: Page ID 01 (AC’97 2.3 Discovery Descriptor Definition) Others: Reserved. This register is used to select a descriptor of 16 word pages between registers MX60 to MX6F. Value of 0 is used to select vendor specific space to maintain compatibility with AC’97 2.2 vendor specific register. Once PG[3:0] is not 0000b and 0001b, ALC250 will return zero data for ACLINK mixer read command.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 14

6.1.18 MX26 Powerdown Control/Status

Default: 000Fh This read/write register is used to program powerdown states and monitor subsystem readiness. The lower half of this register is read only status; a “1” indicating that the subsection is “ready.” Ready is defined as the subsection’s ability to perform in its nominal state. When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC’97 control and status registers are in a fully operational state. The AC’97 controller must further probe this powerdown control /status register to determine exactly which subsections, if any are ready. Bit Type Function

15 R/W PR7 External Amplifier Power Down (EAPD) 0: Normal 1: Power down

14 R/W PR6 0: Normal 1: Power down Headphone Out (HP-OUT, pin-39/41)

13 R/W PR5 0: Normal 1: Disable internal clock

12 R/W PR4 0: Normal 1: Power down AC-Link

11 R/W PR3 0: Normal 1: Power down Mixer (Vref off)

10 R/W PR2 0: Normal 1: Power down Mixer (Vref still on)

9 R/W PR1 0: Normal 1: Power down PCM DAC

8 R/W PR0 0: Normal 1: Power down PCM ADC and input MUX

7:4 Reserved, Read as 0

3 R Vref Status 1: Vref is up to normal level 0: Not yet ready

2 R Analog Mixer Status 1: Ready 0: Not yet ready

1 R DAC Status 1: Ready 0: Not yet ready

0 R ADC Status 1: Ready 0: Not yet ready

nTruth table for power down mode : ADC DAC Mixer Verf ACLINK Int CLK HP-OUT EAPD PR0=1 PD PR1=1 PD PR2=1 PD PD PR3=1 PD PD PD PD PD PR4=1 PD PD PD PR5=1 PD PD PD P R 6 = 1 P D P R 7 = 1 P D PD: Power down Blank: Don’t care oIf Mixer is power down (PR2=1 or PR3=1), the LINE-OUT (pin-35/36) is shut down and its output is floated. pIf Headphone-Out is power down (PR6=1), the HP-OUT (pin-39/41) is shut down and its output is floated.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 15

6.1.19 MX28 Extended Audio ID

Default: 0605h The Extended Audio ID register is a read only register used to communicate information to the digital controller on two functions. ALC250 is designed as the primary CODEC with ID is ‘00’. Bit Type Function 15:14 R ID[1:0], read as ‘00’. 13:12 Reserved, Read as 0 11:10 R REV[1:0]=10 to indicate that the ALC250 is AC’97 rev2.3 compliant

9 R AMAP read as 1 (DAC mapping based on ID)

8:6 Reserved, Read as 0 5:4 R/W DAC Slot Assignment DSA[1:0] (Default value depends on ID[1:0]) DSA[1:0] Controls the DAC slot assignment, as described in AC’97 rev2.2.

3 Reserved, Read as 0

2 R SPDIF Read as 1 (S/PDIF is supported)

1 R DRA Read as 1

0 R VRA Read as 1 (Variable Rate Audio is supported)

nThe ALC250 maps DAC slot according to the following table: (default maps to AC’97 spec. rev2.3) DSA[1:0] Left DAC slot # Right DAC slot # Comment 0,0 3 4 Default when ID[1:0]=00 0,1 7 8 Default when ID[1:0]=01,10 1,0 6 9 Default when ID[1:0]=11 1,1 10 11 -

6.1.20 MX2A Extended Audio Status and Control

Default: 0000h This register contains two active bits for powerdown and status of the surrounding DACs. Bits 0, 1 & 2 are read/write bits which are used to enable or disable VRA, DRA and SPDIF respectively. Bits 4 & 5 are read/write bits used to determine the AC-LINK slot assignment of the S/PDIF. Bit 10 is a read only bit which tells the controller if the S/PDIF configuration is valid. Bit Type Function

15 R/W Validity Configuration of S/PDIF Output (VCFG)

Combines with MX3A.15 to decide validity control in S/PDIF output signal. 14:11 NA Reserved

10 R S/PDIF Configuration Valid (SPCV)

0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid. 1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid. 9:6 Reserved 5:4 R/W SPSA[1:0], S/PDIF Slot Assignment when DRS=0 00: S/PDIF source data assigned to AC-LINK slot3/4 01: S/PDIF source data assigned to AC-LINK slot7/8 (Default when ID=00) 10: S/PDIF source data assigned to AC-LINK slot6/9 (Default when ID=01,10) 11: S/PDIF source data assigned to AC-LINK slot10/11 (Default when ID=11) SPSA[1:0], S/PDIF-Out Slot Assignment when DRS=1(for 96K S/PDIF-Out) 01: S/PDIF-Out source is from AC-LINK slot3/4 + slot7/8.

3 Reserved

2 R/W SPDIF 1: Enable 0: Disable (SPDIFO is in high impedance)

1 R/W DRA 1: Enable 0: Disable

0 R/W VRA 1: Enable 0: Disable

n If VRA = 0, ALC250 ADC/DAC operate at fixed 48KHz sampling rate. Otherwise, it operates with variable sampling rate defined in MX2C and MX32. VRA also control write operation of MX2Cand MX32.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 16 o DRA can be written when (ID=00)&(DSA=00), otherwise it is always 0. If DRA = 1, DAC operates at a fixed 96KHz sampling rate. The PCM(n) and PCM(n+1) data is captured in the same frame. In this mode, MX2C is fixed at BB80h, MX32 and ADC is still controlled by VRA. pSPCV is a read only bit that indicates whether the current S/PDIF-Out configuration is supported or not. If the configuration is supported, SPCV is set as 1 by H/W. So driver can check this bit to determine the status of the S/PDIF transmitter system. SPCV is always operating, independent of the SPDIF enable bit (MX2A.2). The S/PDIF output is active if MX2A.2 is set in spite of SPCV. Once S/PDIF output is enabled but SPCV is invalid (SPCV=0), channel status is still output, but the output data bits will be all zero.

6.1.21 MX2C PCM DAC Rate

Default: BB80h The ALC250 allows adjustment of the output sample rate. This register is used to adjust the sample rate. By changing the values, sampling rates from 8000 to 48000 can be chosen. Bit Type Function 15:0 R/W Output Sampling Rate FOSR[15:0] n The ALC250 supports the following sampling rates, as required in the PC99/PC2001 design guide. Sampling rate FOSR[15:0] 8000 1F40h 11025 2B11h 12000 2EE0 16000 3E80h 22050 5622h 24000 5DC0 32000 7D00h

44100 AC44h

48000 BB80h

oNote that If the value written is not support, the closest value is returned. When MX2A.0=0 (VRA is disable), this register will return BB80h when read.

6.1.22 MX32 PCM ADC Rate

Default: BB80h The ALC250 allows adjustment of the input sample rate. This register is used to adjust the sample rate. By changing the values, sampling rates from 8000 to 48000 can be chosen. Bit Type Function 15:0 R/W Output Sampling Rate FISR[15:0] n The ALC250 supports the following sampling rates, as required in the PC99/PC2001 design guide. Sampling rate FISR[15:0] 8000 1F40h 11025 2B11h 12000 2EE0 16000 3E80h 22050 5622h 24000 5DC0 32000 7D00h oNote that If the value written is not support, the closest value is returned. When MX2A.0=0 (VRA is disable), this register will return BB80h when read.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 17

6.1.23 MX3A S/PDIF Out Channel Status/Control

Default: 2000h Bit Type Function

15 R/W Validity Control (control V bit in Sub-Frame)

0: The V bit (valid flag) in sub-frame depends on whether the S/PDIF data is under-run or over-run. 1: The V bit in sub-frame is always send as 1 to indicate the invalid data is not suitable for receiver.

14 R DRS (Double Rate S/PDIF)

0: 32K, 44.1K, 48K S/PDIF-Out 1: 96K S/PDIF-Out This bit only can be set when SPSR is 10b. 13:12 R/W S/PDIF Sample Rate SPSR[1:0] 00: Sample rate set to 44.1KHz, Fs[0:3]=0000 01: Reserved 10: Sample rate set to 48.0KHz, Fs[0:3]=0100 (default) 11: Sample rate set to 32.0KHz, Fs[0:3]=1100

11 R/W Generation Level (LEVEL)

10:4 R/W Category Code (CC[6:0])

3 R/W Preemphasis (PRE)

0: None 1: Filter preemphasis is 50/15 usec

2 R/W Copyright (COPY)

0: Not asserted 1: Asserted

1 R/W Non-Audio Data type (/AUDIO)

0: PCM data 1: AC3 or other digital non-audio data

0 R Professional or Consumer format (PRO)

0: Consumer format 1: Professional format The ALC250 supports consumer channel status format, so this bit is always 0. nThe consumer channel status block (bit0~bit31): 0 1 2 3 4 5 6 7 PRO=0 /AUDIO COPY PRE 0 0 0 0 8 9 10 11 12 13 14 15 CC0 CC1 CC2 CC3 CC4 CC5 CC6 LEVEL 16 17 18 19 20 21 22 23 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 Fs0 Fs1 Fs2 Fs3 0 0 0 0 o The ‘V’ bit in the sub-frame is determined by Validity control (MX3A.15) and VCFG (MX2A.15): Validity VCFG Operation 0 0 If S/PDIF FIFO is under-run, the ‘V’ bit in the sub-frame is set to indicate that the S/PDIF data is invalid. 0 1 If S/PDIF FIFO is under-run, the ‘V’bit in the sub-frame is always 0 , and pads the data with “0”s. 1 0 The ‘V’ bit is always 1, and data bits (bit 8 ~ bit 27) should be forced to 0. 1 1 The ‘V’ bit in sub-frame is always “ ‘0’, and the S/PDIF output data should be forced to zero.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 18

6.2 Vendor Defined Registers (Page ID-00h)

These registers are available to Realtek and Realtek customers for specialized functions.

6.2.1 MX60 S/PDIF Input Channel Status [15:0]

Default: 0000h The data in MX60 are captured from channel status [15:0] of S/PDIF-IN signal. Bit Type Function

15 R LEVEL (Generation Level)

14:8 R CC[6:0] (Category Code) 7:6 R Mode[1:0] 5:3 R PRE[2:0] (Pre-Emphasis)

2 R COPY (Copyright)

0: asserted 1: Not asserted

1 R /AUDIO (Non-Audio Data type)

0: PCM data 1: AC3 or other digital non-audio data

0 R PRO (Professional or Consumer format)

0: consumer format 1: professional format

6.2.2 MX62 S/PDIF Input Channel Status [29:15]

Default: 0000h The data in MX62 are captured from channel status [29:16] of S/PDIF-IN signal. Bit Type Function

15 R “V” bit in sub-frame of SPDIFI

0: Data X and Y are valid 1: At least one of data X and Y is invalid This bit is real-time updated, and it is meaning when S/PDIF-IN is locked

14 R S/PDIF-IN Input Signal Locked by hardware

0: Unlocked 1: Locked 13:12 R Ca[1:0] ( Clock Accuracy) 11:8 R Fs[3:0]. (Sample Frequency in channel status) 0000: 44.1KHz 0010: 48 KHz 0011: 32 KHz Others: Reserved 7:4 R Cn[3:0] (Channel Number) 3:0 R Sn[3:0] (Source Number)

6.2.3 MX64 EQualizer Control Index Port

Default: 0000h Bit Type Function 15:6 NA Reserved 3:0 R/W EQ Control Registers Index

Two-Channel AC’97 2.3 Audio Codec Rev1.3 19

6.2.4 MX64 EQualizer Control Data Port

Default: 0000h Bit Type Function 15:0 R/W EQ Control Registers Data nData written into this mixer will set the EQ register MX64 points to. Read this mixer will get the register content MX60 points to.

6.2.5 MX6A Data Flow Control

Default: 0308h Bit Type Function

15 R/W SDATA-IN Slot 6 Source

0: EQ&MIC ADC Left Channel 1: Original ADC Left Channel

14 R/W Direct DAC Mode

0: Analog output is from summation of DAC and analog inputs. 1: Analog output is from DAC. 13:12 R/W S/PDIF Out Source 00: S/PDIF data is from ACLINK controller 01: Reserved. 10: Directly bypass S/PDIF-In signal to S/PDIF-Out. 11: Reserved.

11 R/W Recorded PCM Data to ACLINK

0: Recorded PCM data to host is from original ADC 1: Recorded PCM data to host is from S/PDIF-IN

10 R/W DAC Source

0: DAC data is from ACLINK controller. 1: DAC data is from DPE.

9 R/W DPE (Digital Process Engine) ADC Source

0: EQ&MIC ADC. 1: Original ADC.

8 R/W EQ&MIC ADC Record Select

0: From mixed signal of MIC, LINE-In, CD-In, AUX-In and VIDEO-In. 1: Left channel is from MIC, right channel is from sum of others. Data to DPE is composed of right channel and its duplicated one.

7 R/W MIC2 Source

0: MIC2 1: (MIC1+MIC2)/2.

6 R/W ADC MIC Source

0: Mono duplicated. (Default) 1: Stereo. 5:4 NA Reserved 3:2 R/W Function Selection for pin-47 and pin-16. MX6A.[3:2] Pin-47 Pin-16 Note

00 EAPD (Out) S/PDIF-In (In)

01 EAPD (Out) JD2 (In)

10 S/PDIF-In (In) JD2 (In) (Default)

11 JD2 (In) S/PDIF-In (In) Compatible with ALC202

1 R/W S/PDIF-In Enable

0: Disable 1: Enable

0 R/W S/PDIF-In Monitoring Control

0: Disable, SPDIFI data is not added into PCM data to DAC. (Default) 1: Enable, SPDIFI data will be added into PCM data to DAC after SPDIFI is locked.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 20

6.3 Discovery Descriptor (Page ID-01h)

These registers are defined in Ac’97 2.3 for sensing and analog plug&play functions.

6.3.1 MX62 PCI Sub System ID

Default: FFFFh Bit Type Function 15:0 R/W PCI Sub System Vendor ID This register can be written once only after power on. BIOS can set its own sub-system ID. The default value FFFFh means this register is implemented and data is not set by BIOS.

6.3.2 MX64 PCI Sub Vendor ID

Default: FFFFh Bit Type Function 15:0 R/W PCI Vendor ID This register can be written once only after power on. BIOS can set its own sub-vendor ID. The default value FFFFh means this register is implemented and data is not set by BIOS.

6.3.3 MX66 Sense Function Select

Default: 0000h Bit Type Function 15:5 Reserved 4:1 R/W Function Code bits, FC[3:0] These bits specify the type of audio function described in page ID-01h MX66, MX68 and MX6A. 0h: LINE OUT 1h: HP OUT 5h: MIC1 In 6h: MIC2 In 7h: LINE In Others: Not supported

0 R/W Tip or Ring Selection, T/R

This bit sets which jack conductor the sense value is measured from. It is combined with FC[3:0]. 0: Tip (Left channel) 1: Ring (Right channel)

Two-Channel AC’97 2.3 Audio Codec Rev1.3 21

6.3.4 MX68 Sense Function Information

Default: 02F1h Bit Type Function 15:11 R/W Gain bits, G[4:0] These bits are updated by BIOS to tell driver the gain supported by external amplifier. 1 LSB = 1.5dBV 00000b: 0dBV, 00001b: +1.5dBV,… 01111b:+24dBV 10000b: 0dBV, 10001b: -1.5dBV,… 11111b: -24dBV

10 R/W Inversion bit, INV

0: No inversion reported 1: Inverted. 9:5 R/W Buffer delays, DL[4:0] Delay measurement for the signal from inputs to outputs channels in 20.83 usec (1/48000 second) units.

4 R/W Information Valid bit, IV

0: After a sense cycle is completed indicates that no information is provided on the sensing method 1: After a sense cycle is completed indicates that information is provided on the sensing method Clearing this bit by writing “1”, writing “0” to this bit has no effect. 3:1 NA Reserved

0 R Function Information Present, FIP

This bit is set to a ‘1’ indicates that the G[4:0], INV, DL[4:0] and ST[2:0] bits are supported and are Read/Write capable.

6.3.5 MX6A Sense Detail

Default: 0000h Bit Type Function 15:13 R/W Connection/Jack Location bits, ST[2:0] 000b: Rear I/O Panel (Default) 001b: Front Panel 010b: Motherboard 011b: Dock/External 100b ~ 110b: Reserved 111b: Unused I/O. These bits should be written by BIOS to let driver know where those I/O FC[3:0] specify are located. 12:8 R Sense bits, S[4:0] (Default value depends on sensed result after Cold Reset) For output devices: 02h: Not specificed or unknown 05h: Powered speaker 06h: Earphone or passive speaker Other: Not supported For input deices: 12h: Not specified or unknown 13h: Mono Microphone 15h: Stereo Line-In Other: Not supported This field reports the type of output/input peripheral plugged in the jack after sensing. 7:0 R Always read as 0.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 22

6.4 Extension Registers

6.4.1 MX76 GPIO & Interrupt Setup

Default: 0000h Bit Type Function

15 R/W GPIO Statue Indication in SDATA_IN

0:The status of JD and its valid tag is not indicated in SDATA_IN. 1: The status of JD and its valid tag is indicated in SDATA_IN

14 R/W SPDIFI Valid Interrupt Enable

0:Disable 1: Enable

13 R/W SPDIFI Lock Interrupt Enable

0:Disable 1: Enable

12 R/W JD2 (Jack-Detect 2) interrupt Enable

0: Disable 1: Enable. A low to high transaction will trigger the JD2 interrupt in bit0 of SDATA_IN’s slot-12. 11:7 Reserved

6 R/W JD1 (Jack-Detect 1) interrupt Enable

0: Disable 1: Enable. A low to high transaction will trigger the JD interrupt in bit0 of SDATA_IN’s slot-12. 5:0 Reserved

6.4.2 MX78 GPIO & Interrupt Status

Default: 0000h Bit Type Function

15 NA Reserved

14 R/W S/PDINF-In Valid Interrupt Status (SPDIFIN_VIS). 0: No SPDIFI Valid Interrupt. 1: SPDIFI Valid interrupt. Write 1 to clear this status bit and its interrupt. 13 R/W S/PDINF-In Lock Interrupt Status (SPDIFIN_LIS). 0: No SPDIFI Lock interrupt. 1: SPDIFI LOCK interrupt. Write 1 to clear this status bit and its interrupt.

12 R/W JD2 Interrupt Status (JD2_IS)

0: No JD2 interrupt. 1: JD2 interrupt. Write 1 to clear this status bit. 11:7 NA Reserved

6 R/W JD1 Interrupt Status (JD1_IS)

0: No JD1 interrupt. 1: JD1 interrupt. Write 1 to clear this status bit. 5:3 NA Reserved

2 R Jack-Detect Event (JDEVT)

0: No Jack-Detect event occurs. 1: Jack-Detect event occurs. JDEVT = JDS1 | JDS2 Software can check this bit and MX7A.1 to know the status of JDx. When MX7A.5=0, MX7A.1=JDS1. When MX7A.5=1, MX7A.1=JDS2.

0 NA Reserved

Two-Channel AC’97 2.3 Audio Codec Rev1.3 23

6.4.3 MX7A Miscellaneous Control

Default: 0000h Bit Type Function 15:11 NA Reserved

10 R/W Pin-37 Function Selection (MONO-OUT or Vrefout3)

0: Vrefout3 1: MONO-OUT

9 R/W Vrefout Off Control

0: Vrefout is normal on (output of buffered Vref). 1: Vrefout is off. (In High-Z).

8 R/W Vrefout / Vrefout2 / Vrefout3 Level Control

0: 2.5V 1: 4.0V 7:6 NA Reserved 5 R/W Source of Jack-Detect status for MX7A.1 0: MX7A.1 indicates the status of Jack-Detect 1 1: MX7A.1 indicates the status of Jack-Detect 2

4 R/W HP-OUT Control

0: Normal 1: HP-OUT is muted by H/W when MX7A.1=1

3 R/W MONO-OUT Control

0: Normal 1: MONO-OUT is muted by H/W when MX7A.1=1

2 R/W SPDIF Output Gating

0: SPDIF output is not gated with MX7A.1 1: SPDIF output is gated with MX7A.1.

1 R Status of Jack-Detect 1 or 2 (JDSx)

0: JDSx is pull low 1: JDSx is floating or pull high

0 R/W LINE-OUT Output Control

0: Normal 1: LINE-OUT output is muted by H/W when MX7A.1=1

6.4.4 MX7C Vendor ID1

The two registers (MX7C Vendor ID1 and MX7E Vendor ID2) contain four 8-bit ID codes. The first three codes have been assigned by Microsoft for Plug and Play definitions. The fourth code is a Realtek assigned code identifying the ALC250. The MX7C Vendor ID1 register contains the value 414Ch, which is the first and second characters of the Microsoft ID code. The MX7C Vendor ID2 register contains the value 4750h, which is the third of the Microsoft ID code Default: 414Ch Bit Type Function 15:0 R Vendor ID “AL”

6.4.5 MX7E Vendor ID2

Default: 4750h Bit Type Function 15:8 R Vendor ID - “G” 7:0 R Device ID – 50h for ALC250

Two-Channel AC’97 2.3 Audio Codec Rev1.3 24

6.5 EQualizer Control Registers

6.5.1 Index-00h EQ Band-0 Coefficient (Low Pass Filter, LP0: a1)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.2 Index-02h EQ Band-0 Gain (Low Pass Filter, LP0: Ho)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)

6.5.3 Index-03h EQ Band-1 Coefficient (Band Pass Filter, BP1: a1)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.4 Index-04h EQ Band-1 Coefficient (Band Pass Filter, BP1: a2)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.5 Index-05h EQ Band-1 Gain (Band Pass Filter, BP1: Ho)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)

6.5.6 Index-06h EQ Band-2 Coefficient (Band Pass Filter, BP1: a1)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.7 Index-07h EQ Band-2 Coefficient (Band Pass Filter, BP1: a2)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.8 Index-08h EQ Band-2 Gain (Band Pass Filter, BP2: Ho)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)

6.5.9 Index-09h EQ Band-3 Coefficient (Band Pass Filter, BP3: a1)

Default: 0000h Bit Type Function

Two-Channel AC’97 2.3 Audio Codec Rev1.3 25 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.10 Index-0Ah EQ Band-3 Coefficient (Band Pass Filter, BP3: a2)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.11 Index-0Bh EQ Band-3 Gain (Band Pass Filter, BP3: Ho)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)

6.5.12 Index-0Ch EQ Band-4 Coefficient (Band Pass Filter, BP4: a1)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.13 Index-0Dh EQ Band-4 Coefficient (Band Pass Filter, BP4: a2)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.14 Index-0Eh EQ Band-4 Gain (Band Pass Filter, BP4: Ho)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)

6.5.15 Index-0Fh EQ Band-5 Coefficient (Band Pass Filter, BP5: a1)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.16 Index-10h EQ Band-5 Coefficient (Band Pass Filter, BP5: a2)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.17 Index-11h EQ Band-5 Gain (Band Pass Filter, BP5: Ho)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)

Two-Channel AC’97 2.3 Audio Codec Rev1.3 26

6.5.18 Index-12h EQ Band-6 Coefficient (High Pass Filter, HP6: a1)

Default: 0000h Bit Type Function 15:0 R/W 16-bit 2’s complement coefficient. Range= -2 ~ 1.99

6.5.19 Index-13h EQ Band-6 Coefficient (High Pass Filter, HP6: a2)

Default: 0000h Bit Type Function 15:1 NA Reserved

0 R/W 0: 20dB/decade slope 1: 40dB/decade slope (2 cascaded HP6)

6.5.20 Index-20h EQ Control & Status Register

Default: 0000h Bit Type Function

15 R/W Digital Process Engine Output Control

0: Bypass digital EQ (Default) 1: Digital EQ output. 14 R/W EQ Band-6 Control. 0: Disable 1: Enable. 13 R/W EQ Band-5 Control. 0: Disable 1: Enable. 12 R/W EQ Band-4 Control. 0: Disable 1: Enable. 11 R/W EQ Band-3 Control. 0: Disable 1: Enable. 10 R/W EQ Band-2 Control. 0: Disable 1: Enable. 9 R/W EQ Band-1 Control. 0: Disable 1: Enable. 8 R/W EQ Band-0 Control. 0: Disable 1: Enable.

7 R/W Bypass Digital EQ Control by JDx

0:Normal, bypass EQ control is decided by EQ Control&Status register Index-20h.15 (Default) 1: Bypass digital EQ by H/W when MX7A.1=1 The EQ function is planned to compensate frequenc y response for mini speaker, it should be bypassed when headphone jack is plugged to be output device. 6 R EQ Band-6 Status. 0: No rmal 1: Overflow. This bit is set if overflow had ever occurred. Write 1 to clear it. 5 R EQ Band-5 Status. 0: No rmal 1: Overflow. This bit is set if overflow had ever occurred. Write 1 to clear it. 4 R EQ Band-4 Status. 0: No rmal 1: Overflow. This bit is set if overflow had ever occurred. Write 1 to clear it. 3 R EQ Band-3 Status. 0: No rmal 1: Overflow. This bit is set if overflow had ever occurred. Write 1 to clear it. 2 R EQ Band-2 Status. 0: No rmal 1: Overflow. This bit is set if overflow had ever occurred. Write 1 to clear it. 1 R EQ Band-1 Status. 0: No rmal 1: Overflow. This bit is set if overflow had ever occurred. Write 1 to clear it. 0 R EQ Band-0 Status. 0: No rmal 1: Overflow. This bit is set if overflow had ever occurred. Write 1 to clear it. nWrite to EQ coefficient-{a1,a1,Ho} will be ignored when specific control bit is enabled, it means modify individual EQ coefficients is forbidden when EQ is working.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 27

6.5.21 Index-21h EQ PCM Digital Volume Control

Default: 007Fh Bit Type Function 15 R/W Mute Control. 0: Turn on 1: Mute, force data to zero. (-∞ dB) 14:7 Reserved 6:0 R/W 7-bit Volume Ratio, EQVR[7:0] The multiplier ratio is EQVR[7:0]/128. (1/128 ~ 1) nIf 7-bit volume ratio is 7Fh, it means the multiplier is 1 (0dB).

6.5.22 Index-22h EQ MIC ADC Digital Volume Control

Default: 007Fh Bit Type Function 15 R/W Mute Control. 0: Turn on 1: Mute, force data to zero. (-∞ dB) 14:7 Reserved 6:0 R/W 7-bit Volume Ratio, EQMICVR[7:0] The multiplier ratio is EQMICVR[7:0]/128. (1/128 ~ 1) nIf 7-bit volume ratio is 7Fh, it means the multiplier is 1 (0dB).

Two-Channel AC’97 2.3 Audio Codec Rev1.3 28 7. Electrical Characteristics

7.1 DC Characteristics

7.1.1 Absolute Maximum Ratings

Parameter Symbol Minimum Typical Maximum Units Power Supplies Digital Analog DVDD AVDD 3.0 3.0 3.3 5.0 3.6 5.5 V V Operating Ambient Temperature Ta 0 - +70 oC Storage Temperature Ts +125 oC

7.1.2 Threshold Hold Voltage

Dvdd= 3.3V±5%, Tambient=250C, with 50pF external load. Parameter Symbol Minimum Typical Maximum Units Input voltage range V in -0.30 - Dvdd+0.30 V Low level input voltage (AC-LINK, XTAL-IN/OUT) VIL - - 0.50*Dvdd V Low level input voltage (SCK,SDA) VIL - - 1.0 V Low level input voltage (JD1, JD2) VIL - - 2.0 V High level input voltage (AC-LINK, XTAL-IN/OUT) VIH 0.5*DVdd - - V High level input voltage (SCK, SDA) VIH 2.0 - - V High level input voltage (JD1, JD2) VIH 2.0 - V High level output voltage V OH 0.9DVdd - V Low level output voltage V OL - - 0.1DVdd V Input leakage current - -10 - 10 µA Output leakage current (Hi-Z) - -10 - 10 µA Output buffer drive current - - 5 - mA Internal pull up resistance - 30k 50k 100k Ω

7.1.3 Digital Filter Characteristics

Filter Symbol Minimum Typical Maximum Units ADC Lowpass Filter Passband 10 - 20.0 KHz Stopband 28.8 KHz Stopband Rejection -76.0 dB Passband Frequency Response +- 0.20 dB DAC Lowpass Filter Passband 10 - 20.0 KHz Stopband 28.8 KHz Stopband Rejection -78.5 dB Passband Frequency Response +- 0.20 dB

Two-Channel AC’97 2.3 Audio Codec Rev1.3 29

7.1.4 S/PDIF output Characteristics

Dvdd= 3.3V, Tambient=250C, with 75Ω external load. Parameter Symbol Minimum Typical Maximum Units High level output voltage V OH 3.0 3.3 V Low level output voltage V OL - 0 0.5 V

7.2 AC Timing Characteristics

7.2.1 Cold Reset

Parameter Symbol Minimum Typical Maximum Units RESET# active low pulse width T rst_low 1.0 - - µs RESET# inactive to BIT_CLK Startup delay T rst2clk 162.8 - - ns Cold reset timing diagram

7.2.2 Warm Reset

Parameter Symbol Minimum Typical Maximum Units SYNC active high pulse width T sync_high 1.0 - - µs SYNC inactive to BIT_CLK Startup delay Tsync2clk 162.8 - - ns Warm reset timing diagram

7.2.3 AC-Link Clocks

Parameter Symbol Minimum Typical Maximum Units BIT_CLK frequency - 12.288 - MHz BIT_CLK period T clk_period - 81.4 - ns BIT_CLK output jitter - - 750 ps BIT_CLK high pulse width (note 2) T clk_high 36 40.7 45 ns BIT_CLK low pulse width (note 2) T clk_low 36 40.7 45 ns SYNC frequency - 48.0 - KHz SYNC period T sync_period - 20.8 - µs SYNC high pulse width T sync_high - 1.3 - µs SYNC low pulse width T sync_low - 19.5 - µs Note 1: Worse case duty cycle restricted to 45/55.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 30 BIT_CLK and SYNC timing diagram

7.2.4 Data Output and Input Timing

Parameter Symbol Minimum Typical Maximum Units Output Valid Delay from rising edge of BIT_CLK tco - - 15 ns Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Note 2: 50pF external load Parameter Symbol Minimum Typical Maximum Units Input Setup to falling edge of BIT_CLK t setup 10 - - ns Input Hold from falling edge of BIT_CLK thold 10 - - ns Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Parameter Symbol Minimum Typical Maximum Units BIT_CLK combined rise or fall plus flight time - - 7 ns SDATA combined rise or fall plus flight time - - 7 ns Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes. Data Output and Input timing diagram

7.2.5 Signal Rise and Fall Timing

Parameter Symbol Minimum Typical Maximum Units BIT_CLK rise time Trise clk - - 6 ns BIT_CLK fall time Tfall clk - - 6 ns SYNC rise time Trise sync - - 6 ns SYNC fall time Tfall sync - - 6 ns SDATA_IN rise time Trise din - - 6 ns SDATA_IN fall time Tfall din - - 6 ns SDATA_OUT rise time Trise dout - - 6 ns SDATA_OUT fall time Tfall dout - - 6 ns Note 1: 75pF external load (50 pF in AC’97 rev2.1) Note 2: rise is from 10% to 90% of Vdd (V ol to Voh) Note 3: fall is from 90% to 10% of Vdd (Voh to Vol)

Two-Channel AC’97 2.3 Audio Codec Rev1.3 31 Signal Rise and Fall timing diagram

7.2.6 AC-Link Low Power Mode Timing

Parameter Symbol Minimum Typical Maximum Units End of slot 2 to BIT_CLK, SDATA_IN low Ts2_pdown - - 1.0 µs AC-Link low power mode timing diagram

7.2.7 ATE Test Mode

To meet AC’97 rev2.3 specifications, EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in test mode. Parameter Symbol Minimum Typical Maximum Units Setup to trailing edge of RESET# (also applies to SYNC) Tsetup2rst 15.0 - - ns Rising edge of RESET# to Hi-Z delay Toff - - 25.0 ns ATE test mode timing diagram

Two-Channel AC’97 2.3 Audio Codec Rev1.3 32

7.2.8 AC-Link IO Pin Capacitance and Loading

Output Pin 1 CODEC 2 CODEC 3 CODEC 4 CODEC BIT_CLK (must support ≥ 2 CODECs) 55pF 62.5pF 75pF 85pF SDATA_IN 47.5pF 55pF 60pF 62.5pF

7.2.9 SPDIF Output

SPDIF_OUT Minimum Typical Maximum Units Rise time/fall time 0 10 % Duty cycle 45 55 % T(h) T(l) T(r) T(f) 90% 50% 10% Notes: Rise time = 100 * T(r)/ (T(l)+ T(h))% Fall time = 100 * T(f)/ (T(l)+ T(h))% Duty cycle = 100 * T(h)/ (T(l)+ T(h))%

Two-Channel AC’97 2.3 Audio Codec Rev1.3 33 8. Analog Performance Characteristics Standard test conditions: Tambient=250C, Dvdd=3.3V ±5%,Avdd=5.0V±5% 1KHz input sine wa ve; Sampling frequency=48KHz; 0dB=1Vrms 10K Ω/50pF load; Test bench Characterization BW: 10Hz~22KHz 0dB attenuation; tone and 3D disabled Parameter Minimum Typical Maximum Units Full scale input voltage: Line inputs (Mixers) Line inputs (A/D) Mic input (0 dB) Mic input (20 dB boost) 1.6 1.0 1.6 0.16 Vrms Full scale output voltage LINE-OUT HP-OUT 1.25 1.25 Vrms Vrms Analog to Analog S/N: CD to LINE-OUT Other to LINE-OUT 100 100 dB Analog frequency response 10 - 22,000 Hz S/N (A-weighted): D/A A/D 100 dB Total Harmonic Distortion: D/A A / D -92 -86 dB D/A & A/D frequency response 20 - 20,000 Hz Transition Band 20,000 - 28,800 Hz Stop Band 28,800 - ∞ Hz Stop Band Rejection -75 - - dB Out-of-Band Rejection - -70 - dB Group delay - - 1 ms Power Supply Rejection - -40 - dB MIC Boost Gain 6 20 30 dB Master Volume (LINE- / HP-OUT): 64 step Step Size Attenuation Control Range 1.5 -94.5 dB dB Master Volume (MONO-OUT): 32 step Step Size Attenuation Control Range 1.5 -46.5 dB dB PC Beep Volume 16 steps: Step Size Attenuation Control Range 3.0 -45 dB dB Analog Mixer Volume 32 steps: Step Size Gain Control Range -34.5 1.5 +12 dB dB Record Gain 16 steps: Step Size Gain Control Range 1.5 +22.5 dB dB DC Volume Control: 32 step Gain Control Range 0 dB DC voltage Mute DC voltage 4.7 -43 0.1 dB V V Input impedance (gain = 0dB, mixer = off) LINE-IN, CD-IN, AUX-IN, MIC1 / MIC2 PCBEEP, PHONE KΩ KΩ cont…

Two-Channel AC’97 2.3 Audio Codec Rev1.3 34 Output Impedance LINE-OUT HP-OUT MONO-OUT 200 500 Ω Ω Ω Amplifier Maximum Output Power @20Ω load mW Power Supply Current VA=5.0V VA=3.3V VD=3.3V mA mA mA Power Down Current VA=5.0V / 3.3V VD=3.3V 1000 700 uA uA Vrefout/Vrefout2/Vrefout3 - 2.50 4.0 V Vrefout Drive Current - 5 - mA

Two-Channel AC’97 2.3 Audio Codec Rev1.3 35 9. Design Suggestions

9.1 Clocking

The clock source is decided by XTLSEL latched from pin-46 after power-on reset. The clock source of different configuration is listed below: Configuration Operation & ID0 Pin-46(XTLSEL) ID0 BIT-CLK Clock source NC 0 (Primary) Output 12.288MHz Crystal or ext. 24.576MHz is attached at XTL-IN Low 0 (Primary) Output 12.288MHz Crystal or ext. 14.318MHz is attached at XTL-IN NC 0 (Primary) Input 12.288M input at BIT-CLKn *Low: Pulled low by a 0 ohm resistor. NC: Not connect or pulled high. *Pin-46is internally pulled high by a weak resistor. nAccording to AC’97 ver 2.3, the primary mode while RESET# is asserted, if a clock is present at BIT-CLK pin for at least 5 cycles before RESET# is de-asserted, ALC250 is a consumer of BITCLK. ALC250 should use external 12.288MHz BITCLK as its clock source.

9.2 AC-Link

When the ALC250 receives serial data from the AC97 controller, it samples SDAT A_OUT on the falling edge of BIT_CLK. When the ALC250 sends serial data to the AC97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK. The ALC250 will return any uninstalled bits or registers with 0 for read operations. The ALC250 also stuffs the unimplemented slot or bit with 0 in SDATA_IN. Note that AC-LINK is MSB-justified. Refer to “Audio CODEC ’97 Component Specification Revision 2.3.” for details. 0 1 2 3 4 5 6 7 8 9 10 11 12 TAG CMD DATA PCM L PCMR SPDIF L SPDIF R TAG ADD R DATA PCM L PCMR Default ALC250 Slot Arrangement – CODEC ID = 00 (ALC250 supports only primary mode)

9.3 Reset

There are 3 types of reset operations: Cold, Warm and Register. Reset Type Trigger condition CODEC response Cold Assert RESET# for a specified period Reset all hardware logic and all registers to its default value. Register Write register indexed 00h Reset all registers to its default value. Warm Driven SYNC high for specified period without BIT_CLK Reactivates AC-LINK, no change to register values. The AC97 controller should drive SYNC and SDATA_OUT low duri ng the period of RESET# assertion to guarantee that the ALC250 has reset successfully. Slot# SYNC SDATA-OUT SDATA-IN

Two-Channel AC’97 2.3 Audio Codec Rev1.3 36

9.4 CD Input

It is important to pay attention to differential CD input. Below is an example of differential CD input. Example of differential CD input

9.5 Odd Addressed Register Access

The ALC250 will return “0000h” when odd-addressed and unimplemented registers are read.

9.6 Power-down Mode

It is important to pay special attention to the power down control register (index 26h), especially PR4 (powerdown AC-link).

9.7 Test Mode

To provide compatibility with AC’97 rev2.2, the ALC250 will float its digital output pins in both ATE and Vendor-Specific test modes. Please refer to AC’97 rev2.2 section 9.2 for a detailed description of the test modes.

9.7.1 ATE In Circuit Test Mode

SDATA_OUT is sampled high at the trailing edge of RESET# . In this mode, the ALC250 will drive BIT_CLK, SDATA_IN, EAPD and SPDIFO to high impedance.

9.7.2 Vendor Specific Test Mode

The Vendor Specific Test mode is no longer supported.

Two-Channel AC’97 2.3 Audio Codec Rev1.3 37

9.8 DC Voltage Volume Control

The ALC250 has a 32-step internal volume control that is controlled by the DC voltage applied the ‘DC Vol’ pin (pin-32). The volume control input range is from GND to AVDD, to attenuate the master volume (real MX02), headphone volume (real MX04) and mono-out volume (real MX06). A higher DC voltage means more attenuation related to output volume. The table below shows the relation between input DC voltage and the 5-bit volume code. Input DC Voltage Volume Code Note Input DC Voltage Volume Code Note 95%=< DC 1F DCMute=1 47%< DC <= 50% F 92%< DC <= 95% 1E DCMute=0 44%< DC <= 47% E 50%< DC <= 53% 10 DC <= 5% 0 DCMute=0 Input DC Voltage is ratio of AVDD (+5VA).

• This 5-bit volume code adds extra attenuation for master volume and headphone volume, the absolute maximum volume is determined by MX02, MX04 and MX06. Once the sum of MX value and volume code exceeds 3Fh, the real MX value is 3Fh. Example 1: (Normal case) MX02=0002h, MX04=0300h, MX06=0001h, Volume Code=2h, then Master Volume=0204h, Headphone Volume=0502h, Mono-Out=0003h Example 2: (The sum exceeds 3Fh for MX02/MX04, 1Fh for MX06) MX02=2F2Fh, MX04=2E2Eh, MX06=0002h, Volume Code=1Eh, then Master Volume=3F3Fh, real Headphone Volume=3D3Dh, Mono-Out=001Fh Example 3: (Volume code is 1Fh, DCMute=1, real MXs should be muted) MX02=0000h, MX04=2020h, MX06=0010h, Volume Code=1Fh, then Master Volume=9F1Fh, Headphone Volume=BF3Fh, Mono-Out=801Fh

Two-Channel AC’97 2.3 Audio Codec Rev1.3 38

9.9 POWER OFF CD Function

The ‘POWER OFF CD’ function describes a state which, after the system has been shut down and a +5V analog power is supplied at VAUX(pin-34), the ALC250 will turn on the CD-IN op and output amplifier. It is possible to design a system which will save op-amp circuitry and bypass CD output directly to the speaker. The figure below indicates the system application circuitry to support the ‘POWER OFF CD’ function. The operation mode is defined by +3.3VCC and +5Vaux. +3.3VCC +5Vaux Operation Mode No (0) No (0) Shut Down No (0) Yes (1) Power Off CD Yes (1) No (0) Normal (+5Vaudio must be on) Yes (1) Yes (1) Normal (+5Vaudio must be on) +3.3VDD +5VA +5Vstandby 1N5817M/CYL 1N5817M/CYL 0.1u0.1u 10u 10u ALC250 VDD VDD AVDD AVDD GND GND AGND AGND XTL-IN XTL-OUT SDOUT BITCLK SDIN SYNC RESET# PC-BEEP PHONE AUX-L AUX-R JD2 JD1 CD-L CD-R CD-GND MIC1 MIC2 LINE-L LINE-R VREF VREFOUT AFILT1 AFILT2 NC DCVOL VREFOUT2 VAUX LINEOUT-L LINEOUT-R MONO-OUT/VREFOUT3 HPOUT-L NC HPOUT-R GPIO0 GPIO1 NC XTLSEL SPDIFI/EAPD SPDIFO1u POWER OFF CD Circuitry

Two-Channel AC’97 2.3 Audio Codec Rev1.3 39 10. Application Circuits Filter Connection Schematic +12V +3.3VDD +5VA +5VA +5VAUX +5VA +3.3VDD +3.3VDD +3.3VDD +5VA +5VDD AC97-SDOUT AC97-SDIN AC97-RESET# Audio-From-Modem EXT 14.318MHz AC97-SYNC AC97-BCLK Pown Down Ext. AMP LINE-OUT-L to Ext.AMP LINE-OUT-R to Ext.AMP SCK SDA Signal-From-PCSPK LINE-OUT-L MIC1-IN LINE-IN-R MIC2-IN LINE-OUT-R LINE-IN-L HP-OUT-L HP-OUT-R JD2 AUX-R AUX-L JD1SDA SCK GPIO0 GPIO1 VREFOUT2 VREFOUT3 SPDIF-OUT SPDIF-OUT VREFOUT R66 0@250 C31 1u@202C67 1u@202 R33 47K@250 +C1 10u C11 0.1u R65 0@250 C43 10u C44 0.1u R35 0@250 L3 FERB Vol-Mute 10u Vol-Down R53 4.7K CD-IN Header1 C20 0.1u +C19 10u +C26 100u 24.576MHz C45 22P C12A1 1u +C23 100u C12 1u C5 1u C41 1u C46 22P R1 0 R3 0 DVDD1 XTL-IN XTL-OUT DVSS1 SDATA-OUT BIT-CLK DVSS2 SDATA-IN DVDD2 SYNC RESET# PC-BEEP PHONE AUX-L AUX-R JD2 JD1 CD-L CD-GND CD-R MIC1 MIC2 LINE-IN-L LINE-IN-RAVDD1 AVSS1 VREF VREFOUT AFILT1 AFILT2 NC DCVOL VREFOUT2 VAUX LINE-OUT-L LINE-OUT-RMONO-O AVDD2 HP-OUT-L NC HP-OUT-R AVSS2 GPIO0/SCK GPIO1/SDA ID0#/JD0 XTLSEL SPDIFI/EAPD SPDIFO 0@EXT-14.318M R12A1 R12B1 10K R7 0 C28 1u C14 1000P C12B1 100P R2 0 R55@203/250 6.8k~8.2k C10 1000P C21 1u C24 1u C25 1u C27 1u C22 1u R64 47K@250 R63 47K@250 C42 0.1u R10 +C39 100u@203/250 R34 0@250 +C37 100u@203/250 R70 0@203/250 R71 0@202 Vol-Up R55 0@203 R56 0@203 R41 0@203/250/202 C16 R67 VAR 10K R4 0@EXT-14.318M R68 0@203/250 R69 0@203/250 + C8 10u C15 10u 10u U1 LM7805CT/200mA INOUT GND C30 1u TOTX178 IN VCC GND N.CN.C R54 4.7K S/PDIF OUTPUT C38 0.01u C50 22P C32 0.1u C40 100P R5 100

220 AGND

Tied at one point only under the codec or near the codec DGNDCrystal Saving: R8,R4=0; Y1,C45,C46=X (EXT-14.288MHz clock) R8,R4=X; Y1=24.576M, C45,C46=22p (24.576MHz crystal) ALC250/203/202 GPIO Volume Contro (ALC203 only) EQualizer Control by uP (ALC250 only) EQualizer Control by uP (ALC250 only) DC Volume Control (ALC202/203/250) For UAJ (ALC203/250) For Power Off CD For UAJ (ALC203/250) Optical Transmitter (Coaxial)

Two-Channel AC’97 2.3 Audio Codec Rev1.3 40 Internal MIC-INMIC1-IN MIC2-IN HP-OUT-R VREFOUT HP-OUT-L JD1 Microphone Input R17 0 R15 0@203/250, Stereo MIC C52 100P C53 100P L13 FERB L15 FERB R13 4.7K@203/250, Stereo MIC Headphone Out C61 100P C60 100P R56 10K@ALC250 C72 3.3u@ALC250 FERB L9 FERB R59 22K R60 22K R12 2.2K@203/250, Mono MIC Jack Detect to bypass EQ while headphone is plugged in (ALC250 only) 4.7K@203/250,Stereo MIC Standard Jack Connection (ALC250/203/202) Jack Connection - Standard Connection Internal MIC-IN JD1 HP-OUT-L HP-OUT-R JD2 VREFOUT3-UAJ1 VREFOUT2 AUX-L AUX-R R50 10K + C71 3.3u UAJ2 5L19 FERB L18 FERB 1N4148 C59 100P C58 100P 1N4148 R51 22K + C66 3.3u L16 FERB R32 10K L17 FERB UAJ1 C62 100P C63 100P R31 22K Universal Audio Jack(UAJ): (ALC250/203) Jack Connection -(Universal Audio Jack, UAJ)

Two-Channel AC’97 2.3 Audio Codec Rev1.3 41 11. Mechanical Dimensions MILLIMETER INCH SYMBOL MIN. TYPICAL MAX. MIN. TYPICAL MAX A 1.60 0.063 A1 0.05 0.15 0.002 0.006 c 0.09 0.20 0.004 0.008 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC D2 5.50 0.217 E 9.00 BSC 0.354 BSC E1 7.00BSC 0.276 BSC E2 5.50 0.217 e 0.50 BSC 0.0197 BSC TH 0 o 3.5 o 7 o 0 o 3.5 o 7 o L1 1.00 0.0393 TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm LEADFRAME MATERIAL DOC. NO. APPROVE VERSION 02 DWG NO. PKGC-065 CHECK DATE REALTEK SEMICONDUCTOR CORP. L

Two-Channel AC’97 2.3 Audio Codec Rev1.3 43 12. Ordering Information Part Number Package Status ALC250 Standard product. LQFP-48 Production ALC250-LF ALC250 with Lead (Pb)-Free package Production Note: 1. See page 3 for lead (Pb)-free package and version identification. 2. Above parts are tested under AVDD =5.0V . If customers have lower AVDD request, please contact Realtek sales representatives or agents. Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw