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(PN: ALC1150-CG) 7.1+2 CHANNEL HD AUDIO CODEC WITH CONTENT PROTECTION DATASHEET Rev. 1.0
01 July 2013
Track ID: JATR-8275-15 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com
7.1+2 Channel HD Audio Codec with Content Protection iii Track ID: JATR-8275-15 Rev. 1.0 COPYRIGHT ©2013 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and soft ware engineer’s general information on the Realtek ALC1150 ICs. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary 1.0 2013/07/01 First Release
7.1+2 Channel HD Audio Codec with Content Protection iv Track ID: JATR-8275-15 Rev. 1.0 Table of Contents
7.1+2 Channel HD Audio Codec with Content Protection v Track ID: JATR-8275-15 Rev. 1.0 8.28. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 57 8.43. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR [7:0]) 66
7.1+2 Channel HD Audio Codec with Content Protection vi Track ID: JATR-8275-15 Rev. 1.0
TABLE 76. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
7.1+2 Channel HD Audio Codec with Content Protection 1 Track ID: JATR-8275-15 Rev. 1.0 1. General Description The ALC1150 is a high-performance multi-channe l High Definition Audio Codec with Realtek proprietary lossless content protection technology that protects pre-reco rded content while still allowing full-rate audio enjoyment from DVD audio, Blu-ray DVD, or HD DVD discs. The ALC1150 provides ten DAC cha nnels that simultaneously support 7.1-channel sound playback, plus 2 channels of independent stereo sound output (mu ltiple streaming) through the front panel stereo outputs. Two stereo ADCs are integrated and can support a microphone array with Acoustic Echo Cancellation (AEC), Beam Forming (BF), and No ise Suppression (NS) technologies. The ALC1150 incorporates Realtek proprietary converter technology to achieve Front differential output 115dB Signal-to-Noise ratio (SNR) playback (DAC) qua lity and 104dB SNR recording (ADC) quality, and is designed for Windows Vista premium desktop and laptop systems. All analog I/O are input and output cap able, and headphone amplifiers are also integrated at three analog output ports (port-D/port-E/port-F). All analog I/Os can be re-tasked according to user definitions. Support for 16/20/24-bit SPDIF and I 2S (Master mode) output with up to 192kHz sample rate offers easy connection of PCs to consumer elec tronic products such as digital d ecoders and speakers. The ALC1150 also features secondary SPDIF-OUT output and converter to transpor t digital audio out put to a High Definition Media Interface (HDMI) transmitter. The ALC1150 supports host audio from the Intel chip sets, and also from any other HDA compatible audio controller. With various software utilitie s like environment sound emulation, multiple-band and independent software equalizer, dynamic range compressor and expander, optional Dolby PCEE program, SRS TruSurround HD, SRS Premium Sound, Fortemedia SAM, Creative Host Audio, Synopsys Sonic Focus, DTS Surround Sensation | UltraPC, and DTS C onnect licenses, the ALC1150 offers the highest sound quality, providing an excellent entertainment package and game experience for PC users.
7.1+2 Channel HD Audio Codec with Content Protection 2 Track ID: JATR-8275-15 Rev. 1.0 2. Features 2.1. Hardware Features Front-DAC with 115/110dB SNR (A-weighting, Differential/Single-End Output), ADC09h with 104dB SNR (A-weighting) DACs (except Front-DAC) with 96dB SNR (A-weighting), ADC08h with 93dB SNR (A-weighting) Ten DAC channels support 16/20/24-bit PCM format for 7.1 channel sound playback, plus 2 channels of concurrent independent stereo sound output (multiple streaming) through the front panel output Two stereo ADCs support 16/20/24-bit PCM format, multiple stereo recording All DACs supports 44.1k/48k/96k/192kHz sample rate All ADCs supports 44.1k/48k/96k/192kHz sample rate Primary 16/20/24-bit SPDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample rate Secondary 16/20/24-bit SPDIF-OUT supports 32k/44.1k/48k/88.2k/96k/192kHz sample rate I2S-OUT supports 44.1k/48k/96k/192kHz sample rate up to 24bits and master mode only. All analog jacks (port-A to port-H) are stereo input and output re-tasking Port-D/E/F built-in headphone amplifiers Port-B/C/E/F with software selectable boost gain (+10/+20/+30dB) for analog microphone input Software selectable 2.3V/3.0V/3.8V VREFOUT Up to four channels of microphone array input are supported for AEC/BF applications Three jack detection pins; each designed to detect up to 4 jacks Supports legacy analog mixer architecture Up to two GPIOs (General Purpose Input and Output) for customized applications. GPIO0 and GPIO1 share pin with SPDIF-OUT2 and I2S-SDO Supports anti-pop mode when analog power LDO-IN is on and digital power is off Content Protection for Full Rate lossless DVD Audio, Blu-ray DVD, and HD-DVD audio content playback (with selected versions of WinDVD/PowerDVD/TMT) 0.75dB per step output volume and input volume control Supports 3.3V digital core power, 1.5V or 3.3V digital I/O power for HD Audio link, and 5.0V analog power
7.1+2 Channel HD Audio Codec with Content Protection 3 Track ID: JATR-8275-15 Rev. 1.0 Intel low power ECR compliant and power status control for each analog/digital converter and pin widget Built-in analog LDO 48-pin QFN ‘Green’ package 2.2. Software Features Meets Microsoft WLP 3.x and future WLP audio requirements WaveRT-based audio function driver for Windows Vista and Windows 7 Direct Sound 3D™ compatible I3DL2 compatible 7.1+2 channel multi-streaming enables concurrent gaming/VoIP Emulation of 26 sound environments to enhance gaming experience Multiband software equalizer and tools provided Voice Cancellation and Key Shifting effect Dynamic range control (expander, compressor, and limiter) with adjustable parameters Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice applications Smart multiple streaming operation HDMI audio driver for AMD platform Optional Dolby PCEE program, SRS TruSurround HD, SRS Premium Sound, Fortemedia SAM, Creative Host Audio, Synopsys Sonic Focus, DTS Surround Sensation | UltraPC, and DTS Connect licenses 3. System Applications Desktop multimedia PCs Notebook PCs
Figure 1. Block Diagram
Pin Complex widgets NID=14h~1Bh are re-tasking IOs. Figure 2. Analog Input/Output Unit
Figure 3. Pin Assignments shown in the location marked ‘V’ and ‘S’.
Table 1. Pin Descriptions
7.1+2 Channel HD Audio Codec with Content Protection 8 Track ID: JATR-8275-15 Rev. 1.0 Name Type Pin Description Characteristic Definition LINE1-R IO 21 Analog Input and Output with Multiple Function (Right) Analog I/O (PORT-C-R), default 1st line input. Recommended to be line level input at rear panel MIC1- VREFO-L O 22 Bias V oltage for MIC1 (Port-B) Analog Output: 2.3V/3.0V/3.8V reference voltage MIC1- VREFO-R O 23 Secondary Bias V oltage for MIC1 (Port-B) Analog Output: 2.3V/3.0V/3.8V reference voltage LDO-IN P 24 Built-In LDO Input VDD (5V) Input LDO-OUT1 - 25 Built-In LDO Output for Mixer & Amp Needs 10µF capacitor to analog ground, and short to Pin43 A VSS1 G 26 Analog Ground for Mixer & Amp Analog GND VREF - 27 0.5×LDO-OUT1 Reference V oltage 10µf capacitor to analog ground MIC2-L IO 28 Analog Input and Output with Multiple Function (Left) Analog I/O (PORT-F-L), default 2 nd mic input. Recommended to be re-tasking port at front panel MIC2-R IO 29 Analog Input and Output with Multiple Function (Right) Analog I/O (PORT-F-R), default 2 nd mic input. Recommended to be re-tasking port at front panel SURR-L IO 30 Analog Input and Output (Left) Analog I/O (PORT-A-L), default surround channel. SURR-R IO 31 Analog Input and Output (Right) Analog I/O (PORT-A-R), default surround channel. CENTER IO 32 Analog Input and Output (Left) Analog I/O (PORT-G-L), default center channel. LFE IO 33 Analog Input and Output (Right) Analog I/O (PORT-G-R), default LFE channel. SIDE-L IO 34 Analog Input and Output (Left) Analog I/O (PORT-H-L), default side channel. SIDE-R IO 35 Analog Input and Output (Right) Analog I/O (PORT-H-R), default side channel. LINE2-L IO 36 Analog Input and Output with Multiple Function (Left) Analog I/O (PORT-E-L), default 2 nd line input. Recommended to be re-tasking port at front panel LINE2-R IO 37 Analog Input and Output with Multiple Function (Right) Analog I/O (PORT-E-R), default 2 nd line input. Recommended to be re-tasking port at front panel FRONT-L- O 38 Negative Line Out Left Analog differential output (PORT-D-L-) FRONT-L+ IO 39 Positive Line Out Left Analog Differential or Single-End output (PORT-D-L+) FRONT-R+ IO 40 Positive Line Out Right Analog Differential or Single-End output (PORT-D-R+) FRONT-R- O 41 Negative Line Out Right Analog differential output (PORT-D-R-) A VSS2 G 42 Analog Ground for DAC & ADC Analog GND LDO-OUT2 - 43 Analog Power for DAC and ADC Needs 10µF capacitor to analog ground, and short to Pin25 VRP - 44 Internal V oltage for DAC, ADC 100µF Polar Capacitor to Analog GND. LINE2- VREFO O 45 Bias V oltage for LINE2 (Port-E) Analog Output: 2.3V/3.0V/3.8V reference voltage PIN46- VREFO O 46 Bias V oltage Analog Output: 2.3V/3.0V/3.8V reference voltage
7.1+2 Channel HD Audio Codec with Content Protection 9 Track ID: JATR-8275-15 Rev. 1.0 Name Type Pin Description Characteristic Definition EAPD/ I2S-LRCLK O 47 External Amplifier Power Down/ I2S Output Serial Audio Data Master Clock Output Æ VOL <0.1×DVDD, VOH >0.9×DVDD 6mA@75Ω Output driving SPDIF-OUT O 48 Primary SPDIF Out Digital Output: V OL <0.1×DVDD, VOH >0.9×DVDD 6mA@75Ω Output driving Total: 48 Pins Note 1: Pins 2 and 4 have multiple functions. Their default operation is as GPIOs. They function as secondary SPDIF-OUT when the configuration register of the SPDIF-OUT2 pin widget (node ID 11h) is enabled, and exclusively function as I2S-SDO pins when the verb table of the I2S-OUT function is enabled. Note 2: If Pin38~41 work with differential output, input (retasking) function is not supported. Note 3: I2S-OUT (pin4/7/12/47) only function as Front-Out or LINE2 port and dedicated output function.
- High Definition Audio Link Protocol
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol. Figure 4. HDA Link Protocol
Table 2. Link Signal Definitions controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported. Table 3. HDA Signal Definitions SDI Codec/Controller Input/Output Serial Data Input from Codec. Figure 5. Bit Timing
the data stream is always carried on SDO0, the second bit on SDO1 and so forth. is always transmitted on SDO0, and copied on SDO1. Figure 9. Striped Stream on Multiple SDOs
Figure 12. Codec Transmits Data Over Multiple SDIs sample rate, independent of any other stream. sample rates based on multiples or sub-multiples of one of the two base rates. of variable rates based on 48kHz. blocks are transmitted every 160 frames.
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence AND interleave n empty frames. AND interleave an empty frame between non-empty frames (Table 6, page 18). Table 4. Defined Sample Rate and Transmission Rate Table 5. 48kHz Variable Rate of Delivery Timing N: No sample block in a frame. Y: One sample block in a frame. x: X sample blocks in a frame.
Table 6. 44.1kHz Variable Rate of Delivery Timing
7.1+2 Channel HD Audio Codec with Content Protection 19 Track ID: JATR-8275-15 Rev. 1.0 7.3. Reset and Initialization There are two types of reset within an HDA link:
- Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
- Codec Reset. Generated by software directing a command to reset a specific codec back to its default state An initialization sequence is requested after any of the following three events:
- Link Reset
- Codec Reset
- Codec changes its power state (for example, hot docking a codec to an HDA system) 7.3.1. Link Reset A link reset may be caused by 3 events: 1. The HDA controller asserts RST# for any reason (power up, or PCI reset) 2. Software initiates a link reset via the ‘CRST’ b it in the Global Control Register (GCR) of the HDA controller 3. Software initiates power management sequences. Figure 13, shows the ‘Link Reset’ timing including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v) Enter ‘Link Reset’: n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a link reset o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
4 BCLK 4 BCLK
Figure 13. Link Reset Timing
Figure 14. Codec Initialization Sequence controls parameters in the codec. Table 7. 40-Bit Commands in 4-Bit Verb Format Table 8. 40-Bit Commands in 12-Bit Verb Format
Table 9. Verbs Supported by the ALC1150 (Y=Supported) *1: The ALC1150 does not support Modem Function, HDMI Function, V endor Defined Groups, and Power Widgets.
Table 10. Parameters in the ALC1150 (Y=Supported) *1: The ALC1150 does not support Modem Function, HDMI Function, V endor Defined Groups, and Power Widgets.
software, opaque to the controller. Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications. Table 11. Solicited Response Format Table 12. Unsolicited Response Format ‘Valid’ bit to indicate the response is ‘Ready’. Bit 34 is set to indicate that an unsolicited response was sent. (NID=01h). Software may have various power states depending on system configuration. Table 14 indicates those nodes that support power management. Table 13. System Power State Definitions D0 All Power On. Individual DACs and ADCs can be powered up or down as required. D1 All Converters (DACs and ADCs) are Powered Down . State maintained, analog reference stays up. D2 Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down. Codec stops PLL. State maintained. Jack-detection and GPI are powered down. D3 (Hot) Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down. Codec stops PLL. State maintained. Jack-detection/GPI work. D3 (Cold) Power is Still Supplied. All amplifiers and converters (DACs and ADCs) are powered down. Codec stops PLL. State maintained. Jack-detection/GPI work when internal OSC powers up.
Table 14. Power Controls in NID 01h Note 2: Jack detection with unsolicited response is issued when a Link Reset occurs in D3 state. Table 15. Powered Down Conditions LINK Response Powered Down Internal Clock is Stopped. maintained if DVDD is supplied. FRONT DAC Powered Down Analog Block and Digital Filter are Powered Down. SURR DAC Powered Down Analog Block and Digital Filter are Powered Down. CEN/LFE DAC Powered Down Analog Block and Digital Filter are Powered Down. SIDESURR DAC Powered Down Analog Block and Digital Filter are Powered Down. FOUT DAC Powered Down Analog Block and Digital Filter are Powered Down. LINE ADC Powered Down Analog Block and Digital Filter are Powered Down. MIX ADC Powered Down Analog Block and Digital Filter are Powered Down. Headphone Driver Powered Down All Headphone Drivers are Powered Down. Mixers Powered Down All Internal Mixer Widgets are Powered Down. The DC reference and VREFOUTx at individual pin complexes are still alive.
- Supported Verbs and Parameters
is not supported by the addressed widget, it will respond with 32 bits of ‘0’. codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget. page 21, for detailed information about supported parameters.. Table 16. Verb – Get Parameters (Verb ID=F00h) Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’. Table 17. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) 31:16 Vendor ID=10ECh (Realtek’s PCI Vendor ID). Note: The Root Node (NID=00h) supports this parameter. Table 18. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) 31:24 Reserved. Read as 0’s. 15:8 Revision ID. The vendor’s revision number. 00h is for the first silicon version (A version), 01h is for the second version (B version), etc. 7:0 Stepping ID. The vendor’s stepping number within the given Revision ID. Note: The Root Node (NID=00h in the ALC1150) supports this parameter.
associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node. Table 19. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) 31:24 Reserved. Read as 0’s. The starting node number in the sequential widgets. For a root node, the total number of function groups in the root node. For a function group, the total number of widget nodes in the function group. Table 20. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) 7:0 Function Group Type. Read as 01h. Note: The Audio Function Group (NID=01h) supports this parameter.
Table 21. Parameter – Audio Function Capa bilities (Verb ID=F00h, Parameter ID=08h) 31:17 Reserved. Read as 0’s. 16 Beep Generator, Read as 1. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0’s. 11:8 Input Delay. Read as 0xF. 3:0 Output Delay. Read as 0xF. Note: The Audio Function Group (NID=01h) supports this parameter. Table 22. Parameter – Audio Widget Capa bilities (Verb ID=F00h, Parameter ID=09h) 31:24 Reserved. Read as 0’s. 19:16 Delay. Samples delayed between the HDA link and widgets. 15:11 Reserved. Read as 0’s. 8 ConnList. Connection List. 7 UnsolCap. Unsolicited Capable. 6 ProcWidget. Processing Widget. 3 AmpParOvr, AMP Param Override. 2 OutAmpPre. Out AMP Present.
parameters to provide supported formats if their ‘Format Override’ bit is set. Table 23. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) 31:21 Reserved. Read as 0’s. 20 B32. 32-bit audio format support. 19 B24. 24-bit audio format support. 18 B20. 20-bit audio format support. 17 B16. 16-bit audio format support. 16 B8. 24-bit audio format support. 15:12 Reserved. Read as 0’s. 11 R12. 384kHz (=8×48kHz) rate support. 10 R11. 192kHz (=4×48kHz) rate support. 8 R9. 96kHz (=2×48kHz) rate support. 7 R8. 88.2kHz (=2×44.1kHz) rate support. 4 R5. 32kHz (=2/3×48kHz) rate support. 2 R3. 16kHz (=1/3×48kHz) rate support. 0 R1. 8kHz (=1/6×48kHz) rate support.
have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table 24. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Note: Input converters and output converters support this parameter. The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget. Table 25. Parameter – Pin Capabilit ies (Verb ID=F00h, Parameter ID=0Ch) specified as a percentage of LDO-OUT1. 7 L-R Swap. Indicates the capability of swapping the left and right. 6 Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins. 5 Input Capable. ‘1’ indicates this pin complex supports input. 4 Output Capable. ‘1’ indicates this pin complex supports output. 3 Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone. 2 Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in. 1 Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement. ‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type. Note: Only Pin Complex widgets support this parameter.
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 26. Parameter – Amplifier Capabilities (V erb ID=F00h, Input Amplifier Parameter ID=0Dh) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. Indicates which step is 0dB. their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table 27. Parameter – Amplifier Capabilities (Ver b ID=F00h, Output Amplifier Parameter ID=12h) Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps. ‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 6:0 Offset. Indicates which step is 0dB.
Parameters in this node provide audio function widget connection information. Table 28. Parameter – Connect List Le ngth (Verb ID=F00h, Parameter ID=0Eh) input, and there is no Connection Select Control (not a MUX widget). Table 29. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) 31 Extended Power States Supported (EPSS).
Table 30. Parameter – Processing Capab ilities (Verb ID=F00h, Parameter ID=10h) 31:16 Reserved. Read as 0’s. 15:8 NumCoeff. Number of Coefficient. Table 31. Parameter – GPIO Capabilit ies (Verb ID=F00h, Parameter ID=11h) 31 GPIWake=0. The ALC1150 does not support GPIO wake up function. 30 GPIUnsol=1. The ALC1150 supports GPIO unsolicited response. 29:24 Reserved. Read as 0’s. 23:16 NumGPIs=00h. No GPI pin is supported. 15:8 NumGPOs=00h. No GPO pin is supported. 7:0 NumGPIOs=02h. Two GPIO pins are supported. Table 32. Parameter – Volume Knob Capa bilities (Verb ID=F00h, Parameter ID=13h) Note: The ALC1150 does not support the Volume Knob Capabilities parameter.
Table 33. Verb – Get Connection Select Control (Verb ID=F01h) 7:0 Connection Index Current Settings (Default Value is 00h). 31:0 Not Supported (Returns 00000000h). Table 34. Verb – Set Connection Select (Verb ID=701h) Table 35. Verb – Get Connection List Entry (Verb ID=F02h) 31:8 Connection List Entry (N+3), (N+2), and (N+1). 7:0 Connection List Entry (N). Returns 23h (Sum Widget) for N=0~3.
7.1+2 Channel HD Audio Codec with Content Protection 35 Track ID: JATR-8275-15 Rev. 1.0 Codec Response for NID=09h (MIX ADC) Bit Description 15:8 Connection List Entry (N+3), (N+2), and (N+1). Returns 000000h. 7:0 Connection List Entry (N). Returns 22h (Sum Widget) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Bh (Mixer) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 17h (Pin Complex – SIDESURR) for N=4~7. Returns 00h for N>7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 16h (Pin Complex – CEN/LFE) for N=4~7. Returns 00h for N>7. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 15h (Pin Complex – SURR) for N=4~7. Returns 00h for N>7. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 00h for N>7. Codec Response for NID=0Ch (Front Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 02h (Front DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Dh (Surround Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h.
7.1+2 Channel HD Audio Codec with Content Protection 36 Track ID: JATR-8275-15 Rev. 1.0 Codec Response for NID=0Dh (Surround Sum) Bit Description 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Eh (Cen/LFE Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 04h (Cen/LFE DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=0Fh (Side-Surr Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 05h (Front DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=26h (Fout Sum) Bit Description 31:24 Connection List Entry (N). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Bh (Mixer) for N=0~3. Returns 00h for N>3.
7.1+2 Channel HD Audio Codec with Content Protection 37 Track ID: JATR-8275-15 Rev. 1.0 Codec Response for NID=26h (Fout Sum) Bit Description 7:0 Connection List Entry (N). Returns 25h (Fout DAC) for N=0~3. Returns 00h for N>3. Codec Response for NID=14h (Port-D) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3. Returns 00h for N>3. Codec Response for NID=15h (Port-A) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for N>3. Codec Response for NID=16h (Port-G) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3.
7.1+2 Channel HD Audio Codec with Content Protection 38 Track ID: JATR-8275-15 Rev. 1.0 Codec Response for NID=17h (Port-H) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 0Fh (Sum Widget NID=0Fh) for N=0~3. Returns 00h for N>3. Codec Response for NID=18h~1Bh (Port-B/C/E/F) Bit Description 31:24 Connection List Entry (N+3). Returns 0Fh (Sum Widget NID=0Fh) for N=0~3. Returns 00h for n>3. 23:16 Connection List Entry (N+2). Returns 0Eh (Sum Widget NID=0Eh) for N=0~3. Returns 00h for N>3. 15:8 Connection List Entry (N+1). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 0Ch (Sum Widget NID=0Ch) for N=0~3. Returns 26h (Sum Widget NID=26h) for N=4~7. Returns 00h for N>7. Codec Response for NID=1Eh (Pin Widget: SPDIF-OUT) Bit Description 31:16 Connection List Entry (N+3) and (N+2). Returns 0000h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 06h (SPDIF-OUT converter) for N=0~3. Returns 00h for N>3.
7.1+2 Channel HD Audio Codec with Content Protection 39 Track ID: JATR-8275-15 Rev. 1.0 Codec Response for NID=11h (Pin Widget: SPDIF-OUT2) Bit Description 31:16 Connection List Entry (N+3) and (N+2). Returns 0000h. 15:8 Connection List Entry (N+1). Returns 00h. 7:0 Connection List Entry (N). Returns 10h (SPDIF-OUT2 converter) for N=0~3. Returns 00h for N>3. Codec Response for NID=22h (Sum Widget before ADC 09h) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 17h (Pin Complex-SIDESURR) for N=4~7. Returns 00h for N>7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 16h (Pin Complex – CEN/LFE) for N=4~7. Returns 00h for N>7. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 15h (Pin Complex – SURR) for N=4~7. Returns 00h for N>7. 7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 0Bh (Sum Widget) for N=8~11. Returns 00h for N>11. Codec Response for NID=23h (Sum Widget before ADC 08h) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex – LINE2) for N=0~3. Returns 17h (Pin Complex-SIDESURR) for N=4~7. Returns 00h for N>7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex – LINE1) for N=0~3. Returns 16h (Pin Complex – CEN/LFE) for N=4~7. Returns 00h for N>7. 15:8 Connection List Entry (N+1). Returns 19h (Pin Complex – MIC2) for N=0~3. Returns 15h (Pin Complex – SURR) for N=4~7. Returns 00h for N>7.
7:0 Connection List Entry (N). Returns 18h (Pin Complex – MIC1) for N=0~3. Returns 14h (Pin Complex – FRONT) for N=4~7. Returns 0Bh (Sum Widget) for N=8~11. 31:0 Not Supported (Returns 00000000h). Table 36. Verb – Get Processing State (Verb ID=F03h) 31:0 Not Supported (Returns 00000000h). Table 37. Verb – Set Processing State (Verb ID=703h)
Table 38. Verb – Get Coefficient Index (Verb ID=Dh) 31:16 Reserved. Read as 0’s. 31:0 Not Supported (Returns 00000000h). Table 39. Verb – Set Coefficient Index (Verb ID=5h) Table 40. Verb – Get Processing Coefficient (Verb ID=Ch) 31:16 Reserved. Read as 0’s. 15:0 Processing Coefficient.
31:0 Not Supported (Returns 00000000h). Table 41. Verb – Set Processing Coefficient (Verb ID=4h) This verb is used to get gain/attenuation settings from each widget. Table 42. Verb – Get Amplifier Gain (Verb ID=Bh) 3:0 Index[3:0] for Input Source. Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.
7.1+2 Channel HD Audio Codec with Content Protection 43 Track ID: JATR-8275-15 Rev. 1.0 Codec Response for 08h (LINE ADC) and 09h (MIX ADC) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain’. Inpu t Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0]. 7-bit step value (0~63) specifying the volume from –17.25dB~+30dB in 0.75dB steps Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute) Codec Response for NID=0Bh (MIXER Sum Widget) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain ’. Input Amplifier Mute. 0: Unmute 1: Mute (Default for all Index) Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0’s (No Output Amplifier Mute) Codec Response for NID=0Ch~0Fh and 26h (Sum Widget: FRONT, SURR, CEN/LFE, SIDESURR, FOUT Sum) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain’. Inpu t Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain). Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain). Codec Response for NID=02h ~ 05h and 25h (DAC Widget: FRONT, SURR, CEN/LFE, SIDESURR, FOUT DAC) Bit Description 31:8 0’s. 7 Bit 15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Mute). Bit 15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute). 6:0 Bit 15 is 0 in ‘Get Amplifier Gain’. Read as 0’s (No Input Amplifier Mute). Bit 15 is 1 in ‘Get Amplifier Gain’. Output Amplifier Gain [6:0]. 7-bit step value (0~87) specifying the volume from –65.25dB~0dB in 0.75dB steps.
7.1+2 Channel HD Audio Codec with Content Protection 44 Track ID: JATR-8275-15 Rev. 1.0 Codec Response for NID=14h~17h (Pin Complex: FRONT/SURR/CENLFE/SIDESURR) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 Bit-15 is 1 in ‘Get Amplifier Gain’. Output Amplifier Mute, 0:Unmute, 1:Mute (NID=14h~17h,Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0’s Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain) Codec Response for NID=18h~1Bh (Pin Complex: MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 Bit-15 is 1 in ‘Get Amplifier Gain’. Output Amplifier Mute, 0:Unmute, 1:Mute (NID=18h~1Bh,Default=1) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Input Amplifier Gain [6:0]. 7-bit step value (0~3) specifying the volume from 0dB~30dB in 10dB steps. Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Gain) Codec Response for NID=22h and 23h (Sum Widget) Bit Description 31:8 0’s 7 Bit-15 is 0 in ‘Get Amplifier Gain’. Inpu t Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in ‘Get Amplifier Gain’. Read as 0 (No Input Amplifier Gain) Codec Response to Other NID Bit Description 31:0 Not Supported (Returns 00000000h).
This verb is used to set amplifier gain/attenuation in each widget. Table 43. Verb – Set Amplifier Gain (Verb ID=3h) ‘1’ indicates output amplifier gain will be set. ‘1’ indicates input amplifier gain will be set. ‘1’ indicates left amplifier gain will be set. ‘1’ indicates right amplifier gain will be set. 11:8 Index Offset (for Input Amplifiers on Sum Widgets and Selector Widgets). A 7-bit step value specifying the amplifier gain.
Table 44. Verb – Get Converter Format (Verb ID=Ah) DAC S/PDIF-OUT, S/PDIF-OUT2). 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV).
Table 45. Verb – Set Converter Format (Verb ID=2h) 13:11 Sample Base Rate Multiple (MULT). 10:8 Sample Base Rate Divisor (DIV).
Table 46. Verb – Get Power State (Verb ID=F05h)
10 PS-SettingReset
0: Setting of widgets has been reset during a low power state. 1: Settings that were changed from the defaults have been reset to their default during a low power state.
9 PS-ClkStopOk
0: No capability to operate normally with BCLK stop. 1: Operate properly with no BCLK. Only Audio Function Group (NID=01h) supports this setting.
8 PS-Error
31:0 Not Supported (Returns 00000000h).
Table 47. Verb – Set Power State (Verb ID=705h) 5:4 PS-Act. Actual Power State [1:0]. PS-Act indicates the actual power state of the referenced node. 1:0 PS-Set. Set Power State [1:0]. Table 48. Verb – Get Converter Stream, Channel (Verb ID=F06h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 31:0 Not Supported (Returns 00000000h).
Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h) The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. (NID=08h, 09h). Other widgets will ignore this verb. Table 50. Verb – Get Pin Widget Control (Verb ID=F07h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O Unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O Unit). 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O Unit). 2:0 VrefEn (Vrefout Enable Control). 31:0 Not Supported (Returns 00000000h).
Table 51. Verb – Set Pin Widget Control (Verb ID=707h) 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O Unit). 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O Unit). 5 In Enable (Input Buffer Enable, EN_IBUF for an I/O Unit). 2:0 VrefEn (Vrefout Enable Control).
unsolicited response to inform software of a real-time event. Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h) 7 Unsolicited Response is Enabled. 3:0 Assigned Tag for Unsolicited Response. The tag[3:0] is assigned by software to determine which widget generates unsolicited responses. 31:0 Not Supported (Returns 00000000h). Enables a widget to generate an unsolicited response. Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h) 7 Enable Unsolicited Response. 3:0 Tag for Unsolicited Response.
Returns the Presence Detect status and the impedance of a device attached to the pin. Table 54. Verb – Get Pin Sense (Verb ID=F09h) The ALC1150 does not support hardware impedance detection. This field is read as 0s. 31:0 Not Supported (Returns 00000000h). Table 55. Verb – Execute Pin Sense (Verb ID=709h) 0 Right (Ring) Channel Select. The ALC1150 does not support hardware impedance sensing and will ignore this control.
Table 56. Verb – Get Volume Knob (Verb ID=F0Fh) 1: The volume generated by external HW volume control will directly affect the volume of the amplifier. Note: The ALC1150 does not support Volume Knob Widget and will ignore this verb and respond with 0’ s. Table 57. Verb – Set Volume Knob (Verb ID=70Fh) 1: The volume generated by external HW volume control will directly affect the volume of the amplifier. Note: The ALC1150 does not support Volume Knob Widget and will ignore this verb and respond with 0’ s.
Reads the 32-bit sticky register for each Pin Widget configured by software. Table 58. Verb – Get Configuration Default (Verb ID=F1Ch) 31:0 32-Bit Configuration Information for Each Pin Widget. Default value for each pin widget.
Table 59. Default Configuration in Chip (14h~1Bh) Table 60. Default Configuration in Chip (1Eh , 11h)
1Eh, e.g., placement and expected default device. Table 61. Verb – Set Configuration Default Bytes 0, 1, 2, 3 widgets will ignore this verb. Table 62. Verb – Get BEEP Generator (Verb ID= F0Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255×4)=47Hz. The highest tone is 48kHz/(1×4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: The ALC1150 does not support Get BEEP Generator and will ignore this verb and respond with 0’ s.
Table 63. Verb – Set BEEP Generator (Verb ID= 70Ah) 7:0 Frequency Divider, F[7:0]. The lowest tone is 48kHz/(255×4)=47Hz. The highest tone is 48kHz/(1×4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: The ALC1150 does not support Set BEEP Generator and will ignore this verb and respond with 0’ s. Table 64. Verb – Get GPIO Data (Verb ID= F15h) The value written (output) or sensed (input) on the corresponding pin if it is enabled.
Table 65. Verb – Set GPIO Data (Verb ID= 715h) The value written determines the value driven on a pin that is configured as an output pin. Table 66. Verb – Get GPIO Enable Mask (Verb ID= F16h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 67. Verb – Set GPIO Enable Mask (Verb ID=716h) Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 68. Verb – Get GPIO Direction (Verb ID=F17h) 1:0 GPIO[1:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 69. Verb – Set GPIO Direction (Verb ID=717h) 1:0 GPIO[1:0] Direction Control. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Table 70. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) 1:0 GPIO[1:0] Unsolicited Enable Mask. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Table 71. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) 1:0 GPIO[1:0] Unsolicited Enable Mask. Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Response’ for NID=01h are enabled. Table 72. Verb – Function Reset (Verb ID=7FFh) Note: The Function Reset command causes all widgets in the ALC1150 to return to their power on default state.
Table 73. Verb – Get Digital Converter Control 1, 2, 3, 4 (Verb ID=F0Dh, F0Eh, F3Eh, F3Fh) 22:20 Reserved. Read as 0’s. Not supported in the ALC1150, read as 0’s. 14:8 CC[6:0] (Category Code). 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (Control V Bit and Data in Sub-Frame). 1 V for Validity Control (Control V Bit and Data in Sub-Frame).
Table 74. Verb – Set Digital Converter Control 1, 2, 3, 4 (Verb ID=70Dh, 70Eh, 73Eh, 73Fh) 6 PRO (Professional or Consumer Format). 5 /AUDIO (Non-Audio Data Type). 2 VCFG for Validity Control (Control V Bit and Data in Sub-Frame). 1 V for Validity Control (Control V Bit and Data in Sub-Frame). 6:0 CC[6:0] (Category Code).
32-bit Read/Write register for Audio Function Group (NID=01h). Table 75. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) 31:16 Subsystem ID[23:8] (Default=10ECh). 15:8 Subsystem ID[7:0] (Default=09h). 7:0 Assembly ID[7:0] (Default=00h).
Table 76. Verb – Set Subsystem ID [31:0] Table 77. Verb – Get EAPD Control (Verb ID=F0Ch) 2 L-R Swap. The ALC1150 does not support swapping left and right channels. Read as 0. 0 Bridge Tied Load (BTL) Enable. The ALC1150 does not support BTL output. Read as 0.
Table 78. Verb – Set EAPD Co ntrol (Verb ID=70Ch for Set) 7:3 Reserved. Written Data is Ignored. 2 L-R Swap. The ALC1150 does not support swapping left and right channels, written data is ignored. 0 Bridge Tied Load (BTL) Enable. The ALC1150 does not support BTL output. Written data is ignored.
- Electrical Characteristics
Table 79. Absolute Maximum Ratings AVDD should contact Realtek technical support representatives for special testing support. DVDD-IO= 1.5V±5%/3.3V±5%, DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load. Table 80. Threshold Voltage
Table 81. Digital Filter Characteristics DVDD=3.3V, Tambient=25°C, with 75Ω external load. Table 82. SPDIF Output Characteristics
Table 83. Link Reset and Initialization Timing
4 BCLK 4 BCLK >= 4 BCLK
Figure 15. Link Reset and Initialization Timing
Table 84. Link Timing Parameters at the Codec Figure 16. Link Signals Timing
Table 85. SPDIF Output Timing Note 1: Bit parameters for 48kHz sample rate of SPDIF-OUT. Figure 17. Output Timing The ALC1150 does not support test mode or Automatic Test Equipment (ATE) mode.
- 1kHz Input Sine Wave; Sampling Frequency=48kHz; 0dB=1Vrms
- 10KΩ/50pF Load; Test Bench Characterization BW:10Hz~22kHz
Table 86. Analog Performance
(www.realtek.com) without modifying this datasheet. the rear panel, and with two re-tasking analog jacks on the front panel. Table 87. Desktop System FRONT (Port-D) 35, 36 Rear Panel Front Channel Line Output and Amplified Output. SURR (Port-A) 39, 41 Rear Panel Surround Channel Line Output. CENTER/LFE (Port-G) 43, 44 Rear Panel Center and Low Frequency (Sub-Woofer) Channel Line Output. SIDE (Port-H) 45, 46 Rear Panel Side Surround Channel Line Output. MIC1 (Port-B) 21, 22 Rear Panel Analog Microphone Input. LINE1 (Port-C) 23, 24 Rear Panel Analog Line Input.
Figure 18. Filter Connection
Figure 19. Front Panel Header and Front Panel Module Connection
In standby mode the ALC1150 turns on DC bias on all analog input and output ports (NID=14h~1Bh). Table 88 shows the DC bias state when Standby mode is enabled. Table 88. Standby Mode
7.1+2 Channel HD Audio Codec with Content Protection 79 Track ID: JATR-8275-15 Rev. 1.0 12. Mechanical Dimensions MQFN48 (6mm x6mm) Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom Max A3 0.20 REF 0.008 REF D/E 6.00BSC 0.236BSC e 0.40BSC 0.016BSC Notes. CONTROLLING DIMENSION: MILLIMETER (mm). REFERENCE DOCUMENT: JEDEC MO-220
Table 89. Ordering Information Note: See page 6 for ‘Green’ package and version identification.
- Please contact a Realtek sales representative for sample availability.