54ACT14 SS | Alldatasheet
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Advanced CMOS TTL Input – 54ACT14 Hex Schmitt-Trigger Inverter with LSTTL compatible inputs in bare die form Rev 1.0 11/03/19 Die Size (Unsawn) 1270 x 110 50 x 43 µm mils Minimum Bond Pad Size 70 x 70 2.76 x 2.76 µm mils Die Thickness 280 (±20) 11.02 (±0.79) µm mils Top Metal Composition Al-Si-Cu Back Metal Composition N/A – Bare Si Schmitt Trigger Inputs TTL & CMOS compatible Input Levels Outputs Sink/Source 24mA Outputs directly inter face CMOS, NMOS and TTL Low power dissipation: I CC 2µA max at 25°C High noise immunity Functionally compatible with bipolar 54F14 Full Military Temperature Range Features:
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection
Description
“ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 280µm(11 Mils) – On request Assembled into Ceramic Package – On request The 54ACT14 Hex Schmitt-Trigger Inverter is fabricated using an advanced CMOS process combining LSTTL speed with CMOS low power consumption while delivering high output drive. The device performs the Boolean function Y = Ᾱ in positive logic. Device inputs directly accept LSTTL or CMOS. Schmitt-Trigger inputs transform slow input rise and fall times into sharply defined jitter-free output signals. Due to the hysteresis voltage of the Schmitt trigger, the 54ACT14 is useful in noisy environments. All inputs are protected against ESD and excess voltage transients. Die Dimensions in µm (mils) 1270 (50) 1100 (43) Mechanical Specification Page 1 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com Advanced CMOS TTL Input – 54ACT14 Rev 1.0 11/03/19 COORDINATES (µm) PAD FUNCTION X Y 1 1A -502 -263.5 2 1Y -364.9 -410 3 2A -157.7 -410 4 2Y 188.9 -410 5 3A 413 -410 6 3Y 495 -298
7 GND 495 -140
8 GND 495 140
11 5Y 188.9 410 12 5A -157.7 410 13 6Y -364.9 410 14 6A -495 263 15 VCC -495 64.2 16 VCC -495 -64.2 CHIP BACK IS ISOLATED Pad Layout and Functions 1270µm (50 mils) 1100µm (43.31 mils) Function Table INPUTS A OUTPUT Y H L L H H = High level (steady state) L = Low level (steady state) Pad 15,15 = VCC Pad 7,8 = GND Y = Ᾱ 0,0 Logic Diagram 2 3 4 5 10111213 DIE ID A ll data sheet.com
www.siliconsupplies.com Advanced CMOS TTL Input – 54ACT14 Rev 1.0 11/03/19 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Input Rise or Fall rate3 (except Schmitt Inputs) tr, tf - 20 ns/V Output Current – High IOH - -24 mA Output Current – Low IOL - 24 mA Recommended Operating Conditions2 (Voltages Referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±50 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Storage Temperature Range TSTG -65 to 150 °C 2. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 3. VIN from 0.8V to 2.0V LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 4.5V 2.0 2.0 2.0 Maximum Positive- Going Input Threshold Voltage VT+ MAX 5.5V 2.1 2.1 2.1 V 4.5V 1.2 1.2 1.2 Minimum Positive- Going Input Threshold Voltage VT+ MIN 5.5V 1.4 1.4 1.4 V 4.5V 1.2 1.2 1.2 Maximum Negative-Going Input Threshold Voltage VT- MAX 5.5V 1.4 1.4 1.4 V 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. A ll data sheet.com
Advanced CMOS TTL Input – 54ACT14 Rev 1.0 11/03/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS FULL RANGE4 25°C 85°C UNITS 4.5V 0.6 0.6 0.6 Minimum Negative- Going Input Threshold Voltage VT- MIN 5.5V V 0.8 0.8 0.8 4.5V 1.4 1.4 1.4 Maximum Hysteresis Voltage5 VH MAX 5.5V 1.6 1.6 1.6 V 4.5V 0.4 0.4 0.4 Minimum Hysteresis Voltage5 VH MIN 5.5V 0.5 0.5 0.5 V 4.5V 4.4 4.4 4.4 5.5V VIN = VT+ IOUT = -50µA 5.4 5.4 5.4 V 4.5V 3.86 3.76 3.7 5.5V VIN = VT+ IOUT = -24mA 4.86 4.76 4.7 V Minimum High-Level Output Voltage VOH 5.5V VIN = VT+ IOH = -50mA5 3.85 3.85 3.85 V 4.5V 0.1 0.1 0.1 5.5V VIN = VT- IOL = 50µA 0.1 0.1 0.1 V 4.5V 0.36 0.44 0.5 5.5V VIN = VT- IOL = 24mA 0.36 0.44 0.5 V Maximum Low-Level Output Voltage VOL 5.5V VIN = VT- IOL = 50Ma6 1.65 1.65 1.65 V Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 5.5V VIN = VCC or GND, IOUT = 0µA 2 20 40 µA Maximum Additional ICC / Input7 ΔICC 5.5V One input at 3.4V, Other input at GND or VCC 0.6 1.5 1.6 mA 5. VH MIN > (VT+ MIN) - (VT- MAX); VH MAX = (VT+ MAX)+(VT- MIN) 6. Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. 7. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0V or VCC LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C tPLH 5.0V 11.5 12.5 14 Maximum Propagation Delay, Input A to Output Y (Figure 1) tPHL 5.0V CL = 50pF ns 10 11 13 Page 4 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com Advanced CMOS TTL Input – 54ACT14 Rev 1.0 11/03/19 Capacitance8 (VCC = 5V, Tj = 25°C) PARAMETER DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. SYMBOL VCC CONDITIONS TYPICAL UNITS VIN = VCC Input Capacitance CIN 5V or GND 4.5 pF Power Dissipation CL = 50pF, Capacitance CPD 5V f = 1 MHz 45 pF 8. Not production tested in die form, characterized by chip design and tested in package. Figure 1 – Propagation Delay, Transition Timing Switching Waveform Test Circuit OUTPUT * Includes all probe and jig capacitance ½ * VCC ½ * VCC ½ * VCC ½ * VCC INPUT OUTPUT 500Ω tPLH tPHL CL* DUT A ll data sheet.com