ACPM-7868

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Document overview

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Technical content

Features

/g120 Quad Band GSM / Linear EDGE PA /g120 Small Size, Low Profile (5 x 5 x 0.9 mm) /g120 Extremely low quiescent current /g120 Digital power mode control for higher efficiency /g120 4 modes for Low Band (HPM, MPM, LPM, and ULPM) /g120 3 modes for High Band (HPM, LPM and ULPM) /g120 16-pin surface mounting package /g120 Internal 50 /g58 matching networks for both RF input and output /g120 Green (Lead-free and RoHS compliant)

Applications

/g120 Quad-band GSM and EDGE

Ordering Information

Part Number Number of Devices Container ACPM-7868-TR1 1000 178 mm (7”) Tape/Reel ACPM-7868-BLK 100 Bulk

Description Min Typ Max Unit Associated Pins RF Input Power * – 15 dBm RFIn_LB, RFIn_HB DC Supply Voltage 0 5.5 V Vbatt, Vcc Enable Voltage 0 3.3 V Ven_LB, Ven_HL Mode Control Voltage 0 3.3 V Vmode0, Vmod1 Storage Temperature -55 +125 °C * under 50 /g58 Notes: 1. No damage assuming only one parameter is set at limit at a time with all other parameters set at within recommended operatin g condition. 2. Operation of any single parameter outside these conditions may cause permanent damage or affect device reliability. Operating Condition Description Symbol Min Typ. Max Unit DC Supply Voltage 3.0 3.5 4.8 V Enable Voltage (Ven) LOW HIGH 1.35 1.8 0.5 2.9 V V Mode Control Voltage (Vmode0, Vmode1) LOW HIGH 1.35 1.8 0.5 2.9 V V Case Temperature -25 +90 °C Control Logic Table for each Modes of Operation Power Mode Ven_LB Ven_HB Vmode0 Vmode1 Power Down Low Low X X Low Band – High Power Mode (HPM) High Low Low Low Low Band – Medium Power Mode (MPM) High Low Low High Low Band – Low Power Mode (LPM) High Low High Low Low Band – Ultra Low Power Mode (ULPM) High Low High High High Band – High Power Mode (HPM) Low High Low Low High Band – Low Power Mode (LPM) Low High High Low High Band – Ultra Low Power Mode (ULPM) Low High High High Recommended Power Levels for each Modes of Operation Power Mode GMSK EDGE Low Band – High Power Mode 30.5 dBm < Pout ≤ Psat 23 dBm < Pout ≤ 29 dBm Low Band – Medium Power Mode 16 dBm < Pout ≤ 30.5 dBm 10 dBm < Pout ≤ 23 dBm Low Band – Low Power Mode Pout ≤ 16 dBm Pout ≤ 10 dBm Low Band – Ultra Low Power Mode Pout ≤ 16 dBm – High Band – High Power Mode 17 dBm < Pout ≤ Psat 16dBm < Pout ≤ 28 dBm High Band – Low Power Mode 11 dBm < Pout ≤ 17 dBm Pout ≤ 16 dBm High Band – Ultra Low Power Mode Pout ≤ 11 dBm –

GSM850/GSM900 PA performance specifications – Conditions: Vbatt and Vcc = 3.5 V, pulse width = 1154 /g80s, duty cycle = 25%, Ven_LB = High, T = 25° C other wise specified Parameter Condition Min Typ Max Unit Operating Frequency Range GSM850 GSM900 824 880 849 915 MHz MHz Quiescent Current High power mode 120 150 180 mA Medium power mode 70 90 110 mA Low Power mode 6 8.5 11 mA Ultra low power mode 6 8.5 11 mA Maximum Output Power GMSK High power mode 34.5 35 dBm GMSK High power mode (degraded power for over Vcc, over Temp) 32.5 dBm EDGE High power mode (RMS power) 29 29.5 dBm GMSK Medium power mode 30.5 31 dBm GMSK Medium power mode (over Vcc, over Temp) 28.5 dBm EDGE Medium power mode (RMS power) 23 dBm GMSK Low power mode (over Vcc, over Temp) 14 16 dBm EDGE Low power mode (RMS power) 10 dBm GMSK Ultra low power mode (over Vcc, over Temp) 14 16 dBm Power Added Efficiency GMSK High power mode, Po = max 48 52 % EDGE high power mode, Po = 29 dBm 25 28 % GMSK medium power mode, Po = 30.5 dBm 33 36 % Low Power mode , Po = 10 dBm 5 8 % Ultra low power mode, Po = 8 dBm 4 6 % Gain High power mode, Po = 34.5 dBm 25.5 32 dB High power mode, Po = 33.5 dBm 27 32 dB Medium power mode, Po = 30.5 dBm 23.5 31 dB Medium power mode, Po = 28.5 dBm 26.5 31 dB Low Power mode, Po = 10 dBm 10 17 dB Ultra low power mode, Po = 8 dBm 10 17 dB Gain Compression High power mode, Po = 23.5 dBm ~ 33.5 dBm 0.8 1.3 dB Gain Variation – Tc and Vbatt (all modes of operation) -25 ≤ Tc ≤ 90 /g58 3.2 V ≤ Vbatt ≤ 4.2 V (fixed Pin at 3.5 V, 25° C condition) -2.5 +2.5 dB EDGE ACPR High Power Mode Po ≤ 25 dBm** Medium Power Mode Po ≤ 23 dBm Low Power Mode Po ≤ 10 dBm ±400 kHz dBc or dBm* -57 -40 dBc/30 kHz dBm/30 kHz ±600 kHz dBc or dBm* -64 -55 dBc/30 kHz dBm/30 kHz ±3000 kHz dBc or dBm* -68 -50 dBc/100 kHz dBm/100 kHz ±6000 kHz dBc or dBm* -74 -59 dBc/100 kHz dBm/100 kHz

GSM850/GSM900 PA performance specifications (Continued) Parameter Condition Min Typ Max Unit EDGE EVM High Power Mode Po ≤ 25 dBm** Medium Power Mode Po ≤ 23 dBm Low Power Mode Po ≤ 10 dBm 23% Output power Noise High power mode Medium power mode Rx = 869-882 MHz, Tx = 837 MHz -85 -84 dBm/100 kHz Rx = 882-894 MHz, Tx = 837 MHz -86 -85 dBm/100 kHz Rx = 925-935 MHz, Tx = 898 MHz -79 dBm/100 kHz Rx = 935-960 MHz, Tx = 898 MHz -85 dBm/100 kHz Harmonics Po < 35 dBm 2 fo -10 dBm 3 ~13 fo -15 dBm Stability F<1 GHz; 8:1 VSWR -36 dBm F>2 GHz, 8:1 VSWR -30 dBm Ruggedness All load phases 10:1 Input Impedance High power mode, Medium power mode 2:1 Low power mode, Ultra low power mode 3:1 Current under mismatch condition VSWR = 5:1, all phase angles, post PA loss = 1.5 dB, Pin = 9 dBm, Vcc = 3.7 V 2.7 3.3 A Forward Isolation Ven_LB = Low, Pin = -10 dBm -30 dBm Cross Isolation Spurious at HB Output, Low Band signal (fundamental) Ven_LB = High -15 dBm dBm * Note 1: If the dBc specification is tighter than the dBm limit, then the dBm limit shall be applied instead. ** Note 2: EDGE operation at high power mode can be extended up to 29 dBm in combination with the pre-distortion scheme of tran sceiver.

DCS1800/PCS1900 PA performance specifications – Conditions: Vbatt and Vcc = 3.5 V, pulse width = 1154 /g80s, duty cycle = 25%, Ven_HB = High, T = 25° C other wise specified Parameter Condition Min Typ Max Unit Operating Frequency Range DCS1800 PCS1900 1710 1850 1785 1910 MHz MHz Quiescent Current High power mode 130 170 210 mA Low power mode 30 45 60 mA Ultra Low Power mode 12 15 20 mA Maximum Output Power GMSK High power mode 32.5 33 dBm GMSK High power mode (degraded power for over Vcc, over Temp) 30.5 dBm EDGE High power mode (RMS power) 28 28.5 dBm GMSK Low power mode (over Vcc, over Temp) 17.8 19.8 dBm EDGE Low power mode (RMS power) 16 dBm GMSK Ultra low power mode (over Vcc, over Temp) 11.8 13.8 dBm Power Added Efficiency GMSK High power mode, Po = Pmax 48 53 % EDGE high power mode, Po = 28.5 dBm 28.5 30 % Low Power mode , Po = 16 dBm 8 10 % Ultra low power mode, Po = 8 dBm 4 6 % Gain High power mode, Po = 32 dBm 25.5 31 dB High power mode, Po = 28.5 dBm 26.5 32 dB Low Power mode, Po = 16 dBm 13 22 dB Ultra low power mode, Po = 8 dBm 10 20 dB Gain Variation – Tc and Vbatt (all modes of operation) -25 ≤ Tc ≤ 90 /g58 3.2 V ≤ Vbatt ≤ 4.2 V (fixed Pin at 3.5 V, 25° C condition) -2.5 +2.5 dB EDGE ACPR High Power Mode Po ≤ 24 dBm** Low Power Mode Po ≤ 16 dBm ±400 kHz dBc or dBm* -57 -40 dBc/30 kHz dBm/30 kHz ±600 kHz dBc or dBm* -64 -60 dBc/30 kHz dBm/30 kHz ±1800 kHz dBc or dBm* -65 -55 dBc/100 kHz dBm/100 kHz ±3000 kHz dBc or dBm* -68 -55 dBc/100 kHz dBm/100 kHz ±6000 kHz dBc or dBm* -76 -55 dBc/100 kHz dBm/100 kHz EDGE EVM High Power Mode Po ≤ 24 dBm** Low Power Mode Po ≤ 16 dBm 23%

DCS1800/PCS1900 PA performance specifications (Continued) Parameter Condition Min Typ Max Unit Output power Noise Po > 28 dBm Rx = 1805-1880 MHz -83 dBm/100 kHz Rx = 1930-1990 MHz -83 dBm/100 kHz Harmonics Po ≤ 32.5 dBm 2 fo -10 dBm 3 – 7 fo -15 dBm Stability F<1 GHz; 8:1 VSWR -36 dBm F>2 GHz, 8:1 VSWR -30 dBm Ruggedness All load phases 10:1 Input Impedance High power mode, Ultra low power mode 2:1 Low power mode 3:1 Current under mismatch condition VSWR = 5:1, all phase angles, post PA loss = 1.5 dB, Pin = 9 dBm, Vcc = 3.7 V 2 2.5 A Forward Isolation Ven_HB = Low, Pin = -10 dBm -30 dBm Cross Isolation Spurious at LB Output, Low Band signal (fundamental) Ven_HB = High -20 dBm dBm * Note 1: If the dBc specification is tighter than the dBm limit, then the dBm limit shall be applied instead. ** Note 2: EDGE operation at high power mode can be extended up to 28dBm in combination with the pre-distortion scheme of trans ceiver.

5 mm X 5 mm Package Footprint, X-Ray Top View Package Dimension Details (All dimensions are in millimeters) X-Ray Top View DCS1800/PCS1900 RF_OUT DCS1800/PCS1900 RF_IN GSM850/GSM900 RF_IN Vbatt HB_EN VMODE0 VMODE1 GND VCC LB_EN GSM850/GSM900 RF_OUT 11 6 21 5 31 4 41 3 51 2 61 1 71 0 0.30 0.30 0.30 0.3 0.125 0.10 0.375 0.375 0.625 0.30 0.10 0.25 0.25 A 0.375 ± 0.05 0.375 ± 0.05 - A (Pad size Tolerance)

Land Pattern Recommendations Metallization Solder Mask Opening Solder Paste Stencil Aperture 0.30 0.625 0.375 0.575 0.475 Ø 0.3mm on 0.5mm pitch 0.50 3.45 0.675 0.475 0.625 3.45 0.525 2.30 0.55 0.575 0.375 0.625 3.05 0.475 2.10 0.50 0.35 0.35

Evaluation Board Schematic Evaluation Board Assembly Diagram DNI DNI

2 Vbatt

3 Ven_HB

4 Vmode0

1 RFin_HB

5 Vmode1

6 Ven_LB

7 GND

8 RFin_LB

RFout_HB 16 GND 14 Vcc 13 RFout_LB 9 GND 10 GND 15 GND 12 GND 11 2.2 nF 47 /g80F

All dimensions are in millimeters 5.0 ± 0.1 5.0 ± 0.1 Pin 1 Mark 0.5 0.9 ± 0.1 Manufacturing Part Number Lot Number P Manufacturing Info YY Manufacturing Year WW Work Week AAAAA Asse mbly Lot Number Pin 1 Mark AVAGO ACPM-7868 PYYWW AAAAA

Notes: 1. 10 sprocket hot pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm. 3. Material: Black conductive Polystyrene. 4. Ao and Bo measured on a plane 0.3 mm above the bottom of the pocket. 5. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. 7. All dimensions are in millimeters. AVAGO ACPM-7868 PYYWW AAAAA Component Orientation

ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environ- ment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at Moisture Classification Level and Floor Life MSL Level Floor Life (out of bag) at factory ambient =< 30°C/60% RH or as stated

1 Unlimited at =< 30°C/85% RH

6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label Note : 1. The MSL Level is marked on the MSL Label on each shipping bag. various temperatures and relative humidity, and times. After soak, the components are subjected to three con- secutive simulated reflows. The out of bag exposure time maximum limits are deter- mined by the classification test describe below which cor- responds to a MSL classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033. ACPM-7868 is MSL3. Thus, according to the J-STD-033 p.10, the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classification reflow temperature for the ACPM-7868 is targeted at 260°C +0/-5°C. Figure and table on next page show typical SMT profile for maximum temperature of 260 +0/-5°C.

Reflow Profile Recommendations Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C Time Temperature Tp TL tp tL t 25°C to Peak Ramp-up ts Tsmin Ramp-down Prehe at Critic al Zone TL to Tp Tsmax Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C Profile Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3°C/sec max 3°C/sec max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 100°C 150°C 60-120 sec 150°C 200°C 60-120 sec Tsmax to TL – Ramp-up Rate 3°C/sec max Time maintained above: – Temperature (TL) – Time (TL) 183°C 60-150 sec 217°C 60-150 sec Peak temperature (Tp) 240 +0/-5°C 260 +0/-5°C Time within 5°C of actual Peak Temperature (tp) 10-30 sec 20-40 sec Ramp-down Rate 6°C/sec max 6°C/sec max Time 25°C to Peak Temperature 6 min max. 8 min max.

Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at <40°C and 90% relative humidity (RH) J-STD-033 p.6. Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within 168 hours with factory conditions <30°C and 60% RH as listed in the Table 5-1 on the J-STD-020D p.6. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the condi- tions above has not been satisfied. The baking conditions are listed in the Table 4-1 on the J-STD-033 p.8. CAUTION Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200°C. This method will minimize moisture related component damage. If any component temperature exceeds 200°C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. Removal for Failure Analysis Not following the above requirements may cause moisture/ reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards Some SMD packages and board materials are not able to withstand long duration bakes at 125°C. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125°C. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake tem- perature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 andIPC-7721. Derating due to Factory Environmental Conditions Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient envi- ronmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in table of Moisture Classification Level and Floor Life. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30°C/60% RH. A solution for address- ing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table on follwoing page lists equivalent derated floor lives for humidities ranging from 20-90% RH for three tempera- ture, 20°C, 25°C, and 30°C. This table is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating this table: 1. Activation Energy for diffusion = 0.35eV (smallest known value). 2. For ≤60% RH, use Diffusivity = 0.121exp ( -0.35eV/kT) mm2/s (this used smallest known Diffusivity @ 30°C). 3. For >60% RH, use Diffusivity = 1.320exp ( -0.35eV/kT) mm2/s (this used largest known Diffusivity @ 30°C).

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-2665EN - January 5, 2011 Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C, 35°C For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity Maximum Percent Relative Humidity Package Type and Body Thickness Moisture Sensitivity Level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% Body Thickness ≥3.1 mm Including PQFPs >84 pin, PLCCs (square) All MQFPs or All BGAs ≥1 mm Level 2a ∞ 124 167 231 103 35°C 30°C 25°C 20°C Level 3 ∞ 35°C 30°C 25°C 20°C Level 4 ∞ 35°C 30°C 25°C 20°C Level 5 ∞ 35°C 30°C 25°C 20°C Level 5a ∞ 35°C 30°C 25°C 20°C Body 2.1 mm ≤ Thickness <3.1 mm including PLCCs (rectangular) 18-32 pin SOICs (wide body) SOICs ≥20 pins, PQFPs ≤80 pins Level 2a ∞ 148 35°C 30°C 25°C 20°C Level 3 ∞ 35°C 30°C 25°C 20°C Level 4 ∞ 35°C 30°C 25°C 20°C Level 5 ∞ 35°C 30°C 25°C 20°C Level 5a ∞ 0.5 0.5 0.5 0.5 35°C 30°C 25°C 20°C Body Thickness <2.1 mm including SOICs <18 pin All TQFPs, TSOPs or All BGAs <1 mm body thickness Level 2a ∞ 0.5 0.5 35°C 30°C 25°C 20°C Level 3 ∞ 0.5 0.5 35°C 30°C 25°C 20°C Level 4 ∞ 0.5 0.5 35°C 30°C 25°C 20°C Level 5 ∞ 0.5 0.5 35°C 30°C 25°C 20°C Level 5a ∞ 0.5 0.5 0.5 35°C 30°C 25°C 20°C